irqchip/renesas-rzv2h: Add RZ/G3E support

The ICU block on the RZ/G3E SoC is almost identical to the one found on
the RZ/V2H SoC, with the following differences:

 - The TINT register base offset is 0x800 instead of zero.
 - The number of GPIO interrupts for TINT selection is 141 instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map.
 - The number of TSSR registers is 16 instead of 8.
 - Each TSSR register can program 2 TINTs instead of 4 TINTs.

Add support for the RZ/G3E driver by filling the rzv2h_hw_info table and
adding LUT for mapping between pin index and TINT selection index.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/all/20250224131253.134199-13-biju.das.jz@bp.renesas.com

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 7bc4397ec149029cf2a4c2ad6327f45306f5ecf7..3d5b5fdf9bde823cc4942961890a009c26e356b1 100644 (file)
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -85,15 +85,19 @@
 
 #define ICU_TINT_EXTRACT_HWIRQ(x)              FIELD_GET(GENMASK(15, 0), (x))
 #define ICU_TINT_EXTRACT_GPIOINT(x)            FIELD_GET(GENMASK(31, 16), (x))
+#define ICU_RZG3E_TINT_OFFSET                  0x800
+#define ICU_RZG3E_TSSEL_MAX_VAL                        0x8c
 #define ICU_RZV2H_TSSEL_MAX_VAL                        0x55
 
 /**
  * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
+ * @tssel_lut:         TINT lookup table
  * @t_offs:            TINT offset
  * @max_tssel:         TSSEL max value
  * @field_width:       TSSR field width
  */
 struct rzv2h_hw_info {
+       const u8        *tssel_lut;
        u16             t_offs;
        u8              max_tssel;
        u8              field_width;
@@ -317,6 +321,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
        if (tint > priv->info->max_tssel)
                return -EINVAL;
 
+       if (priv->info->tssel_lut)
+               tint = priv->info->tssel_lut[tint];
+
        hwirq = irqd_to_hwirq(d);
        tint_nr = hwirq - ICU_TINT_START;
 
@@ -529,18 +536,57 @@ pm_put:
        return ret;
 }
 
+/* Mapping based on port index on Table 4.2-6 and TSSEL bits on Table 4.6-4 */
+static const u8 rzg3e_tssel_lut[] = {
+       81, 82, 83, 84, 85, 86, 87, 88,         /* P00-P07 */
+       89, 90, 91, 92, 93, 94, 95, 96,         /* P10-P17 */
+       111, 112,                               /* P20-P21 */
+       97, 98, 99, 100, 101, 102, 103, 104,    /* P30-P37 */
+       105, 106, 107, 108, 109, 110,           /* P40-P45 */
+       113, 114, 115, 116, 117, 118, 119,      /* P50-P56 */
+       120, 121, 122, 123, 124, 125, 126,      /* P60-P66 */
+       127, 128, 129, 130, 131, 132, 133, 134, /* P70-P77 */
+       135, 136, 137, 138, 139, 140,           /* P80-P85 */
+       43, 44, 45, 46, 47, 48, 49, 50,         /* PA0-PA7 */
+       51, 52, 53, 54, 55, 56, 57, 58,         /* PB0-PB7 */
+       59, 60, 61,                             /* PC0-PC2 */
+       62, 63, 64, 65, 66, 67, 68, 69,         /* PD0-PD7 */
+       70, 71, 72, 73, 74, 75, 76, 77,         /* PE0-PE7 */
+       78, 79, 80,                             /* PF0-PF2 */
+       25, 26, 27, 28, 29, 30, 31, 32,         /* PG0-PG7 */
+       33, 34, 35, 36, 37, 38,                 /* PH0-PH5 */
+       4, 5, 6, 7, 8,                          /* PJ0-PJ4 */
+       39, 40, 41, 42,                         /* PK0-PK3 */
+       9, 10, 11, 12, 21, 22, 23, 24,          /* PL0-PL7 */
+       13, 14, 15, 16, 17, 18, 19, 20,         /* PM0-PM7 */
+       0, 1, 2, 3                              /* PS0-PS3 */
+};
+
+static const struct rzv2h_hw_info rzg3e_hw_params = {
+       .tssel_lut      = rzg3e_tssel_lut,
+       .t_offs         = ICU_RZG3E_TINT_OFFSET,
+       .max_tssel      = ICU_RZG3E_TSSEL_MAX_VAL,
+       .field_width    = 16,
+};
+
 static const struct rzv2h_hw_info rzv2h_hw_params = {
        .t_offs         = 0,
        .max_tssel      = ICU_RZV2H_TSSEL_MAX_VAL,
        .field_width    = 8,
 };
 
+static int rzg3e_icu_init(struct device_node *node, struct device_node *parent)
+{
+       return rzv2h_icu_init_common(node, parent, &rzg3e_hw_params);
+}
+
 static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 {
        return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params);
 }
 
 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
+IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_init)
 IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init)
 IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
 MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");