endif
ifeq ($(CONFIG_RISCV),y)
- @tools/prelink-riscv $@ 0
+ @tools/prelink-riscv $@
endif
quiet_cmd_sym ?= SYM $@
meson-gxbb-nanopi-k2.dtb \
meson-gxbb-p200.dtb \
meson-gxbb-p201.dtb \
+ meson-gxbb-wetek-hub.dtb \
+ meson-gxbb-wetek-play2.dtb \
meson-gxl-s805x-libretech-ac.dtb \
meson-gxl-s905d-libretech-pc.dtb \
meson-gxl-s905w-jethome-jethub-j80.dtb \
meson-gxl-s905x-libretech-cc.dtb \
meson-gxl-s905x-libretech-cc-v2.dtb \
meson-gxl-s905x-p212.dtb \
+ meson-gxm-gt1-ultimate.dtb \
meson-gxm-khadas-vim2.dtb \
meson-gxm-s912-libretech-pc.dtb \
meson-gxm-wetek-core2.dtb \
meson-g12a-radxa-zero.dtb \
meson-g12a-sei510.dtb \
meson-g12a-u200.dtb \
+ meson-g12b-a311d-bananapi-m2s.dtb \
meson-g12b-a311d-khadas-vim3.dtb \
+ meson-g12b-bananapi-cm4-cm4io.dtb \
+ meson-g12b-gsking-x.dtb \
meson-g12b-gtking.dtb \
meson-g12b-gtking-pro.dtb \
- meson-g12b-gsking-x.dtb \
meson-g12b-odroid-go-ultra.dtb \
meson-g12b-odroid-n2.dtb \
meson-g12b-odroid-n2l.dtb \
meson-g12b-odroid-n2-plus.dtb \
+ meson-g12b-radxa-zero2.dtb \
+ meson-sm1-bananapi-m2-pro.dtb \
meson-sm1-bananapi-m5.dtb \
meson-sm1-khadas-vim3l.dtb \
meson-sm1-odroid-c4.dtb \
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-a311d.dtsi"
+#include "meson-g12b-bananapi.dtsi"
+
+/ {
+ compatible = "bananapi,bpi-m2s", "amlogic,a311d", "amlogic,g12b";
+ model = "BananaPi M2S";
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c3;
+ };
+};
+
+/* Camera (CSI) bus */
+&i2c1 {
+ status = "okay";
+ pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>;
+ pinctrl-names = "default";
+};
+
+/* Display (DSI) bus */
+&i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-bananapi-cm4.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b";
+ model = "BananaPi BPI-CM4IO Baseboard with BPI-CM4 Module";
+
+ aliases {
+ ethernet0 = ðmac;
+ i2c0 = &i2c1;
+ i2c1 = &i2c3;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1710000>;
+
+ button-function {
+ label = "Function";
+ linux,code = <KEY_FN>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+
+ hdmi_connector: hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "BPI-CM4IO";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&cecb_AO {
+ status = "okay";
+};
+
+ðmac {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+/* CSI port */
+&i2c1 {
+ status = "okay";
+};
+
+/* DSI port for touchscreen */
+&i2c3 {
+ status = "okay";
+};
+
+/* miniPCIe port with USB + SIM slot */
+&pcie {
+ status = "okay";
+};
+
+&sd_emmc_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+/* Peripheral Only USB-C port */
+&usb {
+ dr_mode = "peripheral";
+
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
+ */
+
+#include "meson-g12b-a311d.dtsi"
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ rtc1 = &vrtc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOAO_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ emmc_1v8: regulator-emmc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc-in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vddio_c: regulator-vddio-c {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_C";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ enable-gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_9 GPIO_OPEN_DRAIN>;
+ gpios-states = <1>;
+
+ states = <1800000 0>,
+ <3300000 1>;
+ };
+
+ vddao_1v8: regulator-vddao-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ vddcpu_a: regulator-vddcpu-a {
+ /*
+ * MP8756GD DC/DC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_A";
+ regulator-min-microvolt = <680000>;
+ regulator-max-microvolt = <1040000>;
+
+ pwm-supply = <&dc_in>;
+
+ pwms = <&pwm_ab 0 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddcpu_b: regulator-vddcpu-b {
+ /*
+ * SY8120B1ABC DC/DC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_B";
+ regulator-min-microvolt = <680000>;
+ regulator-max-microvolt = <1040000>;
+
+ pwm-supply = <&dc_in>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu100 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu101 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu102 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu103 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+/* Ethernet to be enabled in baseboard DT */
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ phy-mode = "rgmii-txid";
+ phy-handle = <&external_phy>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+/* HDMI to be enabled in baseboard DT */
+&hdmi_tx {
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&dc_in>;
+};
+
+/* "Camera" I2C bus */
+&i2c1 {
+ pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>;
+ pinctrl-names = "default";
+};
+
+/* Main I2C bus */
+&i2c2 {
+ pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>;
+ pinctrl-names = "default";
+};
+
+/* "ID" I2C bus */
+&i2c3 {
+ pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
+ pinctrl-names = "default";
+};
+
+&pcie {
+ reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>;
+};
+
+&pwm_ab {
+ pinctrl-0 = <&pwm_a_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+
+ status = "okay";
+};
+
+&pwm_ef {
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vddao_1v8>;
+
+ status = "okay";
+};
+
+/* on-module SDIO WiFi */
+&sd_emmc_a {
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ sd-uhs-sdr104;
+ max-frequency = <50000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_3v3>;
+
+ status = "okay";
+
+ rtl8822cs: wifi@1 {
+ reg = <1>;
+ };
+};
+
+/* SD card to be enabled in baseboard DT */
+&sd_emmc_b {
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_c>;
+};
+
+/* on-module eMMC */
+&sd_emmc_c {
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_1v8>;
+
+ status = "okay";
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+/* on-module UART BT */
+&uart_A {
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8822cs-bt";
+ enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
+ device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&uart_AO {
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb {
+ phys = <&usb2_phy0>, <&usb2_phy1>;
+ phy-names = "usb2-phy0", "usb2-phy1";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ rtc1 = &vrtc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 4 GiB */
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1710000>;
+
+ button-function {
+ label = "RST";
+ linux,code = <KEY_POWER>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ cooling-min-state = <0>;
+ cooling-max-state = <3>;
+ cooling-levels = <0 120 170 220>;
+ pwms = <&pwm_cd 1 40000 0>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ dc_in: regulator-dc-in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vcc_5v: regulator-vcc-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ };
+
+ vcc_3v3: regulator-vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_1v8: regulator-vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_1v8: regulator-vddao-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ };
+
+ vddcpu_a: regulator-vddcpu-a {
+ compatible = "pwm-regulator";
+ regulator-name = "VDDCPU_A";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+ pwm-supply = <&dc_in>;
+ pwms = <&pwm_ab 0 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddcpu_b: regulator-vddcpu-b {
+ compatible = "pwm-regulator";
+ regulator-name = "VDDCPU_B";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+ pwm-supply = <&vsys_3v3>;
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vsys_3v3: regulator-vsys-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSYS_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ emmc_1v8: regulator-emmc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ usb_pwr: regulator-usb-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "BPI-M2S";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu100 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu101 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu102 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu103 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+/* Main i2c bus */
+&i2c2 {
+ status = "okay";
+ pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>;
+ pinctrl-names = "default";
+};
+
+&pcie {
+ status = "okay";
+ reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>;
+};
+
+&pwm_ab {
+ status = "okay";
+ pinctrl-0 = <&pwm_a_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+};
+
+&pwm_cd {
+ status = "okay";
+ pinctrl-0 = <&pwm_d_x6_pins>;
+ pinctrl-names = "default";
+ pwm-gpios = <&gpio GPIOAO_10 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+ /* enable if WiFi/BT board connected */
+ status = "disabled";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ sd-uhs-sdr104;
+ max-frequency = <50000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vsys_3v3>;
+ vqmmc-supply = <&vddao_1v8>;
+
+ rtl8822cs: wifi@1 {
+ reg = <1>;
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vsys_3v3>;
+ vqmmc-supply = <&vsys_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&emmc_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&uart_A {
+ /* enable if WiFi/BT board connected */
+ status = "disabled";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "realtek,rtl8822cs-bt";
+ enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
+ device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb2_phy0 {
+ phy-supply = <&dc_in>;
+};
+
+&usb2_phy1 {
+ phy-supply = <&usb_pwr>;
+};
+
+&usb3_pcie_phy {
+ phy-supply = <&usb_pwr>;
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "peripheral";
+ phys = <&usb2_phy0>, <&usb2_phy1>;
+ phy-names = "usb2-phy0", "usb2-phy1";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ * Copyright (c) 2022 Radxa Limited
+ * Author: Yuntian Zhang <yt@radxa.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-a311d.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "radxa,zero2", "amlogic,a311d", "amlogic,g12b";
+ model = "Radxa Zero2";
+
+ aliases {
+ serial0 = &uart_AO;
+ serial2 = &uart_A;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+ power-button {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio_ao GPIOAO_3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio GPIOA_12 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ ao_5v: regulator-ao-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vcc_1v8: regulator-vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ /* FIXME: actually controlled by VDDCPU_B_EN */
+ };
+
+ vddao_1v8: regulator-vddao-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+ vddcpu_a: regulator-vddcpu-a {
+ /*
+ * MP8756GD Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_A";
+ regulator-min-microvolt = <730000>;
+ regulator-max-microvolt = <1022000>;
+
+ pwm-supply = <&ao_5v>;
+
+ pwms = <&pwm_ab 0 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddcpu_b: regulator-vddcpu-b {
+ /*
+ * Silergy SY8120B1ABC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_B";
+ regulator-min-microvolt = <730000>;
+ regulator-max-microvolt = <1022000>;
+
+ pwm-supply = <&ao_5v>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "RADXA-ZERO2";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+
+ wifi32k: clock-0 {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu100 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu101 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu102 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu103 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&gpio {
+ gpio-line-names =
+ /* GPIOZ */
+ "PIN_27", "PIN_28", "PIN_7", "PIN_11", "PIN_13", "PIN_15", "PIN_18", "PIN_40",
+ "", "", "", "", "", "", "", "",
+ /* GPIOH */
+ "", "", "", "", "PIN_19", "PIN_21", "PIN_24", "PIN_23",
+ "",
+ /* BOOT */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "EMMC_PWRSEQ", "", "", "",
+ /* GPIOC */
+ "", "", "", "", "", "", "SD_CD", "PIN_36",
+ /* GPIOA */
+ "PIN_32", "PIN_12", "PIN_35", "", "", "PIN_38", "", "",
+ "", "", "", "", "LED_GREEN", "PIN_31", "PIN_3", "PIN_5",
+ /* GPIOX */
+ "", "", "", "", "", "", "SDIO_PWRSEQ", "",
+ "", "", "", "", "", "", "", "",
+ "", "BT_SHUTDOWN", "", "";
+};
+
+&gpio_ao {
+ gpio-line-names =
+ /* GPIOAO */
+ "PIN_8", "PIN_10", "", "BTN_POWER", "", "", "", "PIN_29",
+ "PIN_33", "PIN_37", "FAN", "",
+ /* GPIOE */
+ "", "", "";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&ao_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "disabled";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ab {
+ pinctrl-0 = <&pwm_a_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+ status = "okay";
+};
+
+&pwm_ef {
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+ status = "okay";
+};
+
+&pwm_AO_ab {
+ pinctrl-0 = <&pwm_ao_a_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+ status = "okay";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SDIO */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_1v8>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-s922x.dtsi"
+#include "meson-g12b-bananapi.dtsi"
+
+/ {
+ compatible = "bananapi,bpi-m2s", "amlogic,s922x", "amlogic,g12b";
+ model = "BananaPi M2S";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb-wetek.dtsi"
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+ compatible = "wetek,hub", "amlogic,meson-gxbb";
+ model = "WeTek Hub";
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "WETEK-HUB";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
+};
+
+&ir {
+ linux,rc-map-name = "rc-wetek-hub";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb-wetek.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+ compatible = "wetek,play2", "amlogic,meson-gxbb";
+ model = "WeTek Play 2";
+
+ spdif_dit: audio-codec-0 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+ sound-name-prefix = "DIT";
+ };
+
+ leds {
+ led-wifi {
+ label = "wetek-play:wifi-status";
+ gpios = <&gpio GPIODV_26 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-ethernet {
+ label = "wetek-play:ethernet-status";
+ gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ button {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "WETEK-PLAY2";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-3 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
+
+ codec-0 {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
+ pinctrl-0 = <&spdif_out_y_pins>;
+ pinctrl-names = "default";
+};
+
+&i2c_A {
+ status = "okay";
+ pinctrl-0 = <&i2c_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&ir {
+ linux,rc-map-name = "rc-wetek-play2";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-gx-u-boot.dtsi"
+
+ðmac {
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
+ */
+
+#include "meson-gxbb.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-power {
+ /* red in suspend or power-off */
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ panic-indicator;
+ };
+ };
+
+ usb_pwr: regulator-usb-pwrs {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB_PWR";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+};
+
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+ðmac {
+ status = "okay";
+ pinctrl-0 = <ð_rgmii_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <ð_phy0>;
+ phy-mode = "rgmii";
+
+ amlogic,tx-delay-ns = <2>;
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_15 */
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vddio_ao18>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vcc_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb0_phy {
+ status = "okay";
+ phy-supply = <&usb_pwr>;
+};
+
+&usb0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-gxl-u-boot.dtsi"
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "azw,gt1-ultimate", "amlogic,s912", "amlogic,meson-gxm";
+ model = "Beelink GT1 Ultimate";
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-white {
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ panic-indicator;
+ };
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1710000>;
+
+ button-function {
+ label = "update";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
+ phy-mode = "rgmii";
+};
+
+&external_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_15 */
+ interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&ir {
+ linux,rc-map-name = "rc-beelink-gs1";
+};
+
+&sd_emmc_a {
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ };
+};
--- /dev/null
+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-sm1-u-boot.dtsi"
+
+ðmac {
+ snps,reset-gpio = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-bananapi.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "bananapi,bpi-m2-pro", "amlogic,sm1";
+ model = "Banana Pi BPI-M2-PRO";
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "BPI-M2-PRO";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
/dts-v1/;
-#include "meson-sm1.dtsi"
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include "meson-sm1-bananapi.dtsi"
#include <dt-bindings/sound/meson-g12a-toacodec.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
compatible = "bananapi,bpi-m5", "amlogic,sm1";
model = "Banana Pi BPI-M5";
- adc_keys {
- compatible = "adc-keys";
- io-channels = <&saradc 2>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
-
- key {
- label = "SW3";
- linux,code = <BTN_3>;
- press-threshold-microvolt = <1700000>;
- };
- };
-
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
/* TOFIX: handle CVBS_DET on SARADC channel 0 */
cvbs-connector {
compatible = "composite-video-connector";
};
};
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key {
- label = "SW1";
- linux,code = <BTN_1>;
- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
- interrupt-parent = <&gpio_intc>;
- interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- green {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
- };
-
- blue {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- emmc_1v8: regulator-emmc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "EMMC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- dc_in: regulator-dc_in {
- compatible = "regulator-fixed";
- regulator-name = "DC_IN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vddio_c: regulator-vddio_c {
- compatible = "regulator-gpio";
- regulator-name = "VDDIO_C";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
-
- gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>;
- gpios-states = <1>;
-
- states = <1800000 0>,
- <3300000 1>;
- };
-
- tflash_vdd: regulator-tflash_vdd {
- compatible = "regulator-fixed";
- regulator-name = "TFLASH_VDD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_in>;
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- regulator-always-on;
- };
-
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- vddcpu: regulator-vddcpu {
- /*
- * SY8120B1ABC DC/DC Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU";
- regulator-min-microvolt = <690000>;
- regulator-max-microvolt = <1050000>;
-
- vin-supply = <&dc_in>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* USB Hub Power Enable */
- vl_pwr_en: regulator-vl_pwr_en {
- compatible = "regulator-fixed";
- regulator-name = "VL_PWR_EN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_in>;
-
- gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
sound {
compatible = "amlogic,axg-sound-card";
model = "BPI-M5";
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
- status = "okay";
dai-link-0 {
sound-dai = <&frddr_a>;
status = "okay";
};
-&arb {
- status = "okay";
-};
&clkc_audio {
status = "okay";
};
-&cpu0 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu2 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu3 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
- clock-latency = <50000>;
-};
-
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii-txid";
- phy-handle = <&external_phy>;
-};
-
&frddr_a {
status = "okay";
};
status = "okay";
};
-&gpio {
- gpio-line-names =
- /* GPIOZ */
- "ETH_MDIO", /* GPIOZ_0 */
- "ETH_MDC", /* GPIOZ_1 */
- "ETH_RXCLK", /* GPIOZ_2 */
- "ETH_RX_DV", /* GPIOZ_3 */
- "ETH_RXD0", /* GPIOZ_4 */
- "ETH_RXD1", /* GPIOZ_5 */
- "ETH_RXD2", /* GPIOZ_6 */
- "ETH_RXD3", /* GPIOZ_7 */
- "ETH_TXCLK", /* GPIOZ_8 */
- "ETH_TXEN", /* GPIOZ_9 */
- "ETH_TXD0", /* GPIOZ_10 */
- "ETH_TXD1", /* GPIOZ_11 */
- "ETH_TXD2", /* GPIOZ_12 */
- "ETH_TXD3", /* GPIOZ_13 */
- "ETH_INTR", /* GPIOZ_14 */
- "ETH_NRST", /* GPIOZ_15 */
- /* GPIOH */
- "HDMI_SDA", /* GPIOH_0 */
- "HDMI_SCL", /* GPIOH_1 */
- "HDMI_HPD", /* GPIOH_2 */
- "HDMI_CEC", /* GPIOH_3 */
- "VL-RST_N", /* GPIOH_4 */
- "CON1-P36", /* GPIOH_5 */
- "VL-PWREN", /* GPIOH_6 */
- "WiFi_3V3_1V8", /* GPIOH_7 */
- "TFLASH_VDD_EN", /* GPIOH_8 */
- /* BOOT */
- "eMMC_D0", /* BOOT_0 */
- "eMMC_D1", /* BOOT_1 */
- "eMMC_D2", /* BOOT_2 */
- "eMMC_D3", /* BOOT_3 */
- "eMMC_D4", /* BOOT_4 */
- "eMMC_D5", /* BOOT_5 */
- "eMMC_D6", /* BOOT_6 */
- "eMMC_D7", /* BOOT_7 */
- "eMMC_CLK", /* BOOT_8 */
- "",
- "eMMC_CMD", /* BOOT_10 */
- "",
- "eMMC_RST#", /* BOOT_12 */
- "eMMC_DS", /* BOOT_13 */
- /* GPIOC */
- "SD_D0_B", /* GPIOC_0 */
- "SD_D1_B", /* GPIOC_1 */
- "SD_D2_B", /* GPIOC_2 */
- "SD_D3_B", /* GPIOC_3 */
- "SD_CLK_B", /* GPIOC_4 */
- "SD_CMD_B", /* GPIOC_5 */
- "CARD_EN_DET", /* GPIOC_6 */
- "",
- /* GPIOA */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "",
- "CON1-P27", /* GPIOA_14 */
- "CON1-P28", /* GPIOA_15 */
- /* GPIOX */
- "CON1-P16", /* GPIOX_0 */
- "CON1-P18", /* GPIOX_1 */
- "CON1-P22", /* GPIOX_2 */
- "CON1-P11", /* GPIOX_3 */
- "CON1-P13", /* GPIOX_4 */
- "CON1-P07", /* GPIOX_5 */
- "CON1-P33", /* GPIOX_6 */
- "CON1-P15", /* GPIOX_7 */
- "CON1-P19", /* GPIOX_8 */
- "CON1-P21", /* GPIOX_9 */
- "CON1-P24", /* GPIOX_10 */
- "CON1-P23", /* GPIOX_11 */
- "CON1-P08", /* GPIOX_12 */
- "CON1-P10", /* GPIOX_13 */
- "CON1-P29", /* GPIOX_14 */
- "CON1-P31", /* GPIOX_15 */
- "CON1-P26", /* GPIOX_16 */
- "CON1-P03", /* GPIOX_17 */
- "CON1-P05", /* GPIOX_18 */
- "CON1-P32"; /* GPIOX_19 */
-
- /*
- * WARNING: The USB Hub on the BPI-M5 needs a reset signal
- * to be turned high in order to be detected by the USB Controller
- * This signal should be handled by a USB specific power sequence
- * in order to reset the Hub when USB bus is powered down.
- */
- usb-hub {
- gpio-hog;
- gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb-hub-reset";
- };
-};
-
-&gpio_ao {
- gpio-line-names =
- /* GPIOAO */
- "DEBUG TX", /* GPIOAO_0 */
- "DEBUG RX", /* GPIOAO_1 */
- "SYS_LED2", /* GPIOAO_2 */
- "UPDATE_KEY", /* GPIOAO_3 */
- "CON1-P40", /* GPIOAO_4 */
- "IR_IN", /* GPIOAO_5 */
- "TF_3V3N_1V8_EN", /* GPIOAO_6 */
- "CON1-P35", /* GPIOAO_7 */
- "CON1-P12", /* GPIOAO_8 */
- "CON1-P37", /* GPIOAO_9 */
- "CON1-P38", /* GPIOAO_10 */
- "SYS_LED", /* GPIOAO_11 */
- /* GPIOE */
- "VDDEE_PWM", /* GPIOE_0 */
- "VDDCPU_PWM", /* GPIOE_1 */
- "TF_PWR_EN"; /* GPIOE_2 */
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&dc_in>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddao_1v8>;
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- /* TOFIX: SD card is barely usable in SDR modes */
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&tflash_vdd>;
- vqmmc-supply = <&vddio_c>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&emmc_1v8>;
-};
-
&tdmif_b {
status = "okay";
};
&toddr_c {
status = "okay";
};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb2_phy0 {
- phy-supply = <&dc_in>;
-};
-
-&usb2_phy1 {
- /* Enable the hub which is connected to this port */
- phy-supply = <&vl_pwr_en>;
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-sm1.dtsi"
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+/ {
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ button-sw3 {
+ label = "SW3";
+ linux,code = <BTN_3>;
+ press-threshold-microvolt = <1700000>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key {
+ label = "SW1";
+ linux,code = <BTN_1>;
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_1v8: regulator-emmc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vddio_c: regulator-vddio_c {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_C";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ enable-gpios = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>;
+ gpios-states = <1>;
+
+ states = <1800000 0>,
+ <3300000 1>;
+ };
+
+ tflash_vdd: regulator-tflash_vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ vddcpu: regulator-vddcpu {
+ /*
+ * SY8120B1ABC DC/DC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+
+ pwm-supply = <&dc_in>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* USB Hub Power Enable */
+ vl_pwr_en: regulator-vl_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "VL_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU1_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU2_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU3_CLK>;
+ clock-latency = <50000>;
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii-txid";
+ phy-handle = <&external_phy>;
+};
+
+&gpio {
+ gpio-line-names =
+ /* GPIOZ */
+ "ETH_MDIO", /* GPIOZ_0 */
+ "ETH_MDC", /* GPIOZ_1 */
+ "ETH_RXCLK", /* GPIOZ_2 */
+ "ETH_RX_DV", /* GPIOZ_3 */
+ "ETH_RXD0", /* GPIOZ_4 */
+ "ETH_RXD1", /* GPIOZ_5 */
+ "ETH_RXD2", /* GPIOZ_6 */
+ "ETH_RXD3", /* GPIOZ_7 */
+ "ETH_TXCLK", /* GPIOZ_8 */
+ "ETH_TXEN", /* GPIOZ_9 */
+ "ETH_TXD0", /* GPIOZ_10 */
+ "ETH_TXD1", /* GPIOZ_11 */
+ "ETH_TXD2", /* GPIOZ_12 */
+ "ETH_TXD3", /* GPIOZ_13 */
+ "ETH_INTR", /* GPIOZ_14 */
+ "ETH_NRST", /* GPIOZ_15 */
+ /* GPIOH */
+ "HDMI_SDA", /* GPIOH_0 */
+ "HDMI_SCL", /* GPIOH_1 */
+ "HDMI_HPD", /* GPIOH_2 */
+ "HDMI_CEC", /* GPIOH_3 */
+ "VL-RST_N", /* GPIOH_4 */
+ "CON1-P36", /* GPIOH_5 */
+ "VL-PWREN", /* GPIOH_6 */
+ "WiFi_3V3_1V8", /* GPIOH_7 */
+ "TFLASH_VDD_EN", /* GPIOH_8 */
+ /* BOOT */
+ "eMMC_D0", /* BOOT_0 */
+ "eMMC_D1", /* BOOT_1 */
+ "eMMC_D2", /* BOOT_2 */
+ "eMMC_D3", /* BOOT_3 */
+ "eMMC_D4", /* BOOT_4 */
+ "eMMC_D5", /* BOOT_5 */
+ "eMMC_D6", /* BOOT_6 */
+ "eMMC_D7", /* BOOT_7 */
+ "eMMC_CLK", /* BOOT_8 */
+ "",
+ "eMMC_CMD", /* BOOT_10 */
+ "",
+ "eMMC_RST#", /* BOOT_12 */
+ "eMMC_DS", /* BOOT_13 */
+ "", "",
+ /* GPIOC */
+ "SD_D0_B", /* GPIOC_0 */
+ "SD_D1_B", /* GPIOC_1 */
+ "SD_D2_B", /* GPIOC_2 */
+ "SD_D3_B", /* GPIOC_3 */
+ "SD_CLK_B", /* GPIOC_4 */
+ "SD_CMD_B", /* GPIOC_5 */
+ "CARD_EN_DET", /* GPIOC_6 */
+ "",
+ /* GPIOA */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "",
+ "CON1-P27", /* GPIOA_14 */
+ "CON1-P28", /* GPIOA_15 */
+ /* GPIOX */
+ "CON1-P16", /* GPIOX_0 */
+ "CON1-P18", /* GPIOX_1 */
+ "CON1-P22", /* GPIOX_2 */
+ "CON1-P11", /* GPIOX_3 */
+ "CON1-P13", /* GPIOX_4 */
+ "CON1-P07", /* GPIOX_5 */
+ "CON1-P33", /* GPIOX_6 */
+ "CON1-P15", /* GPIOX_7 */
+ "CON1-P19", /* GPIOX_8 */
+ "CON1-P21", /* GPIOX_9 */
+ "CON1-P24", /* GPIOX_10 */
+ "CON1-P23", /* GPIOX_11 */
+ "CON1-P08", /* GPIOX_12 */
+ "CON1-P10", /* GPIOX_13 */
+ "CON1-P29", /* GPIOX_14 */
+ "CON1-P31", /* GPIOX_15 */
+ "CON1-P26", /* GPIOX_16 */
+ "CON1-P03", /* GPIOX_17 */
+ "CON1-P05", /* GPIOX_18 */
+ "CON1-P32"; /* GPIOX_19 */
+
+ /*
+ * WARNING: The USB Hub needs a reset signal to be turned high in
+ * order to be detected by the USB Controller. This signal should
+ * be handled by a USB specific power sequence to reset the Hub
+ * when the USB bus is powered down.
+ */
+ usb-hub-hog {
+ gpio-hog;
+ gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
+&gpio_ao {
+ gpio-line-names =
+ /* GPIOAO */
+ "DEBUG TX", /* GPIOAO_0 */
+ "DEBUG RX", /* GPIOAO_1 */
+ "SYS_LED2", /* GPIOAO_2 */
+ "UPDATE_KEY", /* GPIOAO_3 */
+ "CON1-P40", /* GPIOAO_4 */
+ "IR_IN", /* GPIOAO_5 */
+ "TF_3V3N_1V8_EN", /* GPIOAO_6 */
+ "CON1-P35", /* GPIOAO_7 */
+ "CON1-P12", /* GPIOAO_8 */
+ "CON1-P37", /* GPIOAO_9 */
+ "CON1-P38", /* GPIOAO_10 */
+ "SYS_LED", /* GPIOAO_11 */
+ /* GPIOE */
+ "VDDEE_PWM", /* GPIOE_0 */
+ "VDDCPU_PWM", /* GPIOE_1 */
+ "TF_PWR_EN"; /* GPIOE_2 */
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&dc_in>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ /* TOFIX: SD card is barely usable in SDR modes */
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&vddio_c>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&emmc_1v8>;
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb2_phy0 {
+ phy-supply = <&dc_in>;
+};
+
+&usb2_phy1 {
+ /* Enable the hub which is connected to this port */
+ phy-supply = <&vl_pwr_en>;
+};
dma-requests = <48>;
};
+ fmc: memory-controller@58002000 {
+ compatible = "st,stm32mp1-fmc2-ebi";
+ reg = <0x58002000 0x1000>;
+ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+ <4 0 0x80000000 0x10000000>; /* NAND */
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clocks = <&rcc FMC_K>;
+ resets = <&rcc FMC_R>;
+ status = "disabled";
+
+ nand-controller@4,0 {
+ compatible = "st,stm32mp1-fmc2-nfc";
+ reg = <4 0x00000000 0x1000>,
+ <4 0x08010000 0x1000>,
+ <4 0x08020000 0x1000>,
+ <4 0x01000000 0x1000>,
+ <4 0x09010000 0x1000>,
+ <4 0x09020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
+ <&mdma 24 0x2 0x12000a08 0x0 0x0>,
+ <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
+ dma-names = "tx", "rx", "ecc";
+ status = "disabled";
+ };
+ };
+
+ qspi: spi@58003000 {
+ compatible = "st,stm32f469-qspi";
+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+ reg-names = "qspi", "qspi_mm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
+ <&mdma 26 0x2 0x10100008 0x0 0x0>;
+ dma-names = "tx", "rx";
+ clocks = <&rcc QSPI_K>;
+ resets = <&rcc QSPI_R>;
+ status = "disabled";
+ };
+
sdmmc1: mmc@58005000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x20253180>;
__func__, boot_ctx, boot_mode, instance, forced_mode);
switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
case BOOT_SERIAL_UART:
- if (instance > ARRAY_SIZE(serial_addr))
+ if (instance >= ARRAY_SIZE(serial_addr))
break;
/* serial : search associated node in devicetree */
sprintf(cmd, "serial@%x", serial_addr[instance]);
break;
case BOOT_FLASH_SD:
case BOOT_FLASH_EMMC:
- if (instance > ARRAY_SIZE(sdmmc_addr))
+ if (instance >= ARRAY_SIZE(sdmmc_addr))
break;
/* search associated sdmmc node in devicetree */
sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
bool "Support SiFive Unmatched Board"
select SYS_CACHE_SHIFT_6
+config TARGET_STARFIVE_VISIONFIVE2
+ bool "Support StarFive VisionFive2 Board"
+
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
select SYS_CACHE_SHIFT_6
source "board/sifive/unmatched/Kconfig"
source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"
+source "board/starfive/visionfive2/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/andesv5/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
+source "arch/riscv/cpu/jh7110/Kconfig"
# architecture-specific options below
ifdef CONFIG_32BIT
KBUILD_LDFLAGS += -m $(32bit-emul)
EFI_LDS := elf_riscv32_efi.lds
+PLATFORM_ELFFLAGS += -B riscv -O elf32-littleriscv
endif
ifdef CONFIG_64BIT
KBUILD_LDFLAGS += -m $(64bit-emul)
EFI_LDS := elf_riscv64_efi.lds
+PLATFORM_ELFFLAGS += -B riscv -O elf64-littleriscv
endif
PLATFORM_CPPFLAGS += -ffixed-gp -fpic
-PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections \
- -fdata-sections
+PLATFORM_RELFLAGS += -fno-common -ffunction-sections -fdata-sections
LDFLAGS_u-boot += --gc-sections -static -pie
EFI_CRT0 := crt0_riscv_efi.o
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+
+config STARFIVE_JH7110
+ bool
+ select ARCH_EARLY_INIT_R
+ select CLK_JH7110
+ select CPU
+ select CPU_RISCV
+ select RAM
+ select RESET_JH7110
+ select SUPPORT_SPL
+ select SPL_RAM if SPL
+ select SPL_STARFIVE_DDR
+ select PINCTRL_STARFIVE_JH7110
+ imply MMC
+ imply MMC_BROKEN_CD
+ imply MMC_SPI
+ imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+ imply SIFIVE_CACHE
+ imply SIFIVE_CCACHE
+ imply SMP
+ imply SPI
+ imply SPL_CPU
+ imply SPL_LOAD_FIT
+ imply SPL_OPENSBI
+ imply SPL_SIFIVE_CLINT
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += cpu.o
+obj-y += dram.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#include <asm/cache.h>
+#include <irq_func.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ cache_flush();
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+ /*
+ * Ensure that we run from first 4GB so that all
+ * addresses used by U-Boot are 32bit addresses.
+ *
+ * This in-turn ensures that 32bit DMA capable
+ * devices work fine because DMA mapping APIs will
+ * provide 32bit DMA addresses only.
+ */
+ if (IS_ENABLED(CONFIG_64BIT) && gd->ram_top > SZ_4G)
+ return SZ_4G;
+
+ return gd->ram_top;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <asm/csr.h>
+#include <asm/sections.h>
+#include <dm.h>
+#include <log.h>
+
+#define CSR_U74_FEATURE_DISABLE 0x7c1
+#define L2_LIM_MEM_END 0x81FFFFFUL
+
+int spl_soc_init(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ /* DDR init */
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+void harts_early_init(void)
+{
+ ulong *ptr;
+ u8 *tmp;
+ ulong len, remain;
+ /*
+ * Feature Disable CSR
+ *
+ * Clear feature disable CSR to '0' to turn on all features for
+ * each core. This operation must be in M-mode.
+ */
+ if (CONFIG_IS_ENABLED(RISCV_MMODE))
+ csr_write(CSR_U74_FEATURE_DISABLE, 0);
+
+ /* clear L2 LIM memory
+ * set __bss_end to 0x81FFFFF region to zero
+ * The L2 Cache Controller supports ECC. ECC is applied to SRAM.
+ * If it is not cleared, the ECC part is invalid, and an ECC error
+ * will be reported when reading data.
+ */
+ ptr = (ulong *)&__bss_end;
+ len = L2_LIM_MEM_END - (ulong)&__bss_end;
+ remain = len % sizeof(ulong);
+ len /= sizeof(ulong);
+
+ while (len--)
+ *ptr++ = 0;
+
+ /* clear the remain bytes */
+ if (remain) {
+ tmp = (u8 *)ptr;
+ while (remain--)
+ *tmp++ = 0;
+ }
+}
spl_call_board_init_r:
mv a0, zero
mv a1, zero
- jal board_init_r
+ j board_init_r
#endif
+#if !defined(CONFIG_SPL_BUILD)
/*
* void relocate_code(addr_sp, gd, addr_moni)
*
beq t0, s4, clear_bss /* skip relocation */
mv t1, s4 /* t1 <- scratch for copy_loop */
- la t3, __bss_start
- sub t3, t3, t0 /* t3 <- __bss_start_ofs */
- add t2, t0, t3 /* t2 <- source end address */
+ la t2, __bss_start /* t2 <- source end address */
copy_loop:
LREG t5, 0(t0)
add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
-/*
- * skip first reserved entry: address, type, addend
- */
- j 10f
-
6:
- LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
+ LREG t5, REGBYTES(t1) /* t5 <-- relocation info:type */
li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
- LREG t3, -(REGBYTES*3)(t1)
- LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
+ LREG t3, 0(t1)
+ LREG t5, (REGBYTES * 2)(t1) /* t5 <-- addend */
add t5, t5, t6 /* t5 <-- location to fix up in RAM */
add t3, t3, t6 /* t3 <-- location to fix up in RAM */
SREG t5, 0(t3)
add t4, t4, t6
9:
- LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
andi t5, t5, 0xFF /* t5 <--- relocation type */
li t3, RELOC_TYPE
bne t5, t3, 10f /* skip non-addned entries */
- LREG t3, -(REGBYTES*3)(t1)
+ LREG t3, 0(t1)
li t5, SYM_SIZE
mul t0, t0, t5
add s5, t4, t0
- LREG t0, -(REGBYTES)(t1) /* t0 <-- addend */
+ LREG t0, (REGBYTES * 2)(t1) /* t0 <-- addend */
LREG t5, REGBYTES(s5)
add t5, t5, t0
add t5, t5, t6 /* t5 <-- location to fix up in RAM */
add t3, t3, t6 /* t3 <-- location to fix up in RAM */
SREG t5, 0(t3)
10:
- addi t1, t1, (REGBYTES*3)
- ble t1, t2, 6b
+ addi t1, t1, (REGBYTES * 3)
+ blt t1, t2, 6b
/*
* trap update
* jump to it ...
*/
jr t4 /* jump to board_init_r() */
+#endif /* !defined(CONFIG_SPL_BUILD) */
#if CONFIG_IS_ENABLED(SMP)
hart_out_of_bounds_loop:
} > .spl_mem
. = ALIGN(4);
- .got : {
- __got_start = .;
- *(.got.plt) *(.got)
- __got_end = .;
- } > .spl_mem
-
- . = ALIGN(4);
-
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
} > .spl_mem
__binman_sym_end = .;
} > .spl_mem
- . = ALIGN(4);
-
- /DISCARD/ : { *(.rela.plt*) }
- .rela.dyn : {
- __rel_dyn_start = .;
- *(.rela*)
- __rel_dyn_end = .;
- } > .spl_mem
-
- . = ALIGN(4);
-
- .dynsym : {
- __dyn_sym_start = .;
- *(.dynsym)
- __dyn_sym_end = .;
- } > .spl_mem
-
- . = ALIGN(4);
+ . = ALIGN(8);
_end = .;
_image_binary_end = .;
__efi_runtime_rel_stop = .;
}
- . = ALIGN(4);
+ . = ALIGN(8);
/DISCARD/ : { *(.rela.plt*) }
.rela.dyn : {
__rel_dyn_end = .;
}
- . = ALIGN(4);
+ . = ALIGN(8);
.dynsym : {
__dyn_sym_start = .;
__dyn_sym_end = .;
}
- . = ALIGN(4);
+ . = ALIGN(8);
_end = .;
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+ chosen {
+ bootph-pre-ram;
+ };
+
+ firmware {
+ spi0 = &qspi;
+ bootph-pre-ram;
+ };
+
+ config {
+ bootph-pre-ram;
+ u-boot,spl-payload-offset = <0x100000>;
+ };
+
+ memory@40000000 {
+ bootph-pre-ram;
+ };
+};
+
+&uart0 {
+ bootph-pre-ram;
+};
+
+&mmc0 {
+ bootph-pre-ram;
+};
+
+&mmc1 {
+ bootph-pre-ram;
+};
+
+&qspi {
+ bootph-pre-ram;
+
+ nor-flash@0 {
+ bootph-pre-ram;
+ };
+};
+
+&sysgpio {
+ bootph-pre-ram;
+};
+
+&mmc0_pins {
+ bootph-pre-ram;
+ mmc0-pins-rest {
+ bootph-pre-ram;
+ };
+};
+
+&mmc1_pins {
+ bootph-pre-ram;
+ mmc1-pins0 {
+ bootph-pre-ram;
+ };
+
+ mmc1-pins1 {
+ bootph-pre-ram;
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 v1.2A";
+ compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+ chosen {
+ bootph-pre-ram;
+ };
+
+ firmware {
+ spi0 = &qspi;
+ bootph-pre-ram;
+ };
+
+ config {
+ bootph-pre-ram;
+ u-boot,spl-payload-offset = <0x100000>;
+ };
+
+ memory@40000000 {
+ bootph-pre-ram;
+ };
+};
+
+&uart0 {
+ bootph-pre-ram;
+};
+
+&mmc0 {
+ bootph-pre-ram;
+};
+
+&mmc1 {
+ bootph-pre-ram;
+};
+
+&qspi {
+ bootph-pre-ram;
+
+ nor-flash@0 {
+ bootph-pre-ram;
+ };
+};
+
+&sysgpio {
+ bootph-pre-ram;
+};
+
+&mmc0_pins {
+ bootph-pre-ram;
+ mmc0-pins-rest {
+ bootph-pre-ram;
+ };
+};
+
+&mmc1_pins {
+ bootph-pre-ram;
+ mmc1-pins0 {
+ bootph-pre-ram;
+ };
+
+ mmc1-pins1 {
+ bootph-pre-ram;
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 v1.3B";
+ compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "jh7110.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+/ {
+ aliases {
+ serial0 = &uart0;
+ spi0 = &qspi;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ i2c0 = &i2c0;
+ i2c2 = &i2c2;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <4000000>;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x2 0x0>;
+ };
+};
+
+&osc {
+ clock-frequency = <24000000>;
+};
+
+&rtc_osc {
+ clock-frequency = <32768>;
+};
+
+&gmac0_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac0_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&gmac1_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac1_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&i2stx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2stx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&i2srx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2srx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&tdm_ext {
+ clock-frequency = <49152000>;
+};
+
+&mclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&uart0 {
+ reg-offset = <0>;
+ current-speed = <115200>;
+ clock-frequency = <24000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+};
+
+&i2c5 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ status = "okay";
+};
+
+&i2c6 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins>;
+ status = "okay";
+};
+
+&sysgpio {
+ status = "okay";
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pinmux = <GPIOMUX(6, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_UART0_RX)>;
+ bias-disable; /* external pull-up */
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c0_pins: i2c0-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(57, GPOUT_LOW,
+ GPOEN_SYS_I2C0_CLK,
+ GPI_SYS_I2C0_CLK)>,
+ <GPIOMUX(58, GPOUT_LOW,
+ GPOEN_SYS_I2C0_DATA,
+ GPI_SYS_I2C0_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c2_pins: i2c2-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(3, GPOUT_LOW,
+ GPOEN_SYS_I2C2_CLK,
+ GPI_SYS_I2C2_CLK)>,
+ <GPIOMUX(2, GPOUT_LOW,
+ GPOEN_SYS_I2C2_DATA,
+ GPI_SYS_I2C2_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c5_pins: i2c5-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(19, GPOUT_LOW,
+ GPOEN_SYS_I2C5_CLK,
+ GPI_SYS_I2C5_CLK)>,
+ <GPIOMUX(20, GPOUT_LOW,
+ GPOEN_SYS_I2C5_DATA,
+ GPI_SYS_I2C5_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c6_pins: i2c6-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(16, GPOUT_LOW,
+ GPOEN_SYS_I2C6_CLK,
+ GPI_SYS_I2C6_CLK)>,
+ <GPIOMUX(17, GPOUT_LOW,
+ GPOEN_SYS_I2C6_DATA,
+ GPI_SYS_I2C6_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ mmc0_pins: mmc0-pins {
+ mmc0-pins-rest {
+ pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+ GPOEN_ENABLE, GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ mmc1_pins: mmc1-pins {
+ mmc1-pins0 {
+ pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
+ GPOEN_ENABLE, GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ mmc1-pins1 {
+ pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
+ GPOEN_SYS_SDIO1_CMD, GPI_SYS_SDIO1_CMD)>,
+ <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
+ GPOEN_SYS_SDIO1_DATA0, GPI_SYS_SDIO1_DATA0)>,
+ <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
+ GPOEN_SYS_SDIO1_DATA1, GPI_SYS_SDIO1_DATA1)>,
+ <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
+ GPOEN_SYS_SDIO1_DATA2, GPI_SYS_SDIO1_DATA2)>,
+ <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
+ GPOEN_SYS_SDIO1_DATA3, GPI_SYS_SDIO1_DATA3)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+};
+
+&mmc0 {
+ compatible = "snps,dw-mshc";
+ max-frequency = <100000000>;
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ cap-mmc-hw-reset;
+ post-power-on-delay-ms = <200>;
+ status = "okay";
+
+};
+
+&mmc1 {
+ compatible = "snps,dw-mshc";
+ max-frequency = <100000000>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ no-sdio;
+ no-mmc;
+ broken-cd;
+ cap-sd-highspeed;
+ post-power-on-delay-ms = <200>;
+ status = "okay";
+};
+
+&qspi {
+ spi-max-frequency = <250000000>;
+ status = "okay";
+
+ nor-flash@0 {
+ compatible = "jedec,spi-nor";
+ reg=<0>;
+ spi-max-frequency = <100000000>;
+ cdns,tshsl-ns = <1>;
+ cdns,tsd2d-ns = <1>;
+ cdns,tchsh-ns = <1>;
+ cdns,tslch-ns = <1>;
+ };
+};
+
+&syscrg {
+ assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+ <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+ <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+ <&syscrg JH7110_SYSCLK_QSPI_REF>;
+ assigned-clock-parents = <&syscrg JH7110_SYSCLK_PLL0_OUT>,
+ <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+ <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+ <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+ assigned-clock-rates = <0>, <0>, <0>, <0>;
+};
+
+&aoncrg {
+ assigned-clocks = <&aoncrg JH7110_AONCLK_APB_FUNC>;
+ assigned-clock-parents = <&osc>;
+ assigned-clock-rates = <0>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+/ {
+ cpus: cpus {
+ bootph-pre-ram;
+
+ S7_0: cpu@0 {
+ bootph-pre-ram;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ bootph-pre-ram;
+ };
+ };
+
+ U74_1: cpu@1 {
+ bootph-pre-ram;
+ cpu1_intc: interrupt-controller {
+ bootph-pre-ram;
+ };
+ };
+
+ U74_2: cpu@2 {
+ bootph-pre-ram;
+ cpu2_intc: interrupt-controller {
+ bootph-pre-ram;
+ };
+ };
+
+ U74_3: cpu@3 {
+ bootph-pre-ram;
+ cpu3_intc: interrupt-controller {
+ bootph-pre-ram;
+ };
+ };
+
+ U74_4: cpu@4 {
+ bootph-pre-ram;
+ cpu4_intc: interrupt-controller {
+ bootph-pre-ram;
+ };
+ };
+ };
+
+ soc {
+ bootph-pre-ram;
+
+ clint: timer@2000000 {
+ bootph-pre-ram;
+ };
+
+ dmc: dmc@15700000 {
+ bootph-pre-ram;
+ compatible = "starfive,jh7110-dmc";
+ reg = <0x0 0x15700000 0x0 0x10000>,
+ <0x0 0x13000000 0x0 0x10000>;
+ resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+ <&syscrg JH7110_SYSRST_DDR_OSC>,
+ <&syscrg JH7110_SYSRST_DDR_APB>;
+ reset-names = "axi", "osc", "apb";
+ clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>;
+ clock-names = "pll1_out";
+ clock-frequency = <2133>;
+ };
+ };
+};
+
+&osc {
+ bootph-pre-ram;
+};
+
+&gmac0_rmii_refin {
+ bootph-pre-ram;
+};
+
+&aoncrg {
+ bootph-pre-ram;
+};
+
+&syscrg {
+ bootph-pre-ram;
+ starfive,sys-syscon = <&sys_syscon>;
+};
+
+&stgcrg {
+ bootph-pre-ram;
+};
+
+&sys_syscon {
+ bootph-pre-ram;
+};
+
+&S7_0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+/ {
+ compatible = "starfive,jh7110";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ S7_0: cpu@0 {
+ compatible = "sifive,s7", "riscv";
+ reg = <0>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <16384>;
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imac_zba_zbb";
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_1: cpu@1 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <1>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc_zba_zbb";
+ tlb-split;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_2: cpu@2 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <2>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc_zba_zbb";
+ tlb-split;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_3: cpu@3 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <3>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc_zba_zbb";
+ tlb-split;
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_4: cpu@4 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <4>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc_zba_zbb";
+ tlb-split;
+
+ cpu4_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&S7_0>;
+ };
+
+ core1 {
+ cpu = <&U74_1>;
+ };
+
+ core2 {
+ cpu = <&U74_2>;
+ };
+
+ core3 {
+ cpu = <&U74_3>;
+ };
+
+ core4 {
+ cpu = <&U74_4>;
+ };
+ };
+ };
+ };
+
+ osc: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc";
+ #clock-cells = <0>;
+ };
+
+ rtc_osc: rtc-oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "rtc_osc";
+ #clock-cells = <0>;
+ };
+
+ gmac0_rmii_refin: gmac0-rmii-refin-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "gmac0_rmii_refin";
+ #clock-cells = <0>;
+ };
+
+ gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "gmac0_rgmii_rxin";
+ #clock-cells = <0>;
+ };
+
+ gmac1_rmii_refin: gmac1-rmii-refin-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "gmac1_rmii_refin";
+ #clock-cells = <0>;
+ };
+
+ gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "gmac1_rgmii_rxin";
+ #clock-cells = <0>;
+ };
+
+ i2stx_bclk_ext: i2stx-bclk-ext-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "i2stx_bclk_ext";
+ #clock-cells = <0>;
+ };
+
+ i2stx_lrck_ext: i2stx-lrck-ext-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "i2stx_lrck_ext";
+ #clock-cells = <0>;
+ };
+
+ i2srx_bclk_ext: i2srx-bclk-ext-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "i2srx_bclk_ext";
+ #clock-cells = <0>;
+ };
+
+ i2srx_lrck_ext: i2srx-lrck-ext-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "i2srx_lrck_ext";
+ #clock-cells = <0>;
+ };
+
+ tdm_ext: tdm-ext-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "tdm_ext";
+ #clock-cells = <0>;
+ };
+
+ mclk_ext: mclk-ext-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "mclk_ext";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clint: timer@2000000 {
+ compatible = "starfive,jh7110-clint", "sifive,clint0";
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>,
+ <&cpu4_intc 3>, <&cpu4_intc 7>;
+ };
+
+ plic: interrupt-controller@c000000 {
+ compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>,
+ <&cpu4_intc 11>, <&cpu4_intc 9>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ riscv,ndev = <136>;
+ };
+
+ ccache: cache-controller@2010000 {
+ compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
+ reg = <0x0 0x2010000 0x0 0x4000>;
+ interrupts = <1>, <3>, <4>, <2>;
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <2097152>;
+ cache-unified;
+ };
+
+ uart0: serial@10000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10000000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
+ <&syscrg JH7110_SYSCLK_UART0_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART0_APB>,
+ <&syscrg JH7110_SYSRST_UART0_CORE>;
+ interrupts = <32>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@10010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10010000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
+ <&syscrg JH7110_SYSCLK_UART1_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART1_APB>,
+ <&syscrg JH7110_SYSRST_UART1_CORE>;
+ interrupts = <33>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@10020000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10020000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
+ <&syscrg JH7110_SYSCLK_UART2_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART2_APB>,
+ <&syscrg JH7110_SYSRST_UART2_CORE>;
+ interrupts = <34>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@10030000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x10030000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
+ interrupts = <35>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10040000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x10040000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
+ interrupts = <36>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@10050000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x10050000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
+ interrupts = <37>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ stgcrg: clock-controller@10230000 {
+ compatible = "starfive,jh7110-stgcrg";
+ reg = <0x0 0x10230000 0x0 0x10000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ stg_syscon: stg_syscon@10240000 {
+ compatible = "starfive,jh7110-stg-syscon","syscon";
+ reg = <0x0 0x10240000 0x0 0x1000>;
+ };
+
+ uart3: serial@12000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12000000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
+ <&syscrg JH7110_SYSCLK_UART3_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART3_APB>,
+ <&syscrg JH7110_SYSRST_UART3_CORE>;
+ interrupts = <45>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@12010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12010000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
+ <&syscrg JH7110_SYSCLK_UART4_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART4_APB>,
+ <&syscrg JH7110_SYSRST_UART4_CORE>;
+ interrupts = <46>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart5: serial@12020000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12020000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
+ <&syscrg JH7110_SYSCLK_UART5_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART5_APB>,
+ <&syscrg JH7110_SYSRST_UART5_CORE>;
+ interrupts = <47>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@12030000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x12030000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
+ interrupts = <48>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@12040000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x12040000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
+ interrupts = <49>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@12050000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x12050000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
+ interrupts = <50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@12060000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x12060000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
+ interrupts = <51>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ qspi: spi@13010000 {
+ compatible = "cdns,qspi-nor";
+ reg = <0x0 0x13010000 0x0 0x10000
+ 0x0 0x21000000 0x0 0x400000>;
+ clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
+ clock-names = "clk_ref";
+ resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+ <&syscrg JH7110_SYSRST_QSPI_AHB>,
+ <&syscrg JH7110_SYSRST_QSPI_REF>;
+ reset-names = "rst_apb", "rst_ahb", "rst_ref";
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ syscrg: clock-controller@13020000 {
+ compatible = "starfive,jh7110-syscrg";
+ reg = <0x0 0x13020000 0x0 0x10000>;
+ clocks = <&osc>, <&gmac1_rmii_refin>,
+ <&gmac1_rgmii_rxin>,
+ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+ <&tdm_ext>, <&mclk_ext>;
+ clock-names = "osc", "gmac1_rmii_refin",
+ "gmac1_rgmii_rxin",
+ "i2stx_bclk_ext", "i2stx_lrck_ext",
+ "i2srx_bclk_ext", "i2srx_lrck_ext",
+ "tdm_ext", "mclk_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sys_syscon: sys_syscon@13030000 {
+ compatible = "starfive,jh7110-sys-syscon","syscon";
+ reg = <0x0 0x13030000 0x0 0x1000>;
+ };
+
+ sysgpio: pinctrl@13040000 {
+ compatible = "starfive,jh7110-sys-pinctrl";
+ reg = <0x0 0x13040000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
+ resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
+ interrupts = <86>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ mmc0: mmc@16010000 {
+ compatible = "starfive,jh7110-mmc";
+ reg = <0x0 0x16010000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
+ <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
+ clock-names = "biu", "ciu";
+ resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
+ reset-names = "reset";
+ interrupts = <74>;
+ fifo-depth = <32>;
+ fifo-watermark-aligned;
+ data-addr = <0>;
+ starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@16020000 {
+ compatible = "starfive,jh7110-mmc";
+ reg = <0x0 0x16020000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
+ <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
+ clock-names = "biu", "ciu";
+ resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
+ reset-names = "reset";
+ interrupts = <75>;
+ fifo-depth = <32>;
+ fifo-watermark-aligned;
+ data-addr = <0>;
+ starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
+ status = "disabled";
+ };
+
+ aoncrg: clock-controller@17000000 {
+ compatible = "starfive,jh7110-aoncrg";
+ reg = <0x0 0x17000000 0x0 0x10000>;
+ clocks = <&osc>, <&rtc_osc>,
+ <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+ <&syscrg JH7110_SYSCLK_APB_BUS>,
+ <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
+ clock-names = "osc", "rtc_osc", "gmac0_rmii_refin",
+ "gmac0_rgmii_rxin", "stg_axiahb",
+ "apb_bus", "gmac0_gtxclk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ aon_syscon: aon_syscon@17010000 {
+ compatible = "starfive,jh7110-aon-syscon","syscon";
+ reg = <0x0 0x17010000 0x0 0x1000>;
+ };
+
+ aongpio: pinctrl@17020000 {
+ compatible = "starfive,jh7110-aon-pinctrl";
+ reg = <0x0 0x17020000 0x0 0x10000>;
+ resets = <&aoncrg JH7110_AONRST_IOMUX>;
+ interrupts = <85>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#ifndef __STARFIVE_JH7110_REGS_H
+#define __STARFIVE_JH7110_REGS_H
+
+#define JH7110_SYS_CRG 0x13020000
+#define JH7110_SYS_SYSCON 0x13030000
+#define JH7110_SYS_IOMUX 0x13040000
+#define JH7110_AON_CRG 0x17000000
+#define JH7110_AON_SYSCON 0x17010000
+
+#define JH7110_BOOT_MODE_SELECT_REG 0x1702002c
+#define JH7110_BOOT_MODE_SELECT_MASK GENMASK(1, 0)
+
+#endif /* __STARFIVE_JH7110_REGS_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#ifndef _SPL_STARFIVE_H
+#define _SPL_STARFIVE_H
+
+int spl_soc_init(void);
+
+#endif /* _SPL_STARFIVE_H */
* IO port access primitives
* -------------------------
*
- * The NDS32 doesn't have special IO access instructions just like ARM;
+ * The RISC-V doesn't have special IO access instructions just like ARM;
* all IO is memory mapped.
* Note that these are defined to perform little endian accesses
* only. Their primary purpose is to access PCI and ISA peripherals.
S: Maintained
L: u-boot-amlogic@groups.io
F: board/amlogic/beelink-s922x/
+F: configs/beelink-gsking-x_defconfig
F: configs/beelink-gtking_defconfig
F: configs/beelink-gtkingpro_defconfig
-F: configs/beelink-gsking-x_defconfig
+F: doc/board/amlogic/beelink-gskingx.rst
F: doc/board/amlogic/beelink-gtking.rst
F: doc/board/amlogic/beelink-gtkingpro.rst
F: configs/nanopi-k2_defconfig
F: configs/odroid-c2_defconfig
F: configs/p200_defconfig
+F: configs/wetek-hub_defconfig
+F: configs/wetek-play2_defconfig
F: doc/board/amlogic/p200.rst
F: doc/board/amlogic/nanopi-k2.rst
F: doc/board/amlogic/odroid-c2.rst
+F: doc/board/amlogic/wetek-hub.rst
+F: doc/board/amlogic/wetek-play2.rst
L: u-boot-amlogic@groups.io
F: board/amlogic/q200/
F: include/configs/q200.h
+F: configs/beelink-gt1-ultimate_defconfig
F: configs/khadas-vim2_defconfig
F: configs/libretech-s905d-pc_defconfig
F: configs/libretech-s912-pc_defconfig
F: configs/wetek-core2_defconfig
+F: doc/board/amlogic/beelink-gt1-ultimate.rst
F: doc/board/amlogic/khadas-vim2.rst
F: doc/board/amlogic/wetek-core2.rst
L: u-boot-amlogic@groups.io
F: board/amlogic/u200/
F: configs/u200_defconfig
+F: configs/bananapi-m2pro_defconfig
F: configs/bananapi-m5_defconfig
F: configs/radxa-zero_defconfig
F: doc/board/amlogic/u200.rst
+F: doc/board/amlogic/bananapi-m2pro.rst
+F: doc/board/amlogic/bananapi-m5.rst
F: doc/board/amlogic/radxa-zero.rst
S: Maintained
L: u-boot-amlogic@groups.io
F: board/amlogic/w400/
+F: configs/bananapi-cm4-cm4io_defconfig
+F: configs/bananapi-m2s_defconfig
+F: configs/radxa-zero2_defconfig
F: doc/board/amlogic/w400.rst
+F: doc/board/amlogic/bananapi-cm4io.rst
+F: doc/board/amlogic/bananapi-m2s.rst
+F: doc/board/amlogic/radxa-zero2.rst
STM32_SDMMC3_BASE
};
- if (instance > ARRAY_SIZE(sdmmc_addr))
+ if (instance >= ARRAY_SIZE(sdmmc_addr))
return 0;
/* search associated sdmmc node in devicetree */
--- /dev/null
+if TARGET_STARFIVE_VISIONFIVE2
+
+config SYS_CPU
+ default "jh7110"
+
+config SYS_BOARD
+ default "visionfive2"
+
+config SYS_VENDOR
+ default "starfive"
+
+config SYS_CONFIG_NAME
+ default "starfive-visionfive2"
+
+config TEXT_BASE
+ default 0x40200000 if SPL
+ default 0x40000000 if !RISCV_SMODE
+ default 0x40200000 if RISCV_SMODE
+
+config SPL_TEXT_BASE
+ default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+ default 0x80000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select STARFIVE_JH7110
+ select SUPPORT_SPL
+ select BINMAN
+ imply CMD_CPU
+ imply CMD_DHCP
+ imply CMD_EXT2
+ imply CMD_EXT4
+ imply CMD_FAT
+ imply CMD_FS_GENERIC
+ imply CMD_GPIO
+ imply CMD_GPT
+ imply CMD_MMC
+ imply CMD_NET
+ imply CMD_PING
+ imply CMD_SF
+ imply DM_GPIO
+ imply DOS_PARTITION
+ imply EFI_PARTITION
+ imply MII
+ imply IP_DYN
+ imply ISO_PARTITION
+ imply PARTITION_TYPE_GUID
+ imply PHY_LIB
+ imply PHY_MSCC
+
+endif
--- /dev/null
+STARFIVE JH7110 VISIONFIVE2 BOARD
+M: startfive
+S: Maintained
+F: arch/riscv/include/asm/arch-jh7110/
+F: board/starfive/visionfive2/
+F: include/configs/starfive-visionfive2.h
+F: configs/starfive_visionfive2_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+#
+
+obj-y := starfive_visionfive2.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/arch/regs.h>
+#include <asm/arch/spl.h>
+#include <asm/io.h>
+#include <log.h>
+#include <spl.h>
+
+#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
+#define JH7110_CLK_CPU_ROOT_SHIFT 24
+#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
+
+int spl_board_init_f(void)
+{
+ int ret;
+
+ ret = spl_soc_init();
+ if (ret) {
+ debug("JH7110 SPL init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 mode;
+
+ mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
+ & JH7110_BOOT_MODE_SELECT_MASK;
+ switch (mode) {
+ case 0:
+ return BOOT_DEVICE_SPI;
+
+ case 1:
+ return BOOT_DEVICE_MMC2;
+
+ case 2:
+ return BOOT_DEVICE_MMC1;
+
+ case 3:
+ return BOOT_DEVICE_UART;
+
+ default:
+ debug("Unsupported boot device 0x%x.\n", mode);
+ return BOOT_DEVICE_NONE;
+ }
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ ret = spl_early_init();
+ if (ret)
+ panic("spl_early_init() failed: %d\n", ret);
+
+ riscv_cpu_setup(NULL, NULL);
+ preloader_console_init();
+
+ /* Set the parent clock of cpu_root clock to pll0,
+ * it must be initialized here
+ */
+ clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET,
+ JH7110_CLK_CPU_ROOT_MASK,
+ BIT(JH7110_CLK_CPU_ROOT_SHIFT));
+
+ ret = spl_board_init_f();
+ if (ret) {
+ debug("spl_board_init_f init failed: %d\n", ret);
+ return;
+ }
+}
+
+#if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ /* boot using first FIT config */
+ return 0;
+}
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <cpu_func.h>
+#include <linux/bitops.h>
+
+#define JH7110_L2_PREFETCHER_BASE_ADDR 0x2030000
+#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
+
+/* enable U74-mc hart1~hart4 prefetcher */
+static void enable_prefetcher(void)
+{
+ u8 hart;
+ u32 *reg;
+
+ /* JH7110 use U74MC CORE IP, it include five cores(one S7 and four U7),
+ * but only U7 cores support prefetcher configuration
+ */
+ for (hart = 1; hart < 5; hart++) {
+ reg = (void *)(u64)(JH7110_L2_PREFETCHER_BASE_ADDR
+ + hart * JH7110_L2_PREFETCHER_HART_OFFSET);
+
+ mb(); /* memory barrier */
+ setbits_le32(reg, 0x1);
+ mb(); /* memory barrier */
+ }
+}
+
+int board_init(void)
+{
+ enable_caches();
+ enable_prefetcher();
+
+ return 0;
+}
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-bananapi-cm4-cm4io"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING="bpi-cm4io"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m2-pro"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING="bpi-m2-pro"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-bananapi-m2s"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" bpi-m2s"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_AHCI_PCI=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-gt1-ultimate"
+CONFIG_DM_RESET=y
+CONFIG_MESON_GXM=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" beelink-gt1"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
+CONFIG_MESON_GXL_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_GXL=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_POWER_DOMAIN=y
-CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-radxa-zero2"
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" radxa-zero2"
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+# CONFIG_PHY_REALTEK is not set
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+# CONFIG_ETH_DESIGNWARE_MESON8B is not set
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_WDT_GPIO=y
CONFIG_WDT_SANDBOX=y
CONFIG_WDT_ALARM_SANDBOX=y
+CONFIG_WDT_FTWDT010=y
CONFIG_FS_CBFS=y
CONFIG_FS_CRAMFS=y
CONFIG_ADDR_MAP=y
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000000
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2-v1.3b"
+CONFIG_SPL_TEXT_BASE=0x8000000
+CONFIG_SYS_PROMPT="StarFive #"
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_STACK=0x8180000
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
+CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000
+CONFIG_ARCH_RV64I=y
+CONFIG_CMODEL_MEDANY=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
+CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_BSS_START_ADDR=0x8040000
+CONFIG_SPL_BSS_MAX_SIZE=0x10000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80000000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x400000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_JH7110=y
+# CONFIG_I2C is not set
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_SF_DEFAULT_SPEED=100000000
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_SPL_PINCONF=y
+CONFIG_SPL_PINCTRL_STARFIVE=y
+CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
+CONFIG_PINCTRL_STARFIVE=y
+# CONFIG_RAM_SIFIVE is not set
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER_EARLY=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_FDT_SIMPLEFB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_ADTIMG=y
CONFIG_ARM=y
CONFIG_ARCH_STM32MP=y
CONFIG_TFABOOT=y
-CONFIG_SYS_MALLOC_F_LEN=0x20000
+CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000
CONFIG_ENV_OFFSET=0x480000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_FDT_SIMPLEFB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_ADTIMG=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_FDT_SIMPLEFB=y
+CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
CONFIG_SYS_PBSIZE=1050
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_ADTIMG=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_POWER_DOMAIN=y
-CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DEBUG_UART_ANNOUNCE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" wetek-hub"
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-wetek-hub"
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_PHY=y
+CONFIG_MESON_GXBB_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXBB=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" wetek-play2"
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-wetek-play2"
+CONFIG_DEBUG_UART=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
+CONFIG_OF_BOARD_SETUP=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_PHY=y
+CONFIG_MESON_GXBB_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXBB=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for BananaPi CM4 with CM4IO (A311D)
+==========================================
+
+BPI-CM4 is a system-on-module board manufactured by Sinovoip. It follows the Raspberry Pi
+CM4 interface specification but with a single HDMI port and a single DSI output:
+
+ - Amlogic A311D Arm Cortex-A53 dual-core + Cortex-A73 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - 16GB eMMC
+ - NPU
+ - HDMI 2.1 display
+ - Gigabit Ethernet
+ - RTL8822CS WiFi (a/b/g/n/ac) + BT 5.0
+
+BPI-CM4IO is a carrier board for the BPI-CM4 module with the following specification:
+
+ - CM4 interface
+ - HDMI interface
+ - MIPI CSI interface
+ - MIPI DSI interface
+ - Ethernet interface
+ - PCIe interface
+ - SD (micro)
+ - SIM (micro)
+ - 26-pin GPIO
+ - UART serial
+ - 1x USB-C (power)
+ - 2x USB 2.0
+
+Schematics are available from the manufacturer: https://wiki.banana-pi.org/Banana_Pi_BPI-CM4
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make bananapi-cm4io_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh bananapi-cm4io /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+ $ DIR=bananapi-cm4io
+ $ git clone --depth 1 https://github.com/Dangku/amlogic-u-boot.git -b khadas-g12b-v2015.01-m2s $DIR
+
+ $ cd $DIR
+ $ make bananapi_cm4_defconfig
+ $ make
+ $ export UBDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ $ cp $UBDIR/build/scp_task/bl301.bin fip/
+ $ cp $UBDIR/build/board/bananapi/bananpi_cm4/firmware/acs.bin fip/
+ $ cp $UBDIR/fip/g12a/bl2.bin fip/
+ $ cp $UBDIR/fip/g12a/bl30.bin fip/
+ $ cp $UBDIR/fip/g12a/bl31.img fip/
+ $ cp $UBDIR/fip/g12a/ddr3_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/ddr4_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/ddr4_2d.fw fip/
+ $ cp $UBDIR/fip/g12a/diag_lpddr4.fw fip/
+ $ cp $UBDIR/fip/g12a/lpddr3_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/lpddr4_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/lpddr4_2d.fw fip/
+ $ cp $UBDIR/fip/g12a/piei.fw fip/
+ $ cp $UBDIR/fip/g12a/aml_ddr.fw fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for BananaPi BPI-M2-PRO (S905X3)
+=======================================
+
+BananaPi BPI-M2-PRO is a Single Board Computer manufactured by Sinovoip with the
+following specification:
+
+ - Amlogic S905X3 Arm Cortex-A55 quad-core SoC
+ - 2GB DDR4 SDRAM
+ - 16GB eMMC
+ - Gigabit Ethernet
+ - RTL8821CU USB WiFi (a/b/g/n/ac) + BT 5.0
+ - HDMI 2.1 display
+ - 40-pin GPIO header
+ - 2x USB 3.0 Host
+ - 1x DC Jack (power)
+ - microSD
+ - UART serial
+ - Infrared receiver
+
+Schematics are available from the manufacturer: https://wiki.banana-pi.org/Banana_Pi_BPI-M2_Pro
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make bananapi-m2pro_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh bananapi-m2pro /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+ $ DIR=bananapi-m2pro
+ $ git clone --depth 1 https://github.com/Dangku/amlogic-u-boot.git -b odroidg12-v2015.01-c4-m5 $DIR
+
+ $ cd $DIR
+ $ make bananapi_m2pro_defconfig
+ $ make
+ $ export UBOOTDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ $ cp $UBOOTDIR/build/board/bananapi/bananpi_m5/firmware/acs.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl2.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl30.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl31.img fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/piei.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for BananaPi M2S (A311D & S922X)
+=======================================
+
+BananaPi BPI-M2S ships is a Single Board Computer manufactured by Sinovoip that ships in
+two variants with Amlogic S922X or A311D SoC and the following common specification:
+
+- 16GB eMMC
+- HDMI 2.1a video
+- 2x 10/100/1000 Base-T Ethernet (1x RTL8211F, 1x RTL811H)
+- 2x USB 2.0 ports
+- 2x Status LED's (green/blue)
+- 1x Power/Reset button
+- 1x micro SD card slot
+- 40-pin GPIO header
+- PWM fan header
+- UART header
+
+The S992X variant has:
+- 2GB LPDDR4 RAM
+
+The A311D variant has:
+
+- 4GB LPDDR4 RAM
+- NPU (5.0 TOPS)
+- MIPI DSI header
+- MIPI CSI header
+
+An optional RTL8822CS SDIO WiFi/BT mezzanine is available for both board variants.
+
+Schematics are available from the manufacturer: https://wiki.banana-pi.org/Banana_Pi_BPI-M2S
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make bananapi-m2s_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh bananapi-m2s /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+ $ DIR=bananapi-m2s
+ $ git clone --depth 1 https://github.com/Dangku/amlogic-u-boot.git -b khadas-g12b-v2015.01-m2s $DIR
+
+ $ cd $DIR
+ $ make bananapi_m2s_defconfig
+ $ make
+ $ export UBDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ $ cp $UBDIR/build/scp_task/bl301.bin fip/
+ $ cp $UBDIR/build/board/bananapi/bananpi_m2s/firmware/acs.bin fip/
+ $ cp $UBDIR/fip/g12a/bl2.bin fip/
+ $ cp $UBDIR/fip/g12a/bl30.bin fip/
+ $ cp $UBDIR/fip/g12a/bl31.img fip/
+ $ cp $UBDIR/fip/g12a/ddr3_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/ddr4_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/ddr4_2d.fw fip/
+ $ cp $UBDIR/fip/g12a/diag_lpddr4.fw fip/
+ $ cp $UBDIR/fip/g12a/lpddr3_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/lpddr4_1d.fw fip/
+ $ cp $UBDIR/fip/g12a/lpddr4_2d.fw fip/
+ $ cp $UBDIR/fip/g12a/piei.fw fip/
+ $ cp $UBDIR/fip/g12a/aml_ddr.fw fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ $UBDIR/fip/g12b/aml_encrypt_g12b --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for BananaPi BPI-M5 (S905X3)
+===================================
+
+BananaPi BPI-M5 is a Single Board Computer manufactured by Sinovoip with the following
+specification:
+
+ - Amlogic S905X3 Arm Cortex-A55 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - 16GB eMMC
+ - Gigabit Ethernet
+ - HDMI 2.1 display
+ - 40-pin GPIO header
+ - 4x USB 3.0 Host
+ - 1x USB-C (power)
+ - microSD
+ - UART serial
+ - Infrared receiver
+
+Schematics are available from the manufacturer: https://wiki.banana-pi.org/Banana_Pi_BPI-M5
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make bananapi-m5_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh bananapi-m5 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+ $ DIR=bananapi-m5
+ $ git clone --depth 1 https://github.com/Dangku/amlogic-u-boot.git -b odroidg12-v2015.01-c4-m5 $DIR
+
+ $ cd $DIR
+ $ make bananapi_m5_defconfig
+ $ make
+ $ export UBOOTDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ $ cp $UBOOTDIR/build/board/bananapi/bananpi_m5/firmware/acs.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl2.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl30.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl31.img fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/piei.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Beelink GS-King-X (S922X)
+====================================
+
+The Shenzen AZW (Beelink) GS-King-X is based on the Amlogic W400 reference board with an
+S922X-H chip and the following specifications:
+
+- 4GB LPDDR4 RAM
+- 64GB eMMC storage
+- 10/100/1000 Base-T Ethernet
+- AP6356S Wireless (802.11 a/b/g/n/ac, BT 4.1)
+- HDMI 2.1 video
+- S/PDIF optical output
+- 2x ESS9018 audio DACs
+- 4x Ricor RT6862 audio amps
+- Analogue headphone output
+- 1x USB 2.0 OTG port
+- 3x USB 3.0 ports
+- IR receiver
+- 1x micro SD card slot (internal)
+- USB SATA controller with 2x 3.5" drive bays
+- 1x Power on/off button
+
+Beelink do not provide public schematics, but have been willing to share them with known
+distro developers to assist with development.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make beelink-gsking-x_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh beelink-s922x /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Beelink released an Amlogic "SDK" dump in their forums but the U-Boot sources included
+result in 2GB RAM detected. The following FIPs were generated with newer sources and
+detect 4GB RAM: https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
+
+.. code-block:: bash
+
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/archive/master.zip
+ $ unzip master.zip
+ $ export FIPDIR=$PWD/amlogic-boot-fip/beelink-s922x
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+ $ cp $FIPDIR/* fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ fip/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ fip/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ fip/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ fip/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
+ $ fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ fip/aml_encrypt_g12b --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Beelink GT1 Ultimate (S912)
+======================================
+
+Beelink GT1 Ultimate is an Android STB manufactured by Shenzen AZW (Beelink) with the
+following specification:
+
+- 2GB or 3GB DDR3 RAM
+- 32GB eMMC
+- HDMI 2.1 video
+- S/PDIF optical output
+- 10/100/1000 Ethernet
+- AP6356S Wireless (802.11 a/b/g/n/ac, BT 4.2)
+- 3x USB 2.0 ports
+- IR receiver
+- 1x micro SD card slot
+- 1x Power LED (white)
+- 1x Reset button (internal)
+
+The GT1 (non-ultimate) board has QCA9377 WiFi/BT but is otherwise identical and should
+be capable of booting images prepared for the Ultimate box (NB: there are known clones
+of both boxes which may differ in specifications).
+
+Beelink do not provide public schematics, but have been willing to share them with known
+distro developers on request.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+Â Â Â $ export CROSS_COMPILE=aarch64-none-elf-
+Â Â Â $ make beelink-gt1-ultimate_defconfig
+Â Â Â $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+Â Â Â $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+Â Â Â $ cd amlogic-boot-fip
+Â Â Â $ mkdir my-output-dir
+Â Â Â $ ./build-fip.sh beelink-gt1 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide firmware sources or tools needed to create the bootloader image
+and Beelink has not publicly shared the U-Boot sources needed to build the FIP binaries
+for signing. However you can download them from the amlogic-fip-repo.
+
+.. code-block:: bash
+
+Â Â Â $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+Â Â Â $ cd amlogic-boot-fip/beelink-gt1
+Â Â Â $ export FIPDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+Â Â Â $ mkdir fip
+Â Â Â $ cp $FIPDIR/bl2.bin fip/
+Â Â Â $ cp $FIPDIR/acs.bin fip/
+Â Â Â $ cp $FIPDIR/bl21.bin fip/
+Â Â Â $ cp $FIPDIR/bl30.bin fip/
+Â Â Â $ cp $FIPDIR/bl301.bin fip/
+Â Â Â $ cp $FIPDIR/bl31.img fip/
+Â Â Â $ cp u-boot.bin fip/bl33.bin
+
+Â Â Â $ $FIPDIR/blx_fix.sh \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl30.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/zero_tmp \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl30_zero.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl301.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl301_zero.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl30_new.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â bl30
+
+Â Â Â $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+Â Â Â $ $FIPDIR/blx_fix.sh \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl2_acs.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/zero_tmp \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl2_zero.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl21.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl21_zero.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â fip/bl2_new.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â bl2
+
+Â Â Â $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+Â Â Â $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+Â Â Â $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+Â Â Â $ $FIPDIR/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+Â Â Â $ $FIPDIR/aml_encrypt_gxl --bootmk \
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â --output fip/u-boot.bin \
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â --bl2 fip/bl2.n.bin.sig \
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â --bl30 fip/bl30_new.bin.enc \
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â --bl31 fip/bl31.img.enc \
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â --bl33 fip/bl33.bin.enc
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+Â Â Â $ DEV=/dev/boot_device
+Â Â Â $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+Â Â Â $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Beelink GT-King
-==========================
+U-Boot for Beelink GT-King (S922X)
+==================================
-The Shenzen AZW (Beelink) GT-King is based on the Amlogic W400 reference
-board with an S922X-H chip.
+The Shenzen AZW (Beelink) GT-King is based on the Amlogic W400 reference board with an
+S922X-H chip and the following specifications:
- 4GB LPDDR4 RAM
- 64GB eMMC storage
- IR receiver
- 1x micro SD card slot
-Beelink do not provide public schematics, but have been willing
-to share them with known distro developers on request.
+Beelink do not provide public schematics, but have been willing to share them with known
+distro developers to assist with development.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make beelink-gtking_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-Amlogic does not provide sources for the firmware and for tools needed
-to create the bootloader image. Beelink have provided the Amlogic "SDK"
-in their forums, but the u-boot sources included result in 2GB RAM being
-detected. The following FIPs were generated with newer private sources
-and give correct (4GB) RAM detection:
+.. code-block:: bash
-https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh beelink-s922x /path/to/u-boot/u-boot.bin my-output-dir
-NB: Beelink use a common board config for GT-King, GT-King Pro and the
-GS-King-X model, hence the "beelink-s922x" name.
+U-Boot Manual Signing
+---------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `beelink-s922x`
+Beelink released an Amlogic "SDK" dump in their forums, but the U-Boot sources included
+result in 2GB RAM detected. The following FIPs were generated with newer sources and
+detect 4GB RAM: https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ fip/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ fip/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ fip/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ fip/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ fip/aml_encrypt_g12b --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Beelink GT-King Pro
-==============================
+U-Boot for Beelink GT-King Pro (S922X)
+======================================
-The Shenzen AZW (Beelink) GT-King Pro is based on the Amlogic W400 reference
-board with an S922X-H chip.
+The Shenzen AZW (Beelink) GT-King Pro is based on the Amlogic W400 reference board with
+an S922X-H chip and the following specifications:
- 4GB LPDDR4 RAM
- 64GB eMMC storage
- 1x SD card slot
- 1x Power on/off button
-Beelink do not provide public schematics, but have been willing
-to share them with known distro developers on request.
+Beelink do not provide public schematics, but have been willing to share them with known
+distro developers to assist with development.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make beelink-gtkingpro_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-Amlogic does not provide sources for the firmware and for tools needed
-to create the bootloader image. Beelink have provided the Amlogic "SDK"
-in their forums, but the u-boot sources included result in 2GB RAM being
-detected. The following FIPs were generated with newer private sources
-and give correct (4GB) RAM detection:
+.. code-block:: bash
-https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh beelink-s922x /path/to/u-boot/u-boot.bin my-output-dir
-NB: Beelink use a common board config for GT-King, GT-King Pro and the
-GS-King-X model, hence the "beelink-s922x" name.
+U-Boot Manual Signing
+---------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `beelink-s922x`
+Beelink released an Amlogic "SDK" dump in their forums, but the U-Boot sources included
+result in 2GB RAM detected. The following FIPs were generated with newer sources and
+detect 4GB RAM: https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ fip/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ fip/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ fip/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ fip/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ fip/aml_encrypt_g12b --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
Amlogic SoC Boot Flow
=====================
-The Amlogic SoCs have a pre-defined boot sequence in the SoC ROM code. Here are
-the possible boot sources of different SoC families supported by U-Boot:
+Amlogic SoCs follow a pre-defined boot sequence stored in SoC ROM code. The possible boot
+sequences of the different SoC families are:
-GX* & AXG family
+GX* & AXG Family
----------------
-+----------+--------------------+-------+-------+---------------+---------------+
-| | 1 | 2 | 3 | 4 | 5 |
-+==========+====================+=======+=======+===============+===============+
-| S905 | POC=0: SPI NOR | eMMC | NAND | SD Card | USB Device |
-| S905X | | | | | |
-| S905L | | | | | |
-| S905W | | | | | |
-| S912 | | | | | |
-+----------+--------------------+-------+-------+---------------+---------------+
-| S805X | POC=0: SPI NOR | eMMC | NAND | USB Device | - |
-| A113D | | | | | |
-| A113X | | | | | |
-+----------+--------------------+-------+-------+---------------+---------------+
++----------+-------------------+---------+---------+---------+---------+
+| | 1 | 2 | 3 | 4 | 5 |
++==========+===================+=========+=========+=========+=========+
+| S905 | POC=0: SPI NOR | eMMC | NAND | SD | USB |
+| S905D | | | | | |
+| S905L | | | | | |
+| S905W | | | | | |
+| S905X | | | | | |
+| S905Y | | | | | |
+| S912 | | | | | |
++----------+-------------------+---------+---------+---------+---------+
+| S805X | POC=0: SPI NOR | eMMC | NAND | USB | - |
+| A113D | | | | | |
+| A113X | | | | | |
++----------+-------------------+---------+---------+---------+---------+
POC pin: `NAND_CLE`
-Some boards provide a button to force USB BOOT which disables the eMMC clock signal
-to bypass the eMMC stage. Others have removable eMMC modules; removing the eMMC and
-SDCard will allow boot from USB.
+Some boards provide a button to force USB boot by disabling the eMMC clock signal and
+allowing the eMMC step to be bypassed. Others have removable eMMC modules; removing an
+eMMC module and SD card will allow boot from USB.
-An exception is the lafrite board (aml-s805x-xx) which has no SDCard slot and boots
-from SPI. The only ways to boot the lafrite board from USB are:
+An exception is the Libre Computer AML-S805X-XX (LaFrite) board which has no SD card
+slot and boots from SPI. Booting a LaFrite board from USB requires either:
- - Erase the first sectors of SPI NOR flash
- - Insert an HDMI boot plug forcing boot over USB
+ - Erasing the first sectors of SPI NOR flash
+ - Inserting an HDMI boot plug forcing boot over USB
-The VIM1 and initial VIM2 boards provide a test point on the eMMC signals to block
-the storage from answering and continue to the next boot step.
+The VIM1 and initial VIM2 boards provide a test point on the eMMC signals to block the
+storage from answering, allowing boot to continue with the next boot step.
-The USB Device boot uses the first USB interface. On some boards this port is only
-available on an USB-A type connector and needs an special Type-A to Type-A cable to
-communicate with the BootROM.
+USB boot uses the first USB interface. On some boards this port is only available on a
+USB-A type connector and requires a special Type-A to Type-A cable to communicate with
+the BootROM.
-G12* & SM1 family
+G12* & SM1 Family
-----------------
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| POC0 | POC1 | POC2 | 1 | 2 | 3 | 4 |
-+=======+=======+=======+===============+===============+===============+===============+
-| 0 | 0 | 0 | USB Device | SPI NOR | NAND/eMMC | SDCard |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 0 | 0 | 1 | USB Device | NAND/eMMC | SDCard | - |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 0 | 1 | 0 | SPI NOR | NAND/eMMC | SDCard | USB Device |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 0 | 1 | 1 | SPI NAND | NAND/eMMC | USB Device | - |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 1 | 0 | 0 | USB Device | SPI NOR | NAND/eMMC | SDCard |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 1 | 0 | 1 | USB Device | NAND/eMMC | SDCard | - |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 1 | 1 | 0 | SPI NOR | NAND/eMMC | SDCard | USB Device |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-| 1 | 1 | 1 | NAND/eMMC | SDCard | USB Device | - |
-+-------+-------+-------+---------------+---------------+---------------+---------------+
-
-The last option (1/1/1) is the normal default seen on production devices.
++-------+-------+-------+------------+------------+------------+-----------+
+| POC0 | POC1 | POC2 | 1 | 2 | 3 | 4 |
++=======+=======+=======+============+============+============+===========+
+| 0 | 0 | 0 | USB | SPI-NOR | NAND/eMMC | SD |
++-------+-------+-------+------------+------------+-------------+----------+
+| 0 | 0 | 1 | USB | NAND/eMMC | SD | - |
++-------+-------+-------+------------+------------+------------+-----------+
+| 0 | 1 | 0 | SPI-NOR | NAND/eMMC | SD | USB |
++-------+-------+-------+------------+------------+------------+-----------+
+| 0 | 1 | 1 | SPI-NAND | NAND/eMMC | USB | - |
++-------+-------+-------+------------+------------+------------+-----------+
+| 1 | 0 | 0 | USB | SPI-NOR | NAND/eMMC | SD |
++-------+-------+-------+------------+------------+------------+-----------+
+| 1 | 0 | 1 | USB | NAND/eMMC | SD | - |
++-------+-------+-------+------------+------------+------------+-----------+
+| 1 | 1 | 0 | SPI-NOR | NAND/eMMC | SD | USB |
++-------+-------+-------+------------+------------+------------+-----------+
+| 1 | 1 | 1 | NAND/eMMC | SD | USB | - |
++-------+-------+-------+------------+------------+------------+-----------+
+
+The last option (1/1/1) is the normal default seen on production devices:
* POC0 pin: `BOOT_4` (0 and all other 1 means SPI NAND boot first)
* POC1 pin: `BOOT_5` (0 and all other 1 means USB Device boot first
* POC2 pin: `BOOT_6` (0 and all other 1 means SPI NOR boot first)
Most boards provide a button to force USB BOOT which lowers `BOOT_5` to 0. Some boards
-provide a test point on the eMMC or SPI NOR clock signals to block the storage from
-answering and continue to the next boot step.
+provide a test point on eMMC or SPI NOR clock signals to block storage from answering
+and allowing boot to continue from the next boot step.
-The Khadas VIM3/3L boards embed a microcontroller which sets POC signals according
-to its configuration or a specific key press sequence to either boot from SPI NOR
-or eMMC then SDCard, or boot as an USB Device.
+The Khadas VIM3/3L boards embed a microcontroller which sets POC signals according to
+its configuration or a specific key press sequence to either boot from SPI NOR or eMMC
+then SD card, or boot as a USB device.
-The Odroid N2/N2+ has a hardware switch to select between SPI NOR or eMMC boot.
+The Odroid N2/N2+ has a hardware switch to select between SPI NOR or eMMC boot. The
+Odroid HC4 has a button to disable SPI-NOR allowing boot from SD card.
Boot Modes
----------
- * SDCard
+ * SD
-The BootROM fetches the first SDCard sectors in one sequence, then checks the content
-of the data. The BootROM expects to find the FIP binary in sector 1, 512 bytes offset
-from the start.
+The BootROM fetches the first SD card sectors in one sequence then checks the content of
+the data. It expects to find the FIP binary in sector 1, 512 bytes offset from the start.
* eMMC
-The BootROM fetches the first sectors in one sequence, first on the main partition,
-and then on the Boot0 followed by Boot1 HW partitions. After each read, the BootROM
-checks the data and looks to the next partition if it fails. The BootROM expects to
-find the FIP binary in sector 1, 512 bytes offset from the start.
+The BootROM fetches the first sectors of the main partition in one sequence then checks
+the content of the data. On GXL and newer boards it expects to find the FIP binary in
+sector 1, 512 bytes offset from the start. If not found it checks the boot0 partition,
+then the boot1 partition. On GXBB it expects to find the FIP binary at an offset that
+conflicts with MBR partition tables, but this has been worked around (thus avoiding the
+need for a partition scheme that relocates the MBR). For a more detailed explanation
+please see: https://github.com/LibreELEC/amlogic-boot-fip/pull/8
- * SPI NOR
+ * SPI-NOR
-The BootROM fetches the first SPI NOR sectors in one sequence, then checks the content
-of the data. The BootROM expects to find the FIP binary in sector 1, 512 bytes offset
-from the start.
+The BootROM fetches the first SPI NOR sectors in one sequence then checks the content of
+the data. It expects to find the FIP binary in sector 1, 512 bytes offset from the start.
- * NAND & SPI NAND
+ * NAND & SPI-NAND
These modes are rarely used in open platforms and no details are available.
- * USB Device
+ * USB
-The BootROM sets the USB Gadget interface to serve a custom USB protocol with the
-USB ID 1b8e:c003. The Amlogic `update` utility is designed to use this protocol. It
-is also implemented in the Amlogic Vendor U-Boot.
+The BootROM supports a custom USB protocol and sets the USB Gadget interface to use the
+USB ID 1b8e:c003. The Amlogic `update` utility uses this protocol. It is also supported
+in the Amlogic vendor U-Boot sources.
-The open-source `pyamlboot` utility https://github.com/superna9999/pyamlboot also
-implements this protocol and can load U-Boot in memory in order to start the SoC
-without any attached storage or to recover from a failed/incorrect image flash.
+The `pyamlboot` utility https://github.com/superna9999/pyamlboot is open-source and also
+implements the USB protocol. It can load U-Boot into memory to start the SoC without the
+storage being attached, or to recover the device from a failed/incorrect image flash.
-HDMI Recovery
--------------
+HDMI Recovery Dongle
+--------------------
-The BootROM also briefly reads 8 bytes at address I2C 0x52 offset 0xf8 (248) on the
-HDMI DDC bus. If the content is `boot@USB` it will force USB boot mode. If the content
-is `boot@SDC` it will force SDCard boot mode.
+The BootROM also reads 8 bytes at address I2C 0x52 offset 0xf8 (248) on the HDMI DDC bus
+during startup. The content `boot@USB` forces USB boot. The content `boot@SDC` forces SD
+card boot. The content `boot@SPI` forces SPI-NOT boot. If an SD card or USB device does
+not enumerate the BootROM continues with the normal boot sequence.
-If USB Device doesn't enumerate or SD Card boot step doesn't work, the BootROM will
-continue with the normal boot sequence.
+HDMI boot dongles can be created by connecting a 256bytes EEPROM set to answer on address
+0x52, with `boot@USB` or `boot@SDC` or `boot@SPI` programmed at offset 0xf8 (248).
-Special boot dongles can be built by connecting a 256bytes EEPROM set to answer on
-address 0x52, and program `boot@USB` or `boot@SDC` at offset 0xf8 (248).
-
-Note: If the SoC is booted with USB Device forced at first step, it will keep the boot
-order on warm reboot. Only cold reboot (power removed) will reset the boot order.
+If the SoC is booted with USB Device forced at first step, it will retain the forced boot
+order on warm reboot. Only cold reboot (removing power) will reset the boot order.
This matrix concerns the actual source code version.
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| | S905 | S905X | S912 | A113X | S905X2 | S922X | S905X3 |
-| | | S805X | S905D | | S905D2 | A311D | S905D3 |
-| | | S905W | | | S905Y2 | | |
-+===============================+===========+=================+==============+=============+============+=============+==============+
-| Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 |
-| | Nanopi-K2 | Khadas-VIM | Libretech-PC | JetHub J100 | SEI510 | Khadas-VIM3 | Khadas-VIM3L |
-| | P200 | LibreTech-CC v1 | WeTek Core2 | | Radxa Zero | GT-King/Pro | Odroid-C4 |
-| | P201 | LibreTech-AC v2 | | | | GSKing-X | Odroid-HC4 |
-| | | JetHub J80 | | | | Odroid-Go- | BananaPi-M5 |
-| | | | | | | Ultra | |
-| | | | | | | Odroid-N2L | |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Infrared Decoder | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Fuse access | **Yes** | **Yes** |**Yes** |**Yes** |**Yes** |**Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| SPI (CC) | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| NAND | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| ADC | **Yes** | **Yes** | **Yes** | **Yes** | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| CEC | No | No | No | *N/A* | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Thermal Sensor | No | No | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| LCD/LVDS Output | No | *N/A* | No | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
-| Watchdog | *N/A* | **Yes** | *N/A* | *N/A* | *N/A* | *N/A* | *N/A* |
-+-------------------------------+-----------+-----------------+--------------+-------------+------------+-------------+--------------+
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SoCs | S905 | S805X | S912 | A113X | S905X2 | S922X | S905X3 |
+| | | S905X | S905D | | S905D2 | A311D | S905D3 |
+| | | S905W | | | S905Y2 | | |
++===================+===========+==========+==========+==========+==========+==========+==========+
+| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Infrared Decoder | No | No | No | No | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Fuse access | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SPI (CC) | No | No | No | No | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| NAND | No | No | No | No | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| ADC | **Yes** | **Yes** | **Yes** | **Yes** | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| CEC | No | No | No | *N/A* | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Thermal Sensor | No | No | No | No | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| LCD/LVDS Output | No | *N/A* | No | No | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| SoC Rev/Info | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
+| Watchdog | *N/A* | **Yes** | *N/A* | *N/A* | *N/A* | *N/A* | *N/A* |
++-------------------+-----------+----------+----------+----------+----------+----------+----------+
Boot Documentation
------------------
.. toctree::
:maxdepth: 1
- pre-generated-fip
boot-flow
+ pre-generated-fip
Board Documentation
-------------------
.. toctree::
:maxdepth: 1
+ bananapi-cm4io
+ bananapi-m2pro
+ bananapi-m2s
+ bananapi-m5
+ beelink-gskingx
+ beelink-gt1-ultimate
beelink-gtking
beelink-gtkingpro
- jethub-j100
jethub-j80
+ jethub-j100
+ khadas-vim
khadas-vim2
- khadas-vim3l
khadas-vim3
- khadas-vim
+ khadas-vim3l
libretech-ac
libretech-cc
nanopi-k2
odroid-c2
odroid-c4
+ odroid-hc4
odroid-n2
odroid-n2l
odroid-go-ultra
p212
q200
radxa-zero
- s400
+ radxa-zero2
sei510
sei610
+ s400
u200
wetek-core2
+ wetek-hub
+ wetek-play2
w400
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for JetHub J100
-=======================
+U-Boot for JetHub J100 (A113X)
+==============================
-JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a series of home
-automation controller manufactured by JetHome with the following
-specifications:
+JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation controller device
+manufactured by JetHome with the following specifications:
- Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz
- no video out
- DC source with a voltage of 9 to 56 V / Passive POE
- DIN Rail Mounting case
-Basic version also has:
+The basic version also has:
- - TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output
- power and Zigbee 3.0 support.
+ - TI CC2538 + CC2592 Zigbee Wireless with upto 20dBm output power and Zigbee 3.0
- 1 x 1-Wire
- 2 x RS-485
- 4 x dry contact digital GPIO inputs
- 3 x relay GPIO outputs
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make jethub_j100_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `jethub-j100`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh jethub-j100 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain binaries
-from the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ cd jethub-u-boot
$ export FIPDIR=$PWD
-Go back to mainline U-boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
bl2
$ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $FIPDIR/j100/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ $FIPDIR/j100/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $FIPDIR/j100/aml_encrypt_axg --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc --level v3
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc --level v3
-and then write the image to eMMC with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_emmc_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for JetHub J80
-======================
+U-Boot for JetHub J80 (S905W)
+=============================
-JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation
-controller manufactured by JetHome with the following specifications:
+JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation controller device
+manufactured by JetHome with the following specifications:
- Amlogic S905W (ARM Cortex-A53) quad-core up to 1.5GHz
- No video out
- DC source 5V microUSB
- Square plastic case
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make jethub_j80_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `jethub-j80`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh jethub-j80 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain binaries
-from the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ cd jethub-u-boot
$ export FIPDIR=$PWD
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ $FIPDIR/j80/aml_encrypt_gxl --bl3enc --input fip/bl33.bin --compress lz4
$ $FIPDIR/j80/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $FIPDIR/j80/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-and then write the image to SD/eMMC with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Khadas VIM
-======================
+U-Boot for Khadas VIM (S905X)
+=============================
-Khadas VIM is an Open Source DIY Box manufactured by Shenzhen Wesion
-Technology Co., Ltd with the following specifications:
+Khadas VIM is a Single Board Computer manufactured by Shenzhen Wesion Technology Co. Ltd
+with the following specifications:
- Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
- 2GB DDR3 SDRAM
+ - 8GB/16GB eMMC
- 10/100 Ethernet
- HDMI 2.0 4K/60Hz display
- 40-pin GPIO header
- 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG
- - 8GB/16GBeMMC
- microSD
- SDIO Wifi Module, Bluetooth
- - Two channels IR receiver
+ - Two channel IR receiver
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make khadas-vim_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh khadas-vim /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Khadas VIM2
-=======================
+U-Boot for Khadas VIM2 (S912)
+=============================
-Khadas VIM2 is an Open Source DIY Box manufactured by Shenzhen Wesion
-Technology Co., Ltd with the following specifications:
+Khadas VIM2 is a Single Board Computer manufactured by Shenzhen Wesion Technology Co. Ltd
+with the following specifications:
- Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
- ARM Mali T860 GPU
- - 2/3GB DDR4 SDRAM
+ - 2GB/3GB DDR4 SDRAM
+ - 16GB/32GB/64GB eMMC
- 10/100/1000 Ethernet
- HDMI 2.0 4K/60Hz display
- 40-pin GPIO header
- 2 x USB 2.0 Host, 1 x USB 2.0 Type-C OTG
- - 16GB/32GB/64GB eMMC
- 2MB SPI Flash
- microSD
- SDIO Wifi Module, Bluetooth
- Two channels IR receiver
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make khadas-vim2_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh khadas-vim2 /path/to/u-boot/u-boot.bin my-output-dir
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim2`
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export FIPDIR=$PWD/fip
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
$ DEV=/dev/your_sd_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Khadas VIM3
-======================
+U-Boot for Khadas VIM3 (A311D)
+==============================
-Khadas VIM3 is a single board computer manufactured by Shenzhen Wesion
-Technology Co., Ltd. with the following specifications:
+Khadas VIM3 is a Single Board Computer manufactured by Shenzhen Wesion Technology Co. Ltd
+with the following specifications:
- Amlogic A311D Arm Cortex-A53 dual-core + Cortex-A73 quad-core SoC
- 4GB LPDDR4 SDRAM
PCIe Setup
----------
-The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
-lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
-an USB3.0 Type A connector and a M.2 Key M slot.
-The PHY driving these differential lines is shared between
-the USB3.0 controller and the PCIe Controller, thus only
-a single controller can use it.
-To setup for PCIe, run the following commands from U-Boot:
+The on-board MCU can mux the PCIe/USB3.0 shared differential lines using a FUSB340TMX USB
+3.1 SuperSpeed Data Switch between a USB3.0 Type-A connector and an M.2 Key M slot. The
+PHY driving these differential lines is shared between the USB3.0 controller and the PCIe
+Controller, thus only a single controller can use it.
+
+To setup for PCIe run the following commands from U-Boot then power-cycle the board:
.. code-block:: none
i2c dev i2c@5000
i2c mw 0x18 0x33 1
-Then power-cycle the board.
-
-To set back to USB3.0, run the following commands from U-Boot:
+To revert to USB3.0 run the following commands from U-Boot then power-cycle the board:
.. code-block:: none
i2c dev i2c@5000
i2c mw 0x18 0x33 0
-Then power-cycle the board.
-
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make khadas-vim3_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh khadas-vim3 /path/to/u-boot/u-boot.bin my-output-dir
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim3`
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
$ DIR=vim3-u-boot
- $ git clone --depth 1 \
- https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \
- $DIR
+ $ git clone --depth 1 https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 $DIR
$ cd vim3-u-boot
$ make kvim3_defconfig
$ make CROSS_COMPILE=aarch64-none-elf-
$ export UBOOTDIR=$PWD
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ bash fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ bash fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33 --compress lz4
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --ddrfw9 fip/lpddr3_1d.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Khadas VIM3L
-=======================
+U-Boot for Khadas VIM3L (S905D3)
+================================
-Khadas VIM3L is a single board computer manufactured by Shenzhen Wesion
-Technology Co., Ltd. with the following specifications:
+Khadas VIM3L is a Single Board Computer manufactured by Shenzhen Wesion Technology Co. Ltd
+with the following specifications:
- Amlogic S905D3 Arm Cortex-A55 quad-core SoC
- 2GB LPDDR4 SDRAM
PCIe Setup
----------
-The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
-lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
-an USB3.0 Type A connector and a M.2 Key M slot.
-The PHY driving these differential lines is shared between
-the USB3.0 controller and the PCIe Controller, thus only
-a single controller can use it.
-To setup for PCIe, run the following commands from U-Boot:
+The on-board MCU can mux the PCIe/USB3.0 shared differential lines using a FUSB340TMX USB
+3.1 SuperSpeed Data Switch between a USB3.0 Type-A connector and an M.2 Key-M slot. The
+PHY driving these differential lines is shared between the USB3.0 controller and the PCIe
+Controller, thus only a single controller can use it.
+
+To setup for PCIe run the following commands from U-Boot then power-cycle the board:
.. code-block:: none
i2c dev i2c@5000
i2c mw 0x18 0x33 1
-Then power-cycle the board.
-
-To set back to USB3.0, run the following commands from U-Boot:
+To revert to USB3.0 run the following commands from U-Boot then power-cycle the board:
.. code-block:: none
i2c dev i2c@5000
i2c mw 0x18 0x33 0
-Then power-cycle the board.
-
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make khadas-vim3l_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh khadas-vim3l /path/to/u-boot/u-boot.bin my-output-dir
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `khadas-vim3l`
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
$ DIR=vim3l-u-boot
- $ git clone --depth 1 \
- https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 \
- $DIR
+ $ git clone --depth 1 https://github.com/khadas/u-boot.git -b khadas-vims-v2015.01 $DIR
$ cd vim3l-u-boot
$ make kvim3l_defconfig
$ make CROSS_COMPILE=aarch64-none-elf-
$ export UBOOTDIR=$PWD
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ bash fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ bash fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33 --compress lz4
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --ddrfw9 fip/lpddr3_1d.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for LibreTech AC
-=======================
+U-Boot for LibreTech-AC 'LaFrite' (S805X)
+=========================================
-LibreTech AC is a single board computer manufactured by Libre Technology
+LibreTech-AC aka 'LaFrite' is a Single Board Computer manufactured by Libre Computer
with the following specifications:
- Amlogic S805X ARM Cortex-A53 quad-core SoC @ 1.2GHz
- HDMI 2.0 4K/60Hz display
- 40-pin GPIO header
- 4 x USB 2.0 Host
- - eMMC, SPI NOR Flash
+ - SPI NOR Flash
+ - Removable eMMC module
- Infrared receiver
Schematics are available on the manufacturer website.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make libretech-ac_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `lafrite`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh lafrite /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export UBOOTDIR=$PWD
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic buildroot package and extract it:
.. code-block:: bash
$ tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180418/bootloader
$ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180418
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh $UBOOTDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ $BRDIR/bootloader/uboot-repo/fip/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ sh $UBOOTDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
$ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
$ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
$ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-and then write the image to SD with:
+Then write U-Boot to USB or SPI-NOR with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for LibreTech CCs
-========================
+U-Boot for LibreTech CC 'LePotato' (S905X)
+==========================================
-LibreTech CC is a single board computer manufactured by Libre Technology
-with the following specifications:
+LibreTech CC is a Single Board Computer manufactured by Libre Computer Technology with
+the following specifications:
-V1:
+v1:
- Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
- Infrared receiver
- Jack for CVBS and Audio
-V2:
+v2:
- Added SPI NOR
- Removed Jack
Schematics are available on the manufacturer website.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
Use libretech-cc_v2_defconfig for v2.
-Image creation
---------------
-
-To boot the system, u-boot must be combined with several earlier stage
-bootloaders:
-
-* bl2.bin: vendor-provided binary blob
-* bl21.bin: built from vendor u-boot source
-* bl30.bin: vendor-provided binary blob
-* bl301.bin: built from vendor u-boot source
-* bl31.bin: vendor-provided binary blob
-* acs.bin: built from vendor u-boot source
-
-These binaries and the tools required below have been collected and prebuilt
-for convenience at <https://github.com/BayLibre/u-boot/releases/>. These
-apply to both v1 and v2.
-
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `lepotato`
-
-Download and extract the libretech-cc release from there, and set FIPDIR to
-point to the `fip` subdirectory.
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
.. code-block:: bash
- $ export FIPDIR=/path/to/extracted/fip
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh lepotato /path/to/u-boot/u-boot.bin my-output-dir
-Alternatively, you can obtain the original vendor u-boot tree which
-contains the required blobs and sources, and build yourself.
-Note that old compilers are required for this to build. The compilers here
-are suggested by Amlogic, and they are 32-bit x86 binaries.
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export FIPDIR=$PWD/fip
-Once you have the binaries available (either through the prebuilt download,
-or having built the vendor u-boot yourself), you can then proceed to glue
-everything together. Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
-
-Note that Amlogic provides aml_encrypt_gxl as a 32-bit x86 binary with no
-source code. Should you prefer to avoid that, there are open source reverse
-engineered versions available:
-
-1. gxlimg <https://github.com/repk/gxlimg>, which comes with a handy
- Makefile that automates the whole process.
-2. meson-tools <https://github.com/afaerber/meson-tools>
-
-However, these community-developed alternatives are not endorsed by or
-supported by Amlogic.
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for NanoPi-K2
-====================
+U-Boot for NanoPi-K2 (S905)
+===========================
-NanoPi-K2 is a single board computer manufactured by FriendlyElec
-with the following specifications:
+NanoPi-K2 is a single board computer manufactured by FriendlyElec with the following
+specifications:
- Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
Schematics are available on the manufacturer website.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make nanopi-k2_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `nanopi-k2`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh nanopi-k2 /path/to/u-boot/u-boot.bin my-output-dir
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
$ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
$ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
- $ git clone https://github.com/BayLibre/u-boot.git -b libretech-cc amlogic-u-boot
$ git clone https://github.com/friendlyarm/u-boot.git -b nanopi-k2-v2015.01 amlogic-u-boot
$ cd amlogic-u-boot
$ sed -i 's/aarch64-linux-gnu-/aarch64-none-elf-/' Makefile
$ make
$ export FIPDIR=$PWD/fip
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp $FIPDIR/gxb/bl301.bin fip/
$ cp $FIPDIR/gxb/bl31.img fip/
$ cp u-boot.bin fip/bl33.bin
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/bl1.bin.hardkernel fip/bl1.bin.hardkernel
+ $ chmod +x fip/bl1.bin.hardkernel
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/aml_chksum fip/aml_chksum
+ $ chmod +x fip/aml_chksum
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
-
- $ $FIPDIR/fip_create \
- --bl30 fip/bl30_new.bin \
- --bl31 fip/bl31.img \
- --bl33 fip/bl33.bin \
- fip/fip.bin
-
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+ --bl31 fip/bl31.img \
+ --bl33 fip/bl33.bin \
+ fip/fip.bin
+
+ $ sed -i 's/\x73\x02\x08\x91/\x1F\x20\x03\xD5/' fip/bl2.bin
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin
$ $FIPDIR/gxb/aml_encrypt_gxb --bootsig \
- --input fip/boot_new.bin
- --output fip/u-boot.bin
+ --input fip/boot_new.bin
+ --output fip/u-boot.bin
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
- $ dd if=fip/u-boot.bin of=$DEV conv=fsync,notrunc bs=512 seek=1
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+ $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+ $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+ $ ./aml_chksum fip/u-boot.bin.gxbb
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for ODROID-C2
-====================
+U-Boot for ODROID-C2 (S905)
+===========================
-ODROID-C2 is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
+ODROID-C2 is a single board computer manufactured by Hardkernel with the following
+specifications:
- - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
- 2GB DDR3 SDRAM
- Gigabit Ethernet
- eMMC, microSD
- Infrared receiver
-Schematics are available on the manufacturer website.
+Schematics are available on the manufacturer website: https://wiki.odroid.com
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make odroid-c2_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-c2`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh odroid-c2 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ DIR=odroid-c2
- $ git clone --depth 1 \
- https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \
- $DIR
+ $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 $DIR
+
$ $DIR/fip/fip_create --bl30 $DIR/fip/gxb/bl30.bin \
- --bl301 $DIR/fip/gxb/bl301.bin \
- --bl31 $DIR/fip/gxb/bl31.bin \
- --bl33 u-boot.bin \
- $DIR/fip.bin
+ --bl301 $DIR/fip/gxb/bl301.bin \
+ --bl31 $DIR/fip/gxb/bl31.bin \
+ --bl33 u-boot.bin \
+ $DIR/fip.bin
+
$ $DIR/fip/fip_create --dump $DIR/fip.bin
$ cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin
$ $DIR/fip/gxb/aml_encrypt_gxb --bootsig \
- --input $DIR/boot_new.bin \
- --output $DIR/u-boot.img
+ --input $DIR/boot_new.bin \
+ --output $DIR/u-boot.img
$ dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/your_boot_device
$ BL1=$DIR/sd_fuse/bl1.bin.hardkernel
$ dd if=$BL1 of=$DEV conv=fsync bs=1 count=442
$ dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for ODROID-C4
-====================
+U-Boot for ODROID-C4 (S905X3)
+=============================
-ODROID-C4 is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
+ODROID-C4 is a Single Board Computer manufactured by Hardkernel with the following
+specifications:
- Amlogic S905X3 Arm Cortex-A55 quad-core SoC
- 4GB DDR4 SDRAM
- UART serial
- Infrared receiver
-The ODROID-HC4 is a variant with a PCIe-SATA controller, the same commands
-applies for HC4.
-
Schematics are available on the manufacturer website.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make odroid-c4_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh odroid-c4 /path/to/u-boot/u-boot.bin my-output-dir
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-c4` or `odroid-hc4`
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export UBOOTDIR=$PWD
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33 --compress lz4
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --ddrfw9 fip/lpddr3_1d.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write the image to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for ODROID-GO-ULTRA
-==========================
+U-Boot for ODROID-GO-ULTRA (S922X)
+==================================
-The Odroid Go Ultra is a portable gaming device with the following
-characteristics:
+The ODROID GO ULTRA is a portable gaming device with the following characteristics:
- Amlogic S922X SoC
- RK817 & RK818 PMICs
- 2x ADC Analog Joysticks
- USB-C Port for USB2 Device and Charging
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make odroid-go-ultra_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-Pleaser refer to :doc:`pre-generated-fip` with codename `odroid-go-ultra`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh odroid-go-ultra /path/to/u-boot/u-boot.bin my-output-dir
+
+Then write the image to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for ODROID-HC4 (S905X3)
+==============================
+
+ODROID-HC4 is a variant of the ODROID-C4 single board computer manufactured by Hardkernel
+with the following specification:
+
+ - Amlogic S905X3 Arm Cortex-A55 quad-core SoC
+ - 4GB DDR4 SDRAM
+ - 16MB XT25F128B SPI-NOR flash
+ - Gigabit Ethernet
+ - HDMI 2.1 display
+ - 7-pin GPIO header for OLED display and RTC
+ - 1x USB 2.0 host (micro)
+ - 2x SATA ports via ASM1061 PCIe to SATA controller
+ - microSD
+ - UART serial
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make odroid-hc4_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh odroid-hc4 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+
+ $ DIR=odroid-hc4
+ $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidg12-v2015.01 $DIR
+
+ $ cd odroid-hc4
+ $ make odroidc4_defconfig
+ $ make
+ $ export UBOOTDIR=$PWD
+
+Go back to mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh
+ $ cp $UBOOTDIR/build/scp_task/bl301.bin fip/
+ $ cp $UBOOTDIR/build/board/hardkernel/odroidc4/firmware/acs.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl2.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl30.bin fip/
+ $ cp $UBOOTDIR/fip/g12a/bl31.img fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr3_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr4_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/ddr4_2d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/diag_lpddr4.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr3_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr4_1d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/lpddr4_2d.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/piei.fw fip/
+ $ cp $UBOOTDIR/fip/g12a/aml_ddr.fw fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ $UBOOTDIR/fip/g12a/aml_encrypt_g12a --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --ddrfw9 fip/lpddr3_1d.fw \
+ --level v3
+
+Then write U-Boot to SD or SPI-NOR with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for ODROID-N2
-====================
+U-Boot for ODROID-N2/N2+ (S922X)
+================================
-ODROID-N2 is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
+ODROID-N2 and ODROID-N2+ are a Single Board Computers manufactured by Hardkernel with the
+following specifications:
- Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
- 4GB DDR4 SDRAM
- eMMC, microSD
- Infrared receiver
-Schematics are available on the manufacturer website.
+ODROID-N2+ uses Rev-C silicon allowing higher CPU opp-points. U-Boot contains logic to
+read the model detail from SARADC and select the correct device-tree file if FDTDIR is
+used instead of an FDT reference to a specfic device-tree.
-U-Boot compilation
+Schematics are available on the manufacturer website: https://wiki.odroid.com
+
+U-Boot Compilation
------------------
.. code-block:: bash
$ make odroid-n2_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh odroid-n2 /path/to/u-boot/u-boot.bin my-output-dir
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-n2` or `odroid-n2-plus`
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
$ DIR=odroid-n2
- $ git clone --depth 1 \
- https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 \
- $DIR
+ $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 $DIR
$ cd odroid-n2
$ make odroidn2_defconfig
$ make
$ export UBOOTDIR=$PWD
- Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33 --compress lz4
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33 --compress lz4
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for ODROID-N2L
-=====================
+U-Boot for ODROID-N2L (S922X)
+=============================
-ODROID-N2L is a single board computer manufactured by Hardkernel
-Co. Ltd with the following specifications:
+ODROID-N2L is a Single Board Computer manufactured by Hardkernel with the following
+specifications:
- Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
- 4GB DDR4 SDRAM
- HDMI 2.1 4K/60Hz display
- 40-pin GPIO header
- - 1 x USB 3.0 Host, 1 x USB USB 2.0 Host
+ - 1x USB 3.0 Host
+ - 1x USB 2.0 Host
- eMMC, microSD
- MIPI DSI Port
-Schematics are available on the manufacturer website.
+Schematics are available on the manufacturer website: https://wiki.odroid.com
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make odroid-n2l_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `odroid-n2l`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh odroid-n2l /path/to/u-boot/u-boot.bin my-output-dir
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic P200
-=======================
+U-Boot for Amlogic P200 (S905)
+==============================
-P200 is a reference board manufactured by Amlogic with the following
-specifications:
+P200 is a reference board manufactured by Amlogic with the following specification:
- Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
- 2GB DDR3 SDRAM
- Gigabit Ethernet
- HDMI 2.0 4K/60Hz display
- - 2 x USB 2.0 Host
+ - 2x USB 2.0 Host
- eMMC, microSD
- Infrared receiver
- SDIO WiFi Module
- - CVBS+Stereo Audio Jack
+ - CVBS + Stereo Audio Jack
Schematics are available from Amlogic on demand.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make p200_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `p200`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh p200 /path/to/u-boot/u-boot.bin my-output-dir
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image but sources have been shared by Linux development contractor, Baylibre:
.. code-block:: bash
$ make
$ export FIPDIR=$PWD/fip
-Go back to mainline U-boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp $FIPDIR/gxb/bl301.bin fip/
$ cp $FIPDIR/gxb/bl31.img fip/
$ cp u-boot.bin fip/bl33.bin
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/bl1.bin.hardkernel fip/bl1.bin.hardkernel
+ $ chmod +x fip/bl1.bin.hardkernel
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/aml_chksum fip/aml_chksum
+ $ chmod +x fip/aml_chksum
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
-
- $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin --bl31 fip/bl31.img --bl33 fip/bl33.bin fip/fip.bin
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+ --bl31 fip/bl31.img \
+ --bl33 fip/bl33.bin \
+ fip/fip.bin
$ cat fip/bl2_new.bin fip/fip.bin >fip/boot_new.bin
- $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig --input fip/boot_new.bin --output fip/u-boot.bin
+ $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig \
+ --input fip/boot_new.bin \
+ --output fip/u-boot.bin
and then write the image to SD with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+ $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+ $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+ $ ./aml_chksum fip/u-boot.bin.gxbb
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic P201
-=======================
+U-Boot for Amlogic P201 (S905)
+==============================
-P201 is a reference board manufactured by Amlogic with the following
-specifications:
+P201 is a reference board manufactured by Amlogic with the following specifications:
- Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
- 2GB DDR3 SDRAM
- 10/100 Ethernet
- HDMI 2.0 4K/60Hz display
- - 2 x USB 2.0 Host
+ - 2x USB 2.0 Host
- eMMC, microSD
- Infrared receiver
- SDIO WiFi Module
- - CVBS+Stereo Audio Jack
+ - CVBS + Stereo Audio Jack
Schematics are available from Amlogic on demand.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make p201_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `p201`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh p201 /path/to/u-boot/u-boot.bin my-output-dir
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image but sources have been shared by Linux development contractor, Baylibre:
.. code-block:: bash
$ cp $FIPDIR/gxb/bl301.bin fip/
$ cp $FIPDIR/gxb/bl31.img fip/
$ cp u-boot.bin fip/bl33.bin
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/bl1.bin.hardkernel fip/bl1.bin.hardkernel
+ $ chmod +x fip/bl1.bin.hardkernel
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/raw/master/nanopi-k2/aml_chksum fip/aml_chksum
+ $ chmod +x fip/aml_chksum
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
-
- $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin --bl31 fip/bl31.img --bl33 fip/bl33.bin fip/fip.bin
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+ --bl31 fip/bl31.img \
+ --bl33 fip/bl33.bin \
+ fip/fip.bin
$ cat fip/bl2_new.bin fip/fip.bin >fip/boot_new.bin
- $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig --input fip/boot_new.bin --output fip/u-boot.bin
+ $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig \
+ --input fip/boot_new.bin \
+ --output fip/u-boot.bin
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+ $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+ $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+ $ ./aml_chksum fip/u-boot.bin.gxbb
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-Pre-Generated FIP file set
-==========================
+Pre-Generated FIP File Repo
+===========================
-The Amlogic ARMv8 based SoCs uses a vendor variant of the Trusted Firmware-A
-boot architecture.
+Pre-built Flattened Image Package (FIP) sources and Amlogic signing binaries for many
+commercially available boards and some Android STB devices are collected for use with
+distro build-systems here: https://github.com/LibreELEC/amlogic-boot-fip
-You can find documentation on the Trusted Firmware-A architecture on: https://www.trustedfirmware.org/projects/tf-a/
+Using the pre-built FIP sources to sign U-Boot is simple, e.g. for LePotato:
-The Trusted Firmware-A uses the following boot elements (simplified):
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh lepotato /path/to/u-boot/u-boot.bin my-output-dir
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
+
+Files Included
+--------------
+
+Amlogic ARMv8 SoCs use a vendor modified variant of the ARM Trusted Firmware-A boot
+architecture. See documentation here: https://www.trustedfirmware.org/projects/tf-a/
+
+Trusted Firmware-A uses the following boot elements (simplified):
+
+- BL1: First boot step implemented in ROM on Amlogic SoCs
+
+- BL2: Second boot step used to initialize the SoC main clocks & DDR interface. BL21
+ and ACS board-specific binaries must be "inserted" into the BL2 binary before signing
+ and packaging in order to be flashed on the platform
+
+- BL30: Amlogic Secure Co-Processor (SCP) firmware used to handle all system management
+ operations (DVFS, suspend/resume, ..)
+
+- BL301: Amlogic Secure Co-Processor (SCP) board-specific firmware "plug-in" to handle
+ custom DVFS & suspend-resume parameters
-- BL1: First boot step, implemented in ROM on Amlogic SoCs
-- BL2: Second boot step, used to initialize the SoC main clocks & DDR interface. The BL21 and ACS board-specific binaries are "inserted" in the BL32 binary before signing/packaging in order to be flashed on the platform.
-- BL30: Amlogic Secure Co-Processor (SCP) firmware used to handle all the system management operations (DVFS, suspend/resume, ...)
-- BL301: Amlogic Secure Co-Processor (SCP) board-specific firmware "plug-in" to handle custom DVFS & suspend-resume parameters
- BL31: Initializes the interrupt controller and the system management interface (PSCI)
-- BL32 (Optional): Is the Trusted Environment Execution (TEE) Operating System to run secure Trusted Apps, e.g. OP-TEE
+
+- BL32 (Optional): Is the Trusted Environment Execution (TEE) Operating System used to
+ run secure Trusted Apps, e.g. OP-TEE
+
- BL33: Is the last non-secure step, usually U-Boot which loads Linux
-Amlogic provides in binary form:
+Amlogic sources provide the following binaries:
- bl2.bin
- bl30.bin
- bl31.img
- bl32.bin
-And for lastest SoCs, Amlogic also provides the DDR drivers used by the BL2 binary.
+For G12A/B and SM1 Amlogic also provides DDR drivers used by the BL2 binary:
+
+- ddr4_1d.fw
+- ddr4_2d.fw
+- ddr3_1d.fw
+- piei.fw
+- lpddr4_1d.fw
+- lpddr4_2d.fw
+- diag_lpddr4.fw
+- aml_ddr.fw
+
+The following files are generated from the Amlogic U-Boot fork:
+
+- acs.bin: Contains the PLL & DDR parameters for the board
+- bl301.bin: Contains the DVFS & suspend-resume handling code for the board
+- bl33.bin: U-boot binary image
+
+The acs.bin and bl301.bin files use U-Boot GPL-2.0+ headers and U-Boot build system and
+are thus considered to be issued from GPL-2.0+ source code.
+
+Amlogic alo provides pre-compiled x86_64 and Python2 binaries:
-The licence of these files wasn't clear until recently, the currently Amlogic distribution licence
-is the following:
+- aml_encrypt_gxb
+- aml_encrypt_gxl
+- aml_encrypt_g12a
+- aml_encrypt_g12b
+- acs_tool.pyc
+
+The repo replaces the pre-compiled acs_tool.pyc with a Python3 acs_tool.py that can be
+used with modern build hosts.
+
+The repo also provides the following files used with GXBB boards:
+
+- bl1.bin.hardkernel
+- aml_chksum
+
+The repo also supports the open-source 'gxlimg' signing tool that can be used to sign
+U-Boot binaries for GXL/GXM/G12A/G12B/SM1 boards: https://github.com/repk/gxlimg
+
+Licensing
+---------
+
+The licence of Amlogic provided binaries was not historically clear but has now been
+clarified. The current Amlogic distribution licence is below:
.. code-block:: C
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-The following files are generated from the Amlogic U-Boot fork:
-
-- acs.bin: contains the PLL & DDR parameters for the board
-- bl301.bin: contains the DVFS & suspend-resume handling code for the board
-- bl33.bin: U-boot binary image
-
-The acs.bin & bl301.bin uses the U-Boot GPL-2.0+ headers & build systems, thus those
-are considered issued from GPL-2.0+ source code.
-
-The tools used to sign & package those binary files are delivered in binary format
-for Intel x86-64 and Python 2.x only.
-
-A collection of pre-built with the corresponding Amlogic binaries for the common
-commercially available boards were collected in the https://github.com/LibreELEC/amlogic-boot-fip
-repository.
-
-Using this collection for a commercially available board is very easy.
-
-Here considering the Libre Computer AML-S905X-CC, which codename is `lepotato`:
-
-.. code-block:: bash
-
- $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
- $ cd amlogic-boot-fip
- $ mkdir my-output-dir
- $ ./build-fip.sh lepotato /path/to/u-boot/u-boot.bin my-output-dir
-
-and then write the image to SD with:
-
-.. code-block:: bash
-
- $ DEV=/dev/your_sd_device
- $ dd if=my-output-dir/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=my-output-dir/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic Q200
-=======================
+U-Boot for Amlogic Q200 (S912)
+==============================
-Q200 is a reference board manufactured by Amlogic with the following
-specifications:
+Q200 is a reference board manufactured by Amlogic with the following specifications:
- Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
- ARM Mali T860 GPU
- 2/3GB DDR4 SDRAM
- 10/100/1000 Ethernet
- HDMI 2.0 4K/60Hz display
- - 2 x USB 2.0 Host, 1 x USB 2.0 Device
+ - 2x USB 2.0 Host
+ - 1x USB 2.0 Device
- 16GB/32GB/64GB eMMC
- 2MB SPI Flash
- microSD
- SDIO Wifi Module, Bluetooth
- IR receiver
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make khadas-vim2_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh q200 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image but sources have been shared by Linux development contractor, Baylibre:
.. code-block:: bash
$ make
$ export FIPDIR=$PWD/fip
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Radxa Zero
-=====================
+U-Boot for Radxa Zero (S905Y2)
+==============================
-Radxa Zero is a small form factor SBC based on the Amlogic S905Y2
-chipset that ships in a number of RAM/eMMC configurations:
+Radxa Zero is a small form factor SBC based on the Amlogic S905Y2 chipset that ships in
+a number of RAM/eMMC configurations:
-Boards with 512MB/1GB LPDDR4 RAM have no eMMC storage and BCM43436
-wireless (2.4GHz b/g/n) while 2GB/4GB boards have 8/16/32/64/128GB
-eMMC storage and BCM4345 wireless (2.4/5GHz a/b/g/n/ac).
+512MB/1GB LPDDR4 RAM boards have no eMMC and BCM43436 wireless (2.4GHz b/g/n) while the
+2GB/4GB boards have 8/16/32/64/128GB eMMC and BCM4345 wireless (2.4/5GHz a/b/g/n/ac).
- Amlogic S905Y2 quad-core Cortex-A53
- Mali G31-MP2 GPU
- 1x micro SD Card slot
- 40 Pin GPIO header
-Schematics are available on the manufacturer website:
+Schematics are available on the manufacturer website: https://dl.radxa.com/zero/docs/hw
-https://dl.radxa.com/zero/docs/hw/RADAX_ZERO_V13_SCH_20210309.pdf
-
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make radxa-zero_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh radxa-zero /path/to/u-boot/u-boot.bin my-output-dir
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `radxa-zero`
+U-Boot Manual Signing
+---------------------
-Amlogic does not provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-git trees published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ cd ../fip/radxa-zero
$ make
-This will generate:
+This will generate the signed U-Boot binaries:
.. code-block:: bash
$ u-boot.bin u-boot.bin.sd.bin u-boot.bin.usb.bl2 u-boot.bin.usb.tpl
-Then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Radxa Zero2 (A311D)
+==============================
+
+Radxa Zero2 is a small form factor SBC based on the Amlogic A311D chipset with the
+following specification:
+
+- Amlogic A311D (Quad A73 + Dual A53) CPU
+- 4GB LPDDR4 RAM
+- 32/64/128GB eMMC
+- Mali G52-MP4 GPU
+- HDMI 2.1 output (micro)
+- BCM4345 WiFi (2.4/5GHz a/b/g/n/ac) and BT 5.0
+- 1x USB 2.0 port - Type C (OTG)
+- 1x USB 3.0 port - Type C (Host)
+- 1x micro SD Card slot
+- 40 Pin GPIO header
+
+Schematics are available on request from Radxa.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make radxa-zero2_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh radxa-zero2 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
+
+.. code-block:: bash
+
+ $ git clone -b radxa-zero-v2021.07 https://github.com/radxa/u-boot.git
+ $ git clone https://github.com/radxa/fip.git
+
+ $ sudo apt-get install -y gcc-aarch64-linux-gnu device-tree-compiler libncurses5 libncurses5-dev
+ $ sudo apt-get install -y bc python dosfstools flex build-essential libssl-dev mtools
+
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz
+ $ sudo tar xvf gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz -C /opt
+
+ $ export CROSS_COMPILE=/opt/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf/bin/aarch64-none-elf-
+ $ export ARCH=arm
+ $ cd u-boot
+ $ make radxa-zero2_defconfig
+ $ make
+
+ $ cp u-boot.bin ../fip/radxa-zero2/bl33.bin
+ $ cd ../fip/radxa-zero2
+ $ make
+
+This will generate the signed U-Boot binaries:
+
+.. code-block:: bash
+
+ $ u-boot.bin u-boot.bin.sd.bin u-boot.bin.usb.bl2 u-boot.bin.usb.tpl
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic S400
-=======================
+U-Boot for Amlogic S400 (A113X)
+===============================
-S400 is a reference board manufactured by Amlogic with the following
-specifications:
+S400 is a reference board manufactured by Amlogic with the following specifications:
- - Amlogic A113DX ARM Cortex-A53 quad-core SoC @ 1.2GHz
+ - Amlogic A113X ARM Cortex-A53 quad-core SoC @ 1.2GHz
- 1GB DDR4 SDRAM
- 10/100 Ethernet
- - 2 x USB 2.0 Host
+ - 2x USB 2.0 Host
- eMMC
- Infrared receiver
- SDIO WiFi Module
Schematics are available from Amlogic on demand.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make s400_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `s400`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh s400 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image but sources have been shared by Linux development contractor, Baylibre:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $FIPDIR/axg/aml_encrypt_axg --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ $FIPDIR/axg/aml_encrypt_axg --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $FIPDIR/axg/aml_encrypt_axg --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc --level v3
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc --level v3
-and then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic SEI510
-=========================
+U-Boot for Amlogic SEI510 (S905X2)
+==================================
-SEI510 is a customer board manufactured by SEI Robotics with the following
-specifications:
+SEI510 is a customer board manufactured by SEI Robotics with the following specification:
- Amlogic S905X2 ARM Cortex-A53 quad-core SoC
- 2GB DDR4 SDRAM
- 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
+ - 1x USB 3.0 Host
- eMMC
- SDcard
- Infrared receiver
- SDIO WiFi Module
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make sei510_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `sei510`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh sei510 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export UBOOTDIR=$PWD
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic Buildroot package and extract it:
.. code-block:: bash
$ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
$ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic SEI610
-=========================
+U-Boot for Amlogic SEI610 (S905X3)
+==================================
-SEI610 is a customer board manufactured by SEI Robotics with the following
-specifications:
+SEI610 is a customer board manufactured by SEI Robotics with the following specification:
- Amlogic S905X3 ARM Cortex-A55 quad-core SoC
- 2GB DDR4 SDRAM
- 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
- - 1 x USB Type-C DRD
- - 1 x FTDI USB Serial Debug Interface
+ - 1x USB 3.0 Host
+ - 1x USB Type-C DRD
+ - 1x FTDI USB Serial Debug Interface
- eMMC
- SDcard
- Infrared receiver
- SDIO WiFi Module
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make sei610_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `sei610`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh sei610 /path/to/u-boot/u-boot.bin my-output-dir
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export UBOOTDIR=$PWD
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic buildroot package and extract it:
.. code-block:: bash
$ export BRDIR=$PWD/buildroot-openlinux-A113-201901
$ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
-Go back to mainline U-Boot source tree then :
-
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic U200
-=======================
+U-Boot for Amlogic U200 (S905X2)
+================================
-U200 is a reference board manufactured by Amlogic with the following
-specifications:
+U200 is a reference board manufactured by Amlogic with the following specification:
- Amlogic S905D2 ARM Cortex-A53 quad-core SoC
- 2GB DDR4 SDRAM
- 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
+ - 1x USB 3.0 Host
- eMMC
- SDcard
- Infrared receiver
Schematics are available from Amlogic on demand.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make u200_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `u200`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh u200 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export UBOOTDIR=$PWD
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic buildroot package and extract it:
.. code-block:: bash
$ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
$ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $FIPDIR/g12a/aml_encrypt_g12a --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for Amlogic W400
-=======================
+U-Boot for Amlogic W400 (S922X)
+===============================
-U200 is a reference board manufactured by Amlogic with the following
-specifications:
+W400 is a reference board manufactured by Amlogic with the following specification:
- Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
- 2GB DDR4 SDRAM
- 10/100 Ethernet (Internal PHY)
- - 1 x USB 3.0 Host
+ - 1x USB 3.0 Host
- eMMC
- SDcard
- Infrared receiver
Schematics are available from Amlogic on demand.
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make w400_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-Amlogic doesn't provide sources for the firmware and for tools needed
-to create the bootloader image, so it is necessary to obtain them from
-the git tree published by the board vendor:
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh jethub-j100 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image so it is necessary to obtain binaries from sources published by the board vendor:
.. code-block:: bash
$ make
$ export UBOOTDIR=$PWD
-Download the latest Amlogic Buildroot package, and extract it :
+Download the latest Amlogic buildroot package and extract it:
.. code-block:: bash
$ export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706
$ export FIPDIR=$BRDIR/bootloader/uboot-repo/fip
-Go back to mainline U-Boot source tree then :
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp u-boot.bin fip/bl33.bin
$ sh fip/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
$ sh fip/blx_fix.sh \
- fip/bl2.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/acs.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
$ $FIPDIR/g12b/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
- --output fip/bl30_new.bin.g12a.enc \
- --level v3
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
$ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
- --output fip/bl30_new.bin.enc \
- --level v3 --type bl30
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
$ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
- --output fip/bl31.img.enc \
- --level v3 --type bl31
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
$ $FIPDIR/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
- --output fip/bl33.bin.enc \
- --level v3 --type bl33
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
$ $FIPDIR/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
- --output fip/bl2.n.bin.sig
+ --output fip/bl2.n.bin.sig
$ $FIPDIR/g12b/aml_encrypt_g12b --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc \
- --ddrfw1 fip/ddr4_1d.fw \
- --ddrfw2 fip/ddr4_2d.fw \
- --ddrfw3 fip/ddr3_1d.fw \
- --ddrfw4 fip/piei.fw \
- --ddrfw5 fip/lpddr4_1d.fw \
- --ddrfw6 fip/lpddr4_2d.fw \
- --ddrfw7 fip/diag_lpddr4.fw \
- --ddrfw8 fip/aml_ddr.fw \
- --level v3
-
-and then write the image to SD with:
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for WeTek Core2
-======================
+U-Boot for WeTek Core2 (S912)
+=============================
-WeTek Core2 is an Android STB based on the Q200 reference design with
-the following specifications:
+WeTek Core2 is an Android STB based on the Q200 reference design with the following
+specifications:
- Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
- ARM Mali T820 GPU
- 3GB DDR4 SDRAM
- 10/100 Realtek RTL8152 Ethernet (internal USB)
- HDMI 2.0 4K/60Hz display
- - 2x USB 2.0 Host, 1x USB 2.0 OTG (internal)
+ - 2x USB 2.0 Host
+ - 1x USB 2.0 OTG (internal)
- 32GB eMMC
- microSD
- SDIO Wifi Module, Bluetooth
- Two channel IR receiver
-U-Boot compilation
+U-Boot Compilation
------------------
.. code-block:: bash
$ make wetek-core2_defconfig
$ make
-Image creation
---------------
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
-For simplified usage, pleaser refer to :doc:`pre-generated-fip` with codename `wetek-core2`
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh wetek-core2 /path/to/u-boot/u-boot.bin my-output-dir
-Amlogic does not provide sources for the firmware or the tools needed
-to create the bootloader image, and WeTek has not publicly shared the
-precompiled FIP binaries. However the public Khadas VIM2 sources also
-work with the Core2 box so we can use the Khadas git tree:
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide firmware sources or tools needed to create the bootloader image
+and WeTek has not publicly shared the precompiled FIP binaries. However the Khadas VIM2
+sources also work with the Core2 box so we can use the Khadas git tree:
.. code-block:: bash
$ make
$ export FIPDIR=$PWD/fip
-Go back to mainline U-Boot source tree then:
+Go back to the mainline U-Boot source tree then:
.. code-block:: bash
$ cp $FIPDIR/gxl/bl301.bin fip/
$ cp $FIPDIR/gxl/bl31.img fip/
$ cp u-boot.bin fip/bl33.bin
+
$ $FIPDIR/blx_fix.sh \
- fip/bl30.bin \
- fip/zero_tmp \
- fip/bl30_zero.bin \
- fip/bl301.bin \
- fip/bl301_zero.bin \
- fip/bl30_new.bin \
- bl30
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
$ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
$ $FIPDIR/blx_fix.sh \
- fip/bl2_acs.bin \
- fip/zero_tmp \
- fip/bl2_zero.bin \
- fip/bl21.bin \
- fip/bl21_zero.bin \
- fip/bl2_new.bin \
- bl2
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
$ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
$ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
$ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
- --output fip/u-boot.bin \
- --bl2 fip/bl2.n.bin.sig \
- --bl30 fip/bl30_new.bin.enc \
- --bl31 fip/bl31.img.enc \
- --bl33 fip/bl33.bin.enc
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
-then write the image to SD with:
+Then write U-Boot to SD or eMMC with:
.. code-block:: bash
- $ DEV=/dev/your_sd_device
+ $ DEV=/dev/boot_device
$ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
- $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for WeTek Hub (S905)
+===========================
+
+WeTek Hub is a small form-factor Android STB manufactured by WeTek with the following
+specification:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 1GB DDR3 SDRAM
+ - 8GB eMMC
+ - Gigabit Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 1x USB otg
+ - microSD
+ - UART jack
+ - Infrared receiver
+
+Schematics are not publicly available but have been shared privately to maintainers.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make wetek-hub_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh wetek-hub /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image and WeTek has not publicly shared the U-Boot sources needed to build FIP binaries
+for signing. However you can download them from the amlogic-fip-repo.
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip/wetek-hub
+ $ export FIPDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ cp $FIPDIR/bl2.bin fip/
+ $ cp $FIPDIR/acs.bin fip/
+ $ cp $FIPDIR/bl21.bin fip/
+ $ cp $FIPDIR/bl30.bin fip/
+ $ cp $FIPDIR/bl301.bin fip/
+ $ cp $FIPDIR/bl31.img fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+ --bl31 fip/bl31.img \
+ --bl33 fip/bl33.bin \
+ fip/fip.bin
+
+ $ sed -i 's/\x73\x02\x08\x91/\x1F\x20\x03\xD5/' fip/bl2.bin
+ $ python3 $FIPDIR/acs_tool.py fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin
+
+ $ $FIPDIR/aml_encrypt_gxb --bootsig \
+ --input fip/boot_new.bin
+ --output fip/u-boot.bin
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+ $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+ $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+ $ ./aml_chksum fip/u-boot.bin.gxbb
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for WeTek Play2 (S905)
+=============================
+
+WeTek Play2 is an Android STB manufactured by WeTek with the following specification:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - 8GB eMMC
+ - Gigabit Ethernet
+ - AP6335 (v1) or AP6255 (v2) WiFi (b/g/n) and BT 4.0
+ - HDMI 2.0 4K/60Hz display
+ - 2x USB 2.0 host
+ - 1x USB 2.0 otg
+ - microSD
+ - UART jack
+ - Infrared receiver
+ - Power LED (blue)
+ - Power button (case, front)
+ - Reset button (underside)
+ - DVB Card: DVB-S or DVB-T/C or ATSC
+
+Schematics are not publicly available but have been shared privately to maintainers.
+
+U-Boot Compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make wetek-play2_defconfig
+ $ make
+
+U-Boot Signing with Pre-Built FIP repo
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip
+ $ mkdir my-output-dir
+ $ ./build-fip.sh wetek-play2 /path/to/u-boot/u-boot.bin my-output-dir
+
+U-Boot Manual Signing
+---------------------
+
+Amlogic does not provide sources for the firmware and tools needed to create a bootloader
+image and WeTek has not publicly shared the U-Boot sources needed to build FIP binaries
+for signing. However you can download them from the amlogic-fip-repo.
+
+.. code-block:: bash
+
+ $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1
+ $ cd amlogic-boot-fip/wetek-play2
+ $ export FIPDIR=$PWD
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+
+ $ cp $FIPDIR/bl2.bin fip/
+ $ cp $FIPDIR/acs.bin fip/
+ $ cp $FIPDIR/bl21.bin fip/
+ $ cp $FIPDIR/bl30.bin fip/
+ $ cp $FIPDIR/bl301.bin fip/
+ $ cp $FIPDIR/bl31.img fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \
+ --bl31 fip/bl31.img \
+ --bl33 fip/bl33.bin \
+ fip/fip.bin
+
+ $ sed -i 's/\x73\x02\x08\x91/\x1F\x20\x03\xD5/' fip/bl2.bin
+ $ python3 $FIPDIR/acs_tool.py fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin
+
+ $ $FIPDIR/aml_encrypt_gxb --bootsig \
+ --input fip/boot_new.bin
+ --output fip/u-boot.bin
+
+Then write U-Boot to SD or eMMC with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/boot_device
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync
+ $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc
+ $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc
+ $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc
+ $ ./aml_chksum fip/u-boot.bin.gxbb
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440
sipeed/index
socionext/index
st/index
+ starfive/index
ste/index
tbs/index
ti/index
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+StarFive
+========
+
+.. toctree::
+ :maxdepth: 1
+
+ visionfive2
--- /dev/null
+.. SPDX-License-Identifier: GPL-2.0+
+
+StarFive VisionFive2
+====================
+
+JH7110 RISC-V SoC
+---------------------
+The JH7110 is 4+1 64-bit RISC-V SoC from StarFive.
+
+The StarFive VisionFive2 development platform is based on JH7110 and capable
+of running Linux.
+
+Mainline support
+----------------
+
+The support for following drivers are already enabled:
+
+1. ns16550 UART Driver.
+2. StarFive JH7110 clock Driver.
+3. StarFive JH7110 reset Driver.
+4. Cadence QSPI controller Driver.
+5. MMC SPI Driver for MMC/SD support.
+
+Booting from MMC using U-Boot SPL
+---------------------------------
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g OpenSBI) is required to
+boot the u-boot.itb in S-mode and provide M-mode runtime services.
+
+Currently, the u-boot.itb is used as a dynamic of the OpenSBI FW_DYNAMIC
+firmware with the latest.
+
+Building
+~~~~~~~~
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be
+cloned and built for JH7110 as below:
+
+.. code-block:: console
+
+ git clone https://github.com/riscv/opensbi.git
+ cd opensbi
+ make PLATFORM=generic FW_TEXT_START=0x40000000 FW_OPTIONS=0
+
+More detailed description of steps required to build FW_DYNAMIC firmware
+is beyond the scope of this document. Please refer OpenSBI documenation.
+(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git)
+
+Now build the U-Boot SPL and U-Boot proper
+
+.. code-block:: console
+
+ cd <U-Boot-dir>
+ make starfive_visionfive2_13b_defconfig
+ make OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
+
+This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
+
+u-boot-spl.bin cannot be used directly on StarFive VisionFive2,we need
+to convert the u-boot-spl.bin to u-boot-spl.bin.normal.out with
+the below command:
+
+ ./spl_tool -c -f $(Uboot_PATH)/spl/u-boot-spl.bin
+
+More detailed description of spl_tool,please refer spl_tool documenation.
+(Note: spl_tool git repo is at https://github.com/starfive-tech/Tools/tree/master/spl_tool)
+
+This will generate u-boot-spl.bin.normal.out file.
+
+Flashing
+~~~~~~~~
+
+SPL loads the U-Boot SPL (u-boot-spl.bin.normal.out) from a partition with GUID type
+2E54B353-1271-4842-806F-E436D6AF6985
+
+U-Boot SPL expects a U-Boot FIT image (u-boot.itb) from a partition with GUID
+type BC13C2FF-59E6-4262-A352-B275FD6F7172
+
+FIT image (u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin and
+device tree blob (jh7110-starfive-visionfive-2-v1.3b.dtb/jh7110-starfive-visionfive-2-v1.2a.dtb)
+
+Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
+
+.. code-block:: bash
+
+ sudo sgdisk --clear \
+ --set-alignment=2 \
+ --new=1:4096:8191 --change-name=1:spl --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985\
+ --new=2:8192:16383 --change-name=2:uboot --typecode=2:BC13C2FF-59E6-4262-A352-B275FD6F7172 \
+ --new=3:16384:1654784 --change-name=3:system --typecode=3:EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 \
+ /dev/sdb
+
+Program the SD card
+
+.. code-block:: bash
+
+ sudo dd if=u-boot-spl.bin.normal.out of=/dev/sdb1
+ sudo dd if=u-boot.itb of=/dev/sdb2
+
+ sudo mount /dev/sdb3 /mnt/
+ sudo cp u-boot-spl.bin.normal.out /mnt/
+ sudo cp u-boot.itb /mnt/
+ sudo cp Image.gz /mnt/
+ sudo cp initramfs.cpio.gz /mnt/
+ sudo cp jh7110-starfive-visionfive-2-v1.3b.dtb /mnt/
+ sudo umount /mnt
+
+Booting
+~~~~~~~
+
+Change DIP switches MSEL[1:0] are set to 10, select the boot mode to SD.
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Sample boot log from StarFive VisionFive2 board
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code-block:: none
+
+
+ U-Boot SPL 2023.04-rc2-00055-gfc43b9c51a-dirty (Mar 02 2023 - 10:51:39 +0800)
+ DDR version: dc2e84f0.
+ Trying to boot from MMC2
+
+ OpenSBI v1.2-80-g4b28afc
+ ____ _____ ____ _____
+ / __ \ / ____| _ \_ _|
+ | | | |_ __ ___ _ __ | (___ | |_) || |
+ | | | | '_ \ / _ \ '_ \ \___ \| _ < | |
+ | |__| | |_) | __/ | | |____) | |_) || |_
+ \____/| .__/ \___|_| |_|_____/|___/_____|
+ | |
+ |_|
+
+ Platform Name : StarFive VisionFive 2 v1.3B
+ Platform Features : medeleg
+ Platform HART Count : 5
+ Platform IPI Device : aclint-mswi
+ Platform Timer Device : aclint-mtimer @ 4000000Hz
+ Platform Console Device : uart8250
+ Platform HSM Device : ---
+ Platform PMU Device : ---
+ Platform Reboot Device : ---
+ Platform Shutdown Device : ---
+ Platform Suspend Device : ---
+ Firmware Base : 0x40000000
+ Firmware Size : 264 KB
+ Firmware RW Offset : 0x20000
+ Runtime SBI Version : 1.0
+
+ Domain0 Name : root
+ Domain0 Boot HART : 2
+ Domain0 HARTs : 0*,1*,2*,3*,4*
+ Domain0 Region00 : 0x0000000002000000-0x000000000200ffff M: (I,R,W) S/U: ()
+ Domain0 Region01 : 0x0000000040000000-0x000000004001ffff M: (R,X) S/U: ()
+ Domain0 Region02 : 0x0000000040000000-0x000000004007ffff M: (R,W) S/U: ()
+ Domain0 Region03 : 0x0000000000000000-0xffffffffffffffff M: (R,W,X) S/U: (R,W,X)
+ Domain0 Next Address : 0x0000000040200000
+ Domain0 Next Arg1 : 0x0000000040287970
+ Domain0 Next Mode : S-mode
+ Domain0 SysReset : yes
+ Domain0 SysSuspend : yes
+
+ Boot HART ID : 2
+ Boot HART Domain : root
+ Boot HART Priv Version : v1.11
+ Boot HART Base ISA : rv64imafdcbx
+ Boot HART ISA Extensions : none
+ Boot HART PMP Count : 8
+ Boot HART PMP Granularity : 4096
+ Boot HART PMP Address Bits: 34
+ Boot HART MHPM Count : 2
+ Boot HART MIDELEG : 0x0000000000000222
+ Boot HART MEDELEG : 0x000000000000b109
+
+
+ U-Boot 2023.04-rc2-00055-gfc43b9c51a-dirty (Mar 02 2023 - 10:51:39 +0800)
+
+ CPU: rv64imac_zba_zbb
+ Model: StarFive VisionFive 2 v1.3B
+ DRAM: 8 GiB
+ Core: 107 devices, 18 uclasses, devicetree: separate
+ MMC: mmc@16010000: 0, mmc@16020000: 1
+ Loading Environment from nowhere... OK
+ In: serial@10000000
+ Out: serial@10000000
+ Err: serial@10000000
+ Net: No ethernet found.
+ Working FDT set to ff74a340
+ Hit any key to stop autoboot: 0
+ StarFive #
+ StarFive #version
+ U-Boot 2023.04-rc2-00055-gfc43b9c51a-dirty (Mar 02 2023 - 10:51:39 +0800)
+
+ riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot VF2_515_v1.0.0_rc4) 10.3.0
+ GNU ld (GNU Binutils) 2.36.1
+ StarFive #
+ StarFive #mmc dev 1
+ switch to partitions #0, OK
+ mmc1 is current device
+ StarFive #mmc info
+ Device: mmc@16020000
+ Manufacturer ID: 9f
+ OEM: 5449
+ Name: SD64G
+ Bus Speed: 50000000
+ Mode: SD High Speed (50MHz)
+ Rd Block Len: 512
+ SD version 3.0
+ High Capacity: Yes
+ Capacity: 58.3 GiB
+ Bus Width: 4-bit
+ Erase Group Size: 512 Bytes
+ StarFive #
+ StarFive #mmc part
+
+ Partition Map for MMC device 1 -- Partition Type: EFI
+
+ Part Start LBA End LBA Name
+ Attributes
+ Type GUID
+ Partition GUID
+ 1 0x00001000 0x00001fff "spl"
+ attrs: 0x0000000000000000
+ type: 2e54b353-1271-4842-806f-e436d6af6985
+ (2e54b353-1271-4842-806f-e436d6af6985)
+ guid: d5ee2056-3020-475b-9a33-25b4257c9f12
+ 2 0x00002000 0x00003fff "uboot"
+ attrs: 0x0000000000000000
+ type: bc13c2ff-59e6-4262-a352-b275fd6f7172
+ (bc13c2ff-59e6-4262-a352-b275fd6f7172)
+ guid: 379ab7fe-fd0c-4149-b758-960c1cbfc0cc
+ 3 0x00004000 0x00194000 "system"
+ attrs: 0x0000000000000000
+ type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
+ (data)
+ guid: 539a6df9-4655-4953-8541-733ca36eb1db
+ StarFive #
+ StarFive #fatls mmc 1:3
+ 6429424 Image.gz
+ 717705 u-boot.itb
+ 125437 u-boot-spl.bin.normal.out
+ 152848495 initramfs.cpio.gz
+ 11285 jh7110-starfive-visionfive-2-v1.3b.dtb
+
+ 5 file(s), 0 dir(s)
+
+ StarFive #fatload mmc 1:3 ${kernel_addr_r} Image.gz
+ 6429424 bytes read in 394 ms (15.6 MiB/s)
+ StarFive #fatload mmc 1:3 ${fdt_addr_r} jh7110-starfive-visionfive-2-v1.3b.dtb
+ 11285 bytes read in 5 ms (2.2 MiB/s)
+ StarFive #fatload mmc 1:3 ${ramdisk_addr_r} initramfs.cpio.gz
+ 152848495 bytes read in 9271 ms (15.7 MiB/s)
+ StarFive #booti ${kernel_addr_r} ${ramdisk_addr_r}:${filesize} ${fdt_addr_r}
+ Uncompressing Kernel Image
+ ## Flattened Device Tree blob at 46000000
+ Booting using the fdt blob at 0x46000000
+ Working FDT set to 46000000
+ Loading Ramdisk to f5579000, end fe73d86f ... OK
+ Loading Device Tree to 00000000f5573000, end 00000000f5578c14 ... OK
+ Working FDT set to f5573000
+
+ Starting kernel ...
+
+
+ ] Linux version 6.2.0-starfive-00026-g11934a315b67 (wyh@wyh-VirtualBox) (riscv64-linux-gnu-gcc (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0, GNU ld (GNU Binutils for Ubuntu) 2.30) #1 SMP Thu Mar 2 14:51:36 CST 2023
+ [ 0.000000] OF: fdt: Ignoring memory range 0x40000000 - 0x40200000
+ [ 0.000000] Machine model: StarFive VisionFive 2 v1.3B
+ [ 0.000000] efi: UEFI not found.
+ [ 0.000000] Zone ranges:
+ [ 0.000000] DMA32 [mem 0x0000000040200000-0x00000000ffffffff]
+ [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
+ [ 0.000000] Movable zone start for each node
+ [ 0.000000] Early memory node ranges
+ [ 0.000000] node 0: [mem 0x0000000040200000-0x000000013fffffff]
+ [ 0.000000] Initmem setup node 0 [mem 0x0000000040200000-0x000000013fffffff]
+ [ 0.000000] On node 0, zone DMA32: 512 pages in unavailable ranges
+ [ 0.000000] SBI specification v1.0 detected
+ [ 0.000000] SBI implementation ID=0x1 Version=0x10002
+ [ 0.000000] SBI TIME extension detected
+ [ 0.000000] SBI IPI extension detected
+ [ 0.000000] SBI RFENCE extension detected
+ [ 0.000000] SBI HSM extension detected
+ [ 0.000000] CPU with hartid=0 is not available
+ [ 0.000000] CPU with hartid=0 is not available
+ [ 0.000000] CPU with hartid=0 is not available
+ [ 0.000000] riscv: base ISA extensions acdfim
+ [ 0.000000] riscv: ELF capabilities acdfim
+ [ 0.000000] percpu: Embedded 18 pages/cpu s35960 r8192 d29576 u73728
+ [ 0.000000] pcpu-alloc: s35960 r8192 d29576 u73728 alloc=18*4096
+ [ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
+ [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031688
+ [ 0.000000] Kernel command line: console=ttyS0,115200 debug rootwait earlycon=sbi
+ [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
+ [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
+ [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
+ [ 0.000000] software IO TLB: area num 4.
+ [ 0.000000] software IO TLB: mapped [mem 0x00000000f1573000-0x00000000f5573000] (64MB)
+ [ 0.000000] Virtual kernel memory layout:
+ [ 0.000000] fixmap : 0xffffffc6fee00000 - 0xffffffc6ff000000 (2048 kB)
+ [ 0.000000] pci io : 0xffffffc6ff000000 - 0xffffffc700000000 ( 16 MB)
+ [ 0.000000] vmemmap : 0xffffffc700000000 - 0xffffffc800000000 (4096 MB)
+ [ 0.000000] vmalloc : 0xffffffc800000000 - 0xffffffd800000000 ( 64 GB)
+ [ 0.000000] modules : 0xffffffff0136a000 - 0xffffffff80000000 (2028 MB)
+ [ 0.000000] lowmem : 0xffffffd800000000 - 0xffffffd8ffe00000 (4094 MB)
+ [ 0.000000] kernel : 0xffffffff80000000 - 0xffffffffffffffff (2047 MB)
+ [ 0.000000] Memory: 3867604K/4192256K available (8012K kernel code, 4919K rwdata, 4096K rodata, 2190K init, 476K bss, 324652K reserved, 0K cma-reserved)
+ [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+ [ 0.000000] rcu: Hierarchical RCU implementation.
+ [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4.
+ [ 0.000000] rcu: RCU debug extended QS entry/exit.
+ [ 0.000000] Tracing variant of Tasks RCU enabled.
+ [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
+ [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+ [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
+ [ 0.000000] CPU with hartid=0 is not available
+ [ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
+ [ 0.000000] riscv-intc: 64 local interrupts mapped
+ [ 0.000000] plic: interrupt-controller@c000000: mapped 136 interrupts with 4 handlers for 9 contexts.
+ [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
+ [ 0.000000] riscv-timer: riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [4]
+ [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 881590404240 ns
+ [ 0.000003] sched_clock: 64 bits at 4MHz, resolution 250ns, wraps every 2199023255500ns
+ [ 0.000437] Console: colour dummy device 80x25
+ [ 0.000568] Calibrating delay loop (skipped), value calculated using timer frequency.. 8.00 BogoMIPS (lpj=16000)
+ [ 0.000602] pid_max: default: 32768 minimum: 301
+ [ 0.000752] LSM: initializing lsm=capability,integrity
+ [ 0.001071] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
+ [ 0.001189] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
+ [ 0.004201] CPU node for /cpus/cpu@0 exist but the possible cpu range is :0-3
+ [ 0.007426] cblist_init_generic: Setting adjustable number of callback queues.
+ [ 0.007457] cblist_init_generic: Setting shift to 2 and lim to 1.
+ [ 0.007875] riscv: ELF compat mode unsupported
+ [ 0.007902] ASID allocator disabled (0 bits)
+ [ 0.008405] rcu: Hierarchical SRCU implementation.
+ [ 0.008426] rcu: Max phase no-delay instances is 1000.
+ [ 0.009247] EFI services will not be available.
+ [ 0.010738] smp: Bringing up secondary CPUs ...
+ [ 0.018358] smp: Brought up 1 node, 4 CPUs
+ [ 0.021776] devtmpfs: initialized
+ [ 0.027337] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+ [ 0.027389] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
+ [ 0.027888] pinctrl core: initialized pinctrl subsystem
+ [ 0.029881] NET: Registered PF_NETLINK/PF_ROUTE protocol family
+ [ 0.030401] audit: initializing netlink subsys (disabled)
+ [ 0.031041] audit: type=2000 audit(0.028:1): state=initialized audit_enabled=0 res=1
+ [ 0.031943] cpuidle: using governor menu
+ [ 0.043011] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
+ [ 0.043033] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
+ [ 0.044943] iommu: Default domain type: Translated
+ [ 0.044965] iommu: DMA domain TLB invalidation policy: strict mode
+ [ 0.046089] SCSI subsystem initialized
+ [ 0.046733] libata version 3.00 loaded.
+ [ 0.047231] usbcore: registered new interface driver usbfs
+ [ 0.047315] usbcore: registered new interface driver hub
+ [ 0.047420] usbcore: registered new device driver usb
+ [ 0.049770] vgaarb: loaded
+ [ 0.050277] clocksource: Switched to clocksource riscv_clocksource
+ [ 0.084690] NET: Registered PF_INET protocol family
+ [ 0.085561] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
+ [ 0.093010] tcp_listen_portaddr_hash hash table entries: 2048 (order: 4, 65536 bytes, linear)
+ [ 0.093152] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
+ [ 0.093224] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
+ [ 0.093821] TCP bind hash table entries: 32768 (order: 9, 2097152 bytes, linear)
+ [ 0.117880] TCP: Hash tables configured (established 32768 bind 32768)
+ [ 0.118500] UDP hash table entries: 2048 (order: 5, 196608 bytes, linear)
+ [ 0.118881] UDP-Lite hash table entries: 2048 (order: 5, 196608 bytes, linear)
+ [ 0.119675] NET: Registered PF_UNIX/PF_LOCAL protocol family
+ [ 0.121749] RPC: Registered named UNIX socket transport module.
+ [ 0.121776] RPC: Registered udp transport module.
+ [ 0.121784] RPC: Registered tcp transport module.
+ [ 0.121791] RPC: Registered tcp NFSv4.1 backchannel transport module.
+ [ 0.121816] PCI: CLS 0 bytes, default 64
+ [ 0.124101] Unpacking initramfs...
+ [ 0.125468] workingset: timestamp_bits=46 max_order=20 bucket_order=0
+ [ 0.128372] NFS: Registering the id_resolver key type
+ [ 0.128498] Key type id_resolver registered
+ [ 0.128525] Key type id_legacy registered
+ [ 0.128625] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
+ [ 0.128649] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
+ [ 0.129358] 9p: Installing v9fs 9p2000 file system support
+ [ 0.130179] NET: Registered PF_ALG protocol family
+ [ 0.130499] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
+ [ 0.130544] io scheduler mq-deadline registered
+ [ 0.130556] io scheduler kyber registered
+ [ 0.416754] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+ [ 0.420857] SuperH (H)SCI(F) driver initialized
+ [ 0.443735] loop: module loaded
+ [ 0.448605] e1000e: Intel(R) PRO/1000 Network Driver
+ [ 0.448627] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
+ [ 0.450716] usbcore: registered new interface driver uas
+ [ 0.450832] usbcore: registered new interface driver usb-storage
+ [ 0.451638] mousedev: PS/2 mouse device common for all mice
+ [ 0.453465] sdhci: Secure Digital Host Controller Interface driver
+ [ 0.453487] sdhci: Copyright(c) Pierre Ossman
+ [ 0.453584] sdhci-pltfm: SDHCI platform and OF driver helper
+ [ 0.454140] usbcore: registered new interface driver usbhid
+ [ 0.454174] usbhid: USB HID core driver
+ [ 0.454833] riscv-pmu-sbi: SBI PMU extension is available
+ [ 0.454920] riscv-pmu-sbi: 16 firmware and 4 hardware counters
+ [ 0.454942] riscv-pmu-sbi: Perf sampling/filtering is not supported as sscof extension is not available
+ [ 0.457071] NET: Registered PF_INET6 protocol family
+ [ 0.460627] Segment Routing with IPv6
+ [ 0.460821] In-situ OAM (IOAM) with IPv6
+ [ 0.461005] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
+ [ 0.462712] NET: Registered PF_PACKET protocol family
+ [ 0.462933] 9pnet: Installing 9P2000 support
+ [ 0.463141] Key type dns_resolver registered
+ [ 0.463168] start plist test
+ [ 0.469261] end plist test
+ [ 0.506774] debug_vm_pgtable: [debug_vm_pgtable ]: Validating architecture page table helpers
+ [ 0.553683] gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation.
+ [ 0.554741] starfive-jh7110-sys-pinctrl 13040000.pinctrl: StarFive GPIO chip registered 64 GPIOs
+ [ 0.555900] gpio gpiochip1: Static allocation of GPIO base is deprecated, use dynamic allocation.
+ [ 0.556772] starfive-jh7110-aon-pinctrl 17020000.pinctrl: StarFive GPIO chip registered 4 GPIOs
+ [ 0.559454] printk: console [ttyS0] disabled
+ [ 0.579948] 10000000.serial: ttyS0 at MMIO 0x10000000 (irq = 3, base_baud = 1500000) is a 16550A
+ [ 0.580082] printk: console [ttyS0] enabled
+ [ 13.642680] Freeing initrd memory: 149264K
+ [ 13.651051] Freeing unused kernel image (initmem) memory: 2188K
+ [ 13.666431] Run /init as init process
+ [ 13.670116] with arguments:
+ [ 13.673168] /init
+ [ 13.675488] with environment:
+ [ 13.678668] HOME=/
+ [ 13.681038] TERM=linux
+ Starting syslogd: OK
+ Starting klogd: OK
+ Running sysctl: OK
+ Populating /dev using udev: [ 14.145944] udevd[93]: starting version 3.2.10
+ [ 15.214287] random: crng init done
+ [ 15.240816] udevd[94]: starting eudev-3.2.10
+ done
+ Saving random seed: OK
+ Starting system message bus: dbus[122]: Unknown username "pulse" in message bus configuration file
+ done
+ Starting rpcbind: OK
+ Starting iptables: OK
+ Starting bluetoothd: OK
+ Starting network: Waiting for interface eth0 to appear............... timeout!
+ run-parts: /etc/network/if-pre-up.d/wait_iface: exit status 1
+ FAIL
+ Starting dropbear sshd: OK
+ Starting NFS statd: OK
+ Starting NFS services: OK
+ Starting NFS daemon: rpc.nfsd: Unable to access /proc/fs/nfsd errno 2 (No such file or directory).
+ Please try, as root, 'mount -t nfsd nfsd /proc/fs/nfsd' and then restart rpc.nfsd to correct the problem
+ FAIL
+ Starting NFS mountd: OK
+ Starting DHCP server: FAIL
+
+ Welcome to Buildroot
+ buildroot login:
+
+Booting from SPI
+----------------
+
+Use Building steps from "Booting from MMC using U-Boot SPL" section.
+
+Partition the SPI in Linux via mtdblock. (Require to boot the board in
+SD boot mode by enabling MTD block in Linux)
+
+Use prebuilt image from here [1], which support to partition the SPI flash.
+
+
+Program the SPI (Require to boot the board in SD boot mode)
+
+Execute below steps on U-Boot proper,
+
+.. code-block:: none
+
+ sf probe
+ fatload mmc 1:3 $kernel_addr_r u-boot.itb
+ sf update $kernel_addr_r 0x100000 $filesize
+
+ fatload mmc 1:3 $kernel_addr_r u-boot-spl.bin.normal.out
+ sf update $kernel_addr_r 0x0 $filesize
+
+
+Power off the board
+
+Change DIP switches MSEL[1:0] are set to 00, select the boot mode to flash
+
+Power up the board.
static const struct udevice_id sifive_ccache_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
{ .compatible = "sifive,fu740-c000-ccache" },
+ { .compatible = "sifive,ccache0" },
{}
};
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sifive/Kconfig"
+source "drivers/clk/starfive/Kconfig"
source "drivers/clk/stm32/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/ti/Kconfig"
obj-y += analogbits/
obj-y += imx/
+obj-$(CONFIG_CLK_JH7110) += starfive/
obj-y += tegra/
obj-y += ti/
obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+config SPL_CLK_JH7110
+ bool "SPL clock support for JH7110"
+ depends on STARFIVE_JH7110 && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM support for clock driver in JH7110.
+
+config CLK_JH7110
+ bool "StarFive JH7110 clock support"
+ depends on STARFIVE_JH7110
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for StarFive JH7110 SoC platform.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += clk-jh7110.o
+obj-y += clk-jh7110-pll.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022-23 StarFive Technology Co., Ltd.
+ *
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm/device.h>
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx"
+
+#define PLL_PD_OFF 1
+#define PLL_PD_ON 0
+
+#define CLK_DDR_BUS_MASK GENMASK(29, 24)
+#define CLK_DDR_BUS_OFFSET 0xAC
+#define CLK_DDR_BUS_OSC_DIV2 0
+#define CLK_DDR_BUS_PLL1_DIV2 1
+#define CLK_DDR_BUS_PLL1_DIV4 2
+#define CLK_DDR_BUS_PLL1_DIV8 3
+
+struct clk_jh7110_pllx {
+ struct clk clk;
+ void __iomem *base;
+ void __iomem *sysreg;
+ enum starfive_pll_type type;
+ const struct starfive_pllx_offset *offset;
+ const struct starfive_pllx_rate *rate_table;
+ int rate_count;
+};
+
+#define getbits_le32(addr, mask) ((in_le32(addr) & (mask)) >> __ffs((mask)))
+
+#define PLLX_SET(offset, mask, val) do {\
+ reg = readl((ulong *)((ulong)pll->base + (offset))); \
+ reg &= ~(mask); \
+ reg |= (mask) & ((val) << __ffs(mask)); \
+ writel(reg, (ulong *)((ulong)pll->base + (offset))); \
+ } while (0)
+
+#define PLLX_RATE(_rate, _pd, _fd) \
+ { \
+ .rate = (_rate), \
+ .prediv = (_pd), \
+ .fbdiv = (_fd), \
+ }
+
+#define to_clk_pllx(_clk) container_of(_clk, struct clk_jh7110_pllx, clk)
+
+static const struct starfive_pllx_rate jh7110_pll0_tbl[] = {
+ PLLX_RATE(375000000UL, 8, 125),
+ PLLX_RATE(500000000UL, 6, 125),
+ PLLX_RATE(625000000UL, 24, 625),
+ PLLX_RATE(750000000UL, 4, 125),
+ PLLX_RATE(875000000UL, 24, 875),
+ PLLX_RATE(1000000000UL, 3, 125),
+ PLLX_RATE(1250000000UL, 12, 625),
+ PLLX_RATE(1375000000UL, 24, 1375),
+ PLLX_RATE(1500000000UL, 2, 125),
+ PLLX_RATE(1625000000UL, 24, 1625),
+ PLLX_RATE(1750000000UL, 12, 875),
+ PLLX_RATE(1800000000UL, 3, 225),
+};
+
+static const struct starfive_pllx_rate jh7110_pll1_tbl[] = {
+ PLLX_RATE(1066000000UL, 12, 533),
+ PLLX_RATE(1200000000UL, 1, 50),
+ PLLX_RATE(1400000000UL, 6, 350),
+ PLLX_RATE(1600000000UL, 3, 200),
+};
+
+static const struct starfive_pllx_rate jh7110_pll2_tbl[] = {
+ PLLX_RATE(1228800000UL, 15, 768),
+ PLLX_RATE(1188000000UL, 2, 99),
+};
+
+static const struct starfive_pllx_offset jh7110_pll0_offset = {
+ .pd = 0x20,
+ .prediv = 0x24,
+ .fbdiv = 0x1c,
+ .frac = 0x20,
+ .postdiv1 = 0x20,
+ .dacpd = 0x18,
+ .dsmpd = 0x18,
+ .pd_mask = BIT(27),
+ .prediv_mask = GENMASK(5, 0),
+ .fbdiv_mask = GENMASK(11, 0),
+ .frac_mask = GENMASK(23, 0),
+ .postdiv1_mask = GENMASK(29, 28),
+ .dacpd_mask = BIT(24),
+ .dsmpd_mask = BIT(25)
+};
+
+static const struct starfive_pllx_offset jh7110_pll1_offset = {
+ .pd = 0x28,
+ .prediv = 0x2c,
+ .fbdiv = 0x24,
+ .frac = 0x28,
+ .postdiv1 = 0x28,
+ .dacpd = 0x24,
+ .dsmpd = 0x24,
+ .pd_mask = BIT(27),
+ .prediv_mask = GENMASK(5, 0),
+ .fbdiv_mask = GENMASK(28, 17),
+ .frac_mask = GENMASK(23, 0),
+ .postdiv1_mask = GENMASK(29, 28),
+ .dacpd_mask = BIT(15),
+ .dsmpd_mask = BIT(16)
+};
+
+static const struct starfive_pllx_offset jh7110_pll2_offset = {
+ .pd = 0x30,
+ .prediv = 0x34,
+ .fbdiv = 0x2c,
+ .frac = 0x30,
+ .postdiv1 = 0x30,
+ .dacpd = 0x2c,
+ .dsmpd = 0x2c,
+ .pd_mask = BIT(27),
+ .prediv_mask = GENMASK(5, 0),
+ .fbdiv_mask = GENMASK(28, 17),
+ .frac_mask = GENMASK(23, 0),
+ .postdiv1_mask = GENMASK(29, 28),
+ .dacpd_mask = BIT(15),
+ .dsmpd_mask = BIT(16)
+};
+
+struct starfive_pllx_clk starfive_jh7110_pll0 __initdata = {
+ .type = PLL0,
+ .offset = &jh7110_pll0_offset,
+ .rate_table = jh7110_pll0_tbl,
+ .rate_count = ARRAY_SIZE(jh7110_pll0_tbl),
+};
+
+struct starfive_pllx_clk starfive_jh7110_pll1 __initdata = {
+ .type = PLL1,
+ .offset = &jh7110_pll1_offset,
+ .rate_table = jh7110_pll1_tbl,
+ .rate_count = ARRAY_SIZE(jh7110_pll1_tbl),
+};
+
+struct starfive_pllx_clk starfive_jh7110_pll2 __initdata = {
+ .type = PLL2,
+ .offset = &jh7110_pll2_offset,
+ .rate_table = jh7110_pll2_tbl,
+ .rate_count = ARRAY_SIZE(jh7110_pll2_tbl),
+};
+
+static const struct starfive_pllx_rate *
+jh7110_get_pll_settings(struct clk_jh7110_pllx *pll, unsigned long rate)
+{
+ for (int i = 0; i < pll->rate_count; i++)
+ if (rate == pll->rate_table[i].rate)
+ return &pll->rate_table[i];
+
+ return NULL;
+}
+
+static void jh7110_pll_set_rate(struct clk_jh7110_pllx *pll,
+ const struct starfive_pllx_rate *rate)
+{
+ u32 reg;
+ bool set = (pll->type == PLL1) ? true : false;
+
+ if (set) {
+ reg = readl((ulong *)((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET));
+ reg &= ~CLK_DDR_BUS_MASK;
+ reg |= CLK_DDR_BUS_OSC_DIV2 << __ffs(CLK_DDR_BUS_MASK);
+ writel(reg, (ulong *)((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET));
+ }
+
+ PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_OFF);
+ PLLX_SET(pll->offset->dacpd, pll->offset->dacpd_mask, 1);
+ PLLX_SET(pll->offset->dsmpd, pll->offset->dsmpd_mask, 1);
+ PLLX_SET(pll->offset->prediv, pll->offset->prediv_mask, rate->prediv);
+ PLLX_SET(pll->offset->fbdiv, pll->offset->fbdiv_mask, rate->fbdiv);
+ PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1, 0);
+ PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_ON);
+
+ if (set) {
+ udelay(100);
+ reg = readl((ulong *)((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET));
+ reg &= ~CLK_DDR_BUS_MASK;
+ reg |= CLK_DDR_BUS_PLL1_DIV2 << __ffs(CLK_DDR_BUS_MASK);
+ writel(reg, (ulong *)((ulong)pll->sysreg + CLK_DDR_BUS_OFFSET));
+ }
+}
+
+static ulong jh7110_pllx_recalc_rate(struct clk *clk)
+{
+ struct clk_jh7110_pllx *pll = to_clk_pllx(dev_get_clk_ptr(clk->dev));
+ u64 refclk = clk_get_parent_rate(clk);
+ u32 dacpd, dsmpd;
+ u32 prediv, fbdiv, postdiv1;
+ u64 frac;
+
+ dacpd = getbits_le32((ulong)pll->base + pll->offset->dacpd,
+ pll->offset->dacpd_mask);
+ dsmpd = getbits_le32((ulong)pll->base + pll->offset->dsmpd,
+ pll->offset->dsmpd_mask);
+ prediv = getbits_le32((ulong)pll->base + pll->offset->prediv,
+ pll->offset->prediv_mask);
+ fbdiv = getbits_le32((ulong)pll->base + pll->offset->fbdiv,
+ pll->offset->fbdiv_mask);
+ postdiv1 = 1 << getbits_le32((ulong)pll->base + pll->offset->postdiv1,
+ pll->offset->postdiv1_mask);
+ frac = (u64)getbits_le32((ulong)pll->base + pll->offset->frac,
+ pll->offset->frac_mask);
+
+ /* Integer Multiple Mode
+ * Both dacpd and dsmpd should be set as 1 while integer multiple mode.
+ *
+ * The frequency of outputs can be figured out as below.
+ *
+ * Fvco = Fref*Nl/M
+ * NI is integer frequency dividing ratio of feedback divider, set by fbdiv1[11:0] ,
+ * NI = 8, 9, 10, 12.13....4095
+ * M is frequency dividing ratio of pre-divider, set by prediv[5:0],M = 1,2...63
+ *
+ * Fclko1 = Fvco/Q1
+ * Q1 is frequency dividing ratio of post divider, set by postdiv1[1:0],Q1= 1,2,4,8
+ *
+ * Fraction Multiple Mode
+ *
+ * Both dacpd and dsmpd should be set as 0 while integer multiple mode.
+ *
+ * Fvco = Fref*(NI+NF)/M
+ * NI is integer frequency dividing ratio of feedback divider, set by fbdiv[11:0] ,
+ * NI = 8, 9, 10, 12.13....4095
+ * NF is fractional frequency dividing ratio, set by frac[23:0], NF =frac[23:0]/2^24= 0~0.99999994
+ * M is frequency dividing ratio of pre-divider, set by prediv[5:0],M = 1,2...63
+ *
+ * Fclko1 = Fvco/Q1
+ * Q1 is frequency dividing ratio of post divider, set by postdivl[1:0],Q1= 1,2,4,8
+ */
+ if (dacpd == 1 && dsmpd == 1)
+ frac = 0;
+ else if (dacpd == 0 && dsmpd == 0)
+ do_div(frac, 1 << 24);
+ else
+ return -EINVAL;
+
+ refclk *= (fbdiv + frac);
+ do_div(refclk, prediv * postdiv1);
+
+ return refclk;
+}
+
+static ulong jh7110_pllx_set_rate(struct clk *clk, ulong drate)
+{
+ struct clk_jh7110_pllx *pll = to_clk_pllx(dev_get_clk_ptr(clk->dev));
+ const struct starfive_pllx_rate *rate;
+
+ rate = jh7110_get_pll_settings(pll, drate);
+ if (!rate)
+ return -EINVAL;
+
+ jh7110_pll_set_rate(pll, rate);
+
+ return jh7110_pllx_recalc_rate(clk);
+}
+
+static const struct clk_ops clk_jh7110_ops = {
+ .set_rate = jh7110_pllx_set_rate,
+ .get_rate = jh7110_pllx_recalc_rate,
+};
+
+struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
+ void __iomem *base, void __iomem *sysreg,
+ const struct starfive_pllx_clk *pll_clk)
+{
+ struct clk_jh7110_pllx *pll;
+ struct clk *clk;
+ int ret;
+
+ if (!pll_clk || !base || !sysreg)
+ return ERR_PTR(-EINVAL);
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->base = base;
+ pll->sysreg = sysreg;
+ pll->type = pll_clk->type;
+ pll->offset = pll_clk->offset;
+ pll->rate_table = pll_clk->rate_table;
+ pll->rate_count = pll_clk->rate_count;
+
+ clk = &pll->clk;
+ ret = clk_register(clk, UBOOT_DM_CLK_JH7110_PLLX, name, parent_name);
+ if (ret) {
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL0)
+ jh7110_pllx_set_rate(clk, 1000000000);
+
+ if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL2)
+ jh7110_pllx_set_rate(clk, 1188000000);
+
+ return clk;
+}
+
+U_BOOT_DRIVER(jh7110_clk_pllx) = {
+ .name = UBOOT_DM_CLK_JH7110_PLLX,
+ .id = UCLASS_CLK,
+ .ops = &clk_jh7110_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022-23 StarFive Technology Co., Ltd.
+ *
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <dm/devres.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+#include <log.h>
+#include <linux/clk-provider.h>
+
+#include "clk.h"
+
+#define STARFIVE_CLK_ENABLE_SHIFT 31 /* [31] */
+#define STARFIVE_CLK_INVERT_SHIFT 30 /* [30] */
+#define STARFIVE_CLK_MUX_SHIFT 24 /* [29:24] */
+#define STARFIVE_CLK_DIV_SHIFT 0 /* [23:0] */
+
+#define OFFSET(id) ((id) * 4)
+#define AONOFFSET(id) (((id) - JH7110_SYSCLK_END) * 4)
+#define STGOFFSET(id) (((id) - JH7110_AONCLK_END) * 4)
+
+typedef int (*jh1710_init_fn)(struct udevice *dev);
+
+struct jh7110_clk_priv {
+ void __iomem *reg;
+ jh1710_init_fn init;
+};
+
+static const char *cpu_root_sels[2] = {
+ [0] = "oscillator",
+ [1] = "pll0_out",
+};
+
+static const char *perh_root_sels[2] = {
+ [0] = "pll0_out",
+ [1] = "pll2_out",
+};
+
+static const char *bus_root_sels[2] = {
+ [0] = "oscillator",
+ [1] = "pll2_out",
+};
+
+static const char *qspi_ref_sels[2] = {
+ [0] = "oscillator",
+ [1] = "qspi_ref_src",
+};
+
+static const char *gmac1_tx_sels[2] = {
+ [0] = "gmac1_gtxclk",
+ [1] = "gmac1_rmii_rtx",
+};
+
+static const char *gmac0_tx_sels[2] = {
+ [0] = "gmac0_gtxclk",
+ [1] = "gmac0_rmii_rtx",
+};
+
+static const char *apb_func_sels[2] = {
+ [0] = "osc_div4",
+ [1] = "oscillator",
+};
+
+static const char *gmac1_rx_sels[2] = {
+ [0] = "gmac1-rgmii-rxin-clock",
+ [1] = "gmac1_rmii_rtx",
+};
+
+static struct clk *starfive_clk_mux(void __iomem *reg,
+ const char *name,
+ unsigned int offset,
+ u8 width,
+ const char * const *parent_names,
+ u8 num_parents)
+{
+ return clk_register_mux(NULL, name, parent_names, num_parents, 0,
+ reg + offset, STARFIVE_CLK_MUX_SHIFT,
+ width, 0);
+}
+
+static struct clk *starfive_clk_gate(void __iomem *reg,
+ const char *name,
+ const char *parent_name,
+ unsigned int offset)
+{
+ return clk_register_gate(NULL, name, parent_name, 0, reg + offset,
+ STARFIVE_CLK_ENABLE_SHIFT, 0, NULL);
+}
+
+static struct clk *starfive_clk_inv(void __iomem *reg,
+ const char *name,
+ const char *parent_name,
+ unsigned int offset)
+{
+ return clk_register_gate(NULL, name, parent_name, 0, reg + offset,
+ STARFIVE_CLK_INVERT_SHIFT, 0, NULL);
+}
+
+static struct clk *starfive_clk_divider(void __iomem *reg,
+ const char *name,
+ const char *parent_name,
+ unsigned int offset,
+ u8 width)
+{
+ return clk_register_divider(NULL, name, parent_name, 0, reg + offset,
+ 0, width, CLK_DIVIDER_ONE_BASED);
+}
+
+static struct clk *starfive_clk_composite(void __iomem *reg,
+ const char *name,
+ const char * const *parent_names,
+ unsigned int num_parents,
+ unsigned int offset,
+ unsigned int mux_width,
+ unsigned int gate_width,
+ unsigned int div_width)
+{
+ struct clk *clk = ERR_PTR(-ENOMEM);
+ struct clk_divider *div = NULL;
+ struct clk_gate *gate = NULL;
+ struct clk_mux *mux = NULL;
+ int mask_arry[4] = {0x1, 0x3, 0x7, 0xF};
+ int mask;
+
+ if (mux_width) {
+ if (mux_width > 4)
+ goto fail;
+ else
+ mask = mask_arry[mux_width - 1];
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ goto fail;
+
+ mux->reg = reg + offset;
+ mux->mask = mask;
+ mux->shift = STARFIVE_CLK_MUX_SHIFT;
+ mux->num_parents = num_parents;
+ mux->flags = 0;
+ mux->parent_names = parent_names;
+ }
+
+ if (gate_width) {
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+
+ if (!gate)
+ goto fail;
+
+ gate->reg = reg + offset;
+ gate->bit_idx = STARFIVE_CLK_ENABLE_SHIFT;
+ gate->flags = 0;
+ }
+
+ if (div_width) {
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ goto fail;
+
+ div->reg = reg + offset;
+
+ if (offset == OFFSET(JH7110_SYSCLK_UART3_CORE) ||
+ offset == OFFSET(JH7110_SYSCLK_UART4_CORE) ||
+ offset == OFFSET(JH7110_SYSCLK_UART5_CORE)) {
+ div->shift = 8;
+ div->width = 8;
+ } else {
+ div->shift = STARFIVE_CLK_DIV_SHIFT;
+ div->width = div_width;
+ }
+ div->flags = CLK_DIVIDER_ONE_BASED;
+ div->table = NULL;
+ }
+
+ clk = clk_register_composite(NULL, name,
+ parent_names, num_parents,
+ &mux->clk, &clk_mux_ops,
+ &div->clk, &clk_divider_ops,
+ &gate->clk, &clk_gate_ops, 0);
+
+ if (IS_ERR(clk))
+ goto fail;
+
+ return clk;
+
+fail:
+ kfree(gate);
+ kfree(div);
+ kfree(mux);
+ return ERR_CAST(clk);
+}
+
+static struct clk *starfive_clk_fix_parent_composite(void __iomem *reg,
+ const char *name,
+ const char *parent_names,
+ unsigned int offset,
+ unsigned int mux_width,
+ unsigned int gate_width,
+ unsigned int div_width)
+{
+ const char * const *parents;
+
+ parents = &parent_names;
+
+ return starfive_clk_composite(reg, name, parents, 1, offset,
+ mux_width, gate_width, div_width);
+}
+
+static struct clk *starfive_clk_gate_divider(void __iomem *reg,
+ const char *name,
+ const char *parent,
+ unsigned int offset,
+ unsigned int width)
+{
+ const char * const *parent_names;
+
+ parent_names = &parent;
+
+ return starfive_clk_composite(reg, name, parent_names, 1,
+ offset, 0, 1, width);
+}
+
+static int jh7110_syscrg_init(struct udevice *dev)
+{
+ struct jh7110_clk_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args args;
+ fdt_addr_t addr;
+ struct clk *pclk;
+ int ret;
+
+ ret = ofnode_parse_phandle_with_args(dev->node_, "starfive,sys-syscon", NULL, 0, 0, &args);
+ if (ret)
+ return ret;
+
+ addr = ofnode_get_addr(args.node);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ clk_dm(JH7110_SYSCLK_PLL0_OUT,
+ starfive_jh7110_pll("pll0_out", "oscillator", (void __iomem *)addr,
+ priv->reg, &starfive_jh7110_pll0));
+ clk_dm(JH7110_SYSCLK_PLL1_OUT,
+ starfive_jh7110_pll("pll1_out", "oscillator", (void __iomem *)addr,
+ priv->reg, &starfive_jh7110_pll1));
+ clk_dm(JH7110_SYSCLK_PLL2_OUT,
+ starfive_jh7110_pll("pll2_out", "oscillator", (void __iomem *)addr,
+ priv->reg, &starfive_jh7110_pll2));
+ clk_dm(JH7110_SYSCLK_CPU_ROOT,
+ starfive_clk_mux(priv->reg, "cpu_root",
+ OFFSET(JH7110_SYSCLK_CPU_ROOT), 1,
+ cpu_root_sels, ARRAY_SIZE(cpu_root_sels)));
+ clk_dm(JH7110_SYSCLK_CPU_CORE,
+ starfive_clk_divider(priv->reg,
+ "cpu_core", "cpu_root",
+ OFFSET(JH7110_SYSCLK_CPU_CORE), 3));
+ clk_dm(JH7110_SYSCLK_CPU_BUS,
+ starfive_clk_divider(priv->reg,
+ "cpu_bus", "cpu_core",
+ OFFSET(JH7110_SYSCLK_CPU_BUS), 2));
+ clk_dm(JH7110_SYSCLK_PERH_ROOT,
+ starfive_clk_composite(priv->reg,
+ "perh_root",
+ perh_root_sels, ARRAY_SIZE(perh_root_sels),
+ OFFSET(JH7110_SYSCLK_PERH_ROOT), 1, 0, 2));
+ clk_dm(JH7110_SYSCLK_BUS_ROOT,
+ starfive_clk_mux(priv->reg, "bus_root",
+ OFFSET(JH7110_SYSCLK_BUS_ROOT), 1,
+ bus_root_sels, ARRAY_SIZE(bus_root_sels)));
+ clk_dm(JH7110_SYSCLK_NOCSTG_BUS,
+ starfive_clk_divider(priv->reg,
+ "nocstg_bus", "bus_root",
+ OFFSET(JH7110_SYSCLK_NOCSTG_BUS), 3));
+ clk_dm(JH7110_SYSCLK_AXI_CFG0,
+ starfive_clk_divider(priv->reg,
+ "axi_cfg0", "bus_root",
+ OFFSET(JH7110_SYSCLK_AXI_CFG0), 2));
+ clk_dm(JH7110_SYSCLK_STG_AXIAHB,
+ starfive_clk_divider(priv->reg,
+ "stg_axiahb", "axi_cfg0",
+ OFFSET(JH7110_SYSCLK_STG_AXIAHB), 2));
+ clk_dm(JH7110_SYSCLK_AHB0,
+ starfive_clk_gate(priv->reg,
+ "ahb0", "stg_axiahb",
+ OFFSET(JH7110_SYSCLK_AHB0)));
+ clk_dm(JH7110_SYSCLK_AHB1,
+ starfive_clk_gate(priv->reg,
+ "ahb1", "stg_axiahb",
+ OFFSET(JH7110_SYSCLK_AHB1)));
+ clk_dm(JH7110_SYSCLK_APB_BUS,
+ starfive_clk_divider(priv->reg,
+ "apb_bus", "stg_axiahb",
+ OFFSET(JH7110_SYSCLK_APB_BUS), 4));
+ clk_dm(JH7110_SYSCLK_APB0,
+ starfive_clk_gate(priv->reg,
+ "apb0", "apb_bus",
+ OFFSET(JH7110_SYSCLK_APB0)));
+ clk_dm(JH7110_SYSCLK_QSPI_AHB,
+ starfive_clk_gate(priv->reg,
+ "qspi_ahb", "ahb1",
+ OFFSET(JH7110_SYSCLK_QSPI_AHB)));
+ clk_dm(JH7110_SYSCLK_QSPI_APB,
+ starfive_clk_gate(priv->reg,
+ "qspi_apb", "apb_bus",
+ OFFSET(JH7110_SYSCLK_QSPI_APB)));
+ clk_dm(JH7110_SYSCLK_QSPI_REF_SRC,
+ starfive_clk_divider(priv->reg,
+ "qspi_ref_src", "pll0_out",
+ OFFSET(JH7110_SYSCLK_QSPI_REF_SRC), 5));
+ clk_dm(JH7110_SYSCLK_QSPI_REF,
+ starfive_clk_composite(priv->reg,
+ "qspi_ref",
+ qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels),
+ OFFSET(JH7110_SYSCLK_QSPI_REF), 1, 1, 0));
+ clk_dm(JH7110_SYSCLK_SDIO0_AHB,
+ starfive_clk_gate(priv->reg,
+ "sdio0_ahb", "ahb0",
+ OFFSET(JH7110_SYSCLK_SDIO0_AHB)));
+ clk_dm(JH7110_SYSCLK_SDIO1_AHB,
+ starfive_clk_gate(priv->reg,
+ "sdio1_ahb", "ahb0",
+ OFFSET(JH7110_SYSCLK_SDIO1_AHB)));
+ clk_dm(JH7110_SYSCLK_SDIO0_SDCARD,
+ starfive_clk_fix_parent_composite(priv->reg,
+ "sdio0_sdcard", "axi_cfg0",
+ OFFSET(JH7110_SYSCLK_SDIO0_SDCARD), 0, 1, 4));
+ clk_dm(JH7110_SYSCLK_SDIO1_SDCARD,
+ starfive_clk_fix_parent_composite(priv->reg,
+ "sdio1_sdcard", "axi_cfg0",
+ OFFSET(JH7110_SYSCLK_SDIO1_SDCARD), 0, 1, 4));
+ clk_dm(JH7110_SYSCLK_USB_125M,
+ starfive_clk_divider(priv->reg,
+ "usb_125m", "pll0_out",
+ OFFSET(JH7110_SYSCLK_USB_125M), 4));
+ clk_dm(JH7110_SYSCLK_NOC_BUS_STG_AXI,
+ starfive_clk_gate(priv->reg,
+ "noc_bus_stg_axi", "nocstg_bus",
+ OFFSET(JH7110_SYSCLK_NOC_BUS_STG_AXI)));
+ clk_dm(JH7110_SYSCLK_GMAC1_AHB,
+ starfive_clk_gate(priv->reg,
+ "gmac1_ahb", "ahb0",
+ OFFSET(JH7110_SYSCLK_GMAC1_AHB)));
+ clk_dm(JH7110_SYSCLK_GMAC1_AXI,
+ starfive_clk_gate(priv->reg,
+ "gmac1_axi", "stg_axiahb",
+ OFFSET(JH7110_SYSCLK_GMAC1_AXI)));
+ clk_dm(JH7110_SYSCLK_GMAC_SRC,
+ starfive_clk_divider(priv->reg,
+ "gmac_src", "pll0_out",
+ OFFSET(JH7110_SYSCLK_GMAC_SRC), 3));
+ clk_dm(JH7110_SYSCLK_GMAC1_GTXCLK,
+ starfive_clk_divider(priv->reg,
+ "gmac1_gtxclk", "pll0_out",
+ OFFSET(JH7110_SYSCLK_GMAC1_GTXCLK), 4));
+ clk_dm(JH7110_SYSCLK_GMAC1_GTXC,
+ starfive_clk_gate(priv->reg,
+ "gmac1_gtxc", "gmac1_gtxclk",
+ OFFSET(JH7110_SYSCLK_GMAC1_GTXC)));
+ clk_dm(JH7110_SYSCLK_GMAC1_RMII_RTX,
+ starfive_clk_divider(priv->reg,
+ "gmac1_rmii_rtx", "gmac1-rmii-refin-clock",
+ OFFSET(JH7110_SYSCLK_GMAC1_RMII_RTX), 5));
+ clk_dm(JH7110_SYSCLK_GMAC1_PTP,
+ starfive_clk_gate_divider(priv->reg,
+ "gmac1_ptp", "gmac_src",
+ OFFSET(JH7110_SYSCLK_GMAC1_PTP), 5));
+ clk_dm(JH7110_SYSCLK_GMAC1_RX,
+ starfive_clk_mux(priv->reg, "gmac1_rx",
+ OFFSET(JH7110_SYSCLK_GMAC1_RX), 1,
+ gmac1_rx_sels, ARRAY_SIZE(gmac1_rx_sels)));
+ clk_dm(JH7110_SYSCLK_GMAC1_TX,
+ starfive_clk_composite(priv->reg,
+ "gmac1_tx",
+ gmac1_tx_sels, ARRAY_SIZE(gmac1_tx_sels),
+ OFFSET(JH7110_SYSCLK_GMAC1_TX), 1, 1, 0));
+ clk_dm(JH7110_SYSCLK_GMAC1_TX_INV,
+ starfive_clk_inv(priv->reg,
+ "gmac1_tx_inv", "gmac1_tx",
+ OFFSET(JH7110_SYSCLK_GMAC1_TX_INV)));
+ clk_dm(JH7110_SYSCLK_GMAC0_GTXCLK,
+ starfive_clk_gate_divider(priv->reg,
+ "gmac0_gtxclk", "pll0_out",
+ OFFSET(JH7110_SYSCLK_GMAC0_GTXCLK), 4));
+ clk_dm(JH7110_SYSCLK_GMAC0_PTP,
+ starfive_clk_gate_divider(priv->reg,
+ "gmac0_ptp", "gmac_src",
+ OFFSET(JH7110_SYSCLK_GMAC0_PTP), 5));
+ clk_dm(JH7110_SYSCLK_GMAC0_GTXC,
+ starfive_clk_gate(priv->reg,
+ "gmac0_gtxc", "gmac0_gtxclk",
+ OFFSET(JH7110_SYSCLK_GMAC0_GTXC)));
+ clk_dm(JH7110_SYSCLK_UART0_APB,
+ starfive_clk_gate(priv->reg,
+ "uart0_apb", "apb0",
+ OFFSET(JH7110_SYSCLK_UART0_APB)));
+ clk_dm(JH7110_SYSCLK_UART0_CORE,
+ starfive_clk_gate(priv->reg,
+ "uart0_core", "oscillator",
+ OFFSET(JH7110_SYSCLK_UART0_CORE)));
+ clk_dm(JH7110_SYSCLK_UART1_APB,
+ starfive_clk_gate(priv->reg,
+ "uart1_apb", "apb0",
+ OFFSET(JH7110_SYSCLK_UART1_APB)));
+ clk_dm(JH7110_SYSCLK_UART1_CORE,
+ starfive_clk_gate(priv->reg,
+ "uart1_core", "oscillator",
+ OFFSET(JH7110_SYSCLK_UART1_CORE)));
+ clk_dm(JH7110_SYSCLK_UART2_APB,
+ starfive_clk_gate(priv->reg,
+ "uart2_apb", "apb0",
+ OFFSET(JH7110_SYSCLK_UART2_APB)));
+ clk_dm(JH7110_SYSCLK_UART2_CORE,
+ starfive_clk_gate(priv->reg,
+ "uart2_core", "oscillator",
+ OFFSET(JH7110_SYSCLK_UART2_CORE)));
+ clk_dm(JH7110_SYSCLK_UART3_APB,
+ starfive_clk_gate(priv->reg,
+ "uart3_apb", "apb0",
+ OFFSET(JH7110_SYSCLK_UART3_APB)));
+ clk_dm(JH7110_SYSCLK_UART3_CORE,
+ starfive_clk_gate_divider(priv->reg,
+ "uart3_core", "perh_root",
+ OFFSET(JH7110_SYSCLK_UART3_CORE), 8));
+ clk_dm(JH7110_SYSCLK_UART4_APB,
+ starfive_clk_gate(priv->reg,
+ "uart4_apb", "apb0",
+ OFFSET(JH7110_SYSCLK_UART4_APB)));
+ clk_dm(JH7110_SYSCLK_UART4_CORE,
+ starfive_clk_gate_divider(priv->reg,
+ "uart4_core", "perh_root",
+ OFFSET(JH7110_SYSCLK_UART4_CORE), 8));
+ clk_dm(JH7110_SYSCLK_UART5_APB,
+ starfive_clk_gate(priv->reg,
+ "uart5_apb", "apb0",
+ OFFSET(JH7110_SYSCLK_UART5_APB)));
+ clk_dm(JH7110_SYSCLK_UART5_CORE,
+ starfive_clk_gate_divider(priv->reg,
+ "uart5_core", "perh_root",
+ OFFSET(JH7110_SYSCLK_UART5_CORE), 8));
+ clk_dm(JH7110_SYSCLK_I2C2_APB,
+ starfive_clk_gate(priv->reg,
+ "i2c2_apb", "apb0",
+ OFFSET(JH7110_SYSCLK_I2C2_APB)));
+ clk_dm(JH7110_SYSCLK_I2C5_APB,
+ starfive_clk_gate(priv->reg,
+ "i2c5_apb", "apb0",
+ OFFSET(JH7110_SYSCLK_I2C5_APB)));
+
+ /* enable noc_bus_stg_axi clock */
+ if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk))
+ clk_enable(pclk);
+
+ return 0;
+}
+
+static int jh7110_aoncrg_init(struct udevice *dev)
+{
+ struct jh7110_clk_priv *priv = dev_get_priv(dev);
+
+ clk_dm(JH7110_AONCLK_OSC_DIV4,
+ starfive_clk_divider(priv->reg,
+ "osc_div4", "oscillator",
+ AONOFFSET(JH7110_AONCLK_OSC_DIV4), 5));
+ clk_dm(JH7110_AONCLK_APB_FUNC,
+ starfive_clk_mux(priv->reg, "apb_func",
+ AONOFFSET(JH7110_AONCLK_APB_FUNC), 1,
+ apb_func_sels, ARRAY_SIZE(apb_func_sels)));
+ clk_dm(JH7110_AONCLK_GMAC0_AHB,
+ starfive_clk_gate(priv->reg,
+ "gmac0_ahb", "stg_axiahb",
+ AONOFFSET(JH7110_AONCLK_GMAC0_AHB)));
+ clk_dm(JH7110_AONCLK_GMAC0_AXI,
+ starfive_clk_gate(priv->reg,
+ "gmac0_axi", "stg_axiahb",
+ AONOFFSET(JH7110_AONCLK_GMAC0_AXI)));
+ clk_dm(JH7110_AONCLK_GMAC0_RMII_RTX,
+ starfive_clk_divider(priv->reg,
+ "gmac0_rmii_rtx", "gmac0-rmii-refin-clock",
+ AONOFFSET(JH7110_AONCLK_GMAC0_RMII_RTX), 5));
+ clk_dm(JH7110_AONCLK_GMAC0_TX,
+ starfive_clk_composite(priv->reg,
+ "gmac0_tx", gmac0_tx_sels,
+ ARRAY_SIZE(gmac0_tx_sels),
+ AONOFFSET(JH7110_AONCLK_GMAC0_TX), 1, 1, 0));
+ clk_dm(JH7110_AONCLK_GMAC0_TX_INV,
+ starfive_clk_inv(priv->reg,
+ "gmac0_tx_inv", "gmac0_tx",
+ AONOFFSET(JH7110_AONCLK_GMAC0_TX_INV)));
+ clk_dm(JH7110_AONCLK_OTPC_APB,
+ starfive_clk_gate(priv->reg,
+ "otpc_apb", "apb_bus",
+ AONOFFSET(JH7110_AONCLK_OTPC_APB)));
+
+ return 0;
+}
+
+static int jh7110_stgcrg_init(struct udevice *dev)
+{
+ struct jh7110_clk_priv *priv = dev_get_priv(dev);
+
+ clk_dm(JH7110_STGCLK_USB_APB,
+ starfive_clk_gate(priv->reg,
+ "usb_apb", "apb_bus",
+ STGOFFSET(JH7110_STGCLK_USB_APB)));
+ clk_dm(JH7110_STGCLK_USB_UTMI_APB,
+ starfive_clk_gate(priv->reg,
+ "usb_utmi_apb", "apb_bus",
+ STGOFFSET(JH7110_STGCLK_USB_UTMI_APB)));
+ clk_dm(JH7110_STGCLK_USB_AXI,
+ starfive_clk_gate(priv->reg,
+ "usb_axi", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_USB_AXI)));
+ clk_dm(JH7110_STGCLK_USB_LPM,
+ starfive_clk_gate_divider(priv->reg,
+ "usb_lpm", "oscillator",
+ STGOFFSET(JH7110_STGCLK_USB_LPM), 2));
+ clk_dm(JH7110_STGCLK_USB_STB,
+ starfive_clk_gate_divider(priv->reg,
+ "usb_stb", "oscillator",
+ STGOFFSET(JH7110_STGCLK_USB_STB), 3));
+ clk_dm(JH7110_STGCLK_USB_APP_125,
+ starfive_clk_gate(priv->reg,
+ "usb_app_125", "usb_125m",
+ STGOFFSET(JH7110_STGCLK_USB_APP_125)));
+ clk_dm(JH7110_STGCLK_USB_REFCLK,
+ starfive_clk_divider(priv->reg, "usb_refclk", "oscillator",
+ STGOFFSET(JH7110_STGCLK_USB_REFCLK), 2));
+ clk_dm(JH7110_STGCLK_PCIE0_AXI,
+ starfive_clk_gate(priv->reg,
+ "pcie0_axi", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE0_AXI)));
+ clk_dm(JH7110_STGCLK_PCIE0_APB,
+ starfive_clk_gate(priv->reg,
+ "pcie0_apb", "apb_bus",
+ STGOFFSET(JH7110_STGCLK_PCIE0_APB)));
+ clk_dm(JH7110_STGCLK_PCIE0_TL,
+ starfive_clk_gate(priv->reg,
+ "pcie0_tl", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE0_TL)));
+ clk_dm(JH7110_STGCLK_PCIE1_AXI,
+ starfive_clk_gate(priv->reg,
+ "pcie1_axi", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE1_AXI)));
+ clk_dm(JH7110_STGCLK_PCIE1_APB,
+ starfive_clk_gate(priv->reg,
+ "pcie1_apb", "apb_bus",
+ STGOFFSET(JH7110_STGCLK_PCIE1_APB)));
+ clk_dm(JH7110_STGCLK_PCIE1_TL,
+ starfive_clk_gate(priv->reg,
+ "pcie1_tl", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE1_TL)));
+
+ return 0;
+}
+
+static int jh7110_clk_probe(struct udevice *dev)
+{
+ struct jh7110_clk_priv *priv = dev_get_priv(dev);
+
+ priv->init = (jh1710_init_fn)dev_get_driver_data(dev);
+ priv->reg = (void __iomem *)dev_read_addr_ptr(dev);
+
+ if (priv->init)
+ return priv->init(dev);
+
+ return 0;
+}
+
+static int jh7110_clk_bind(struct udevice *dev)
+{
+ /* The reset driver does not have a device node, so bind it here */
+ return device_bind_driver_to_node(dev, "jh7110_reset", dev->name,
+ dev_ofnode(dev), NULL);
+}
+
+static const struct udevice_id jh7110_clk_of_match[] = {
+ { .compatible = "starfive,jh7110-syscrg",
+ .data = (ulong)&jh7110_syscrg_init
+ },
+ { .compatible = "starfive,jh7110-stgcrg",
+ .data = (ulong)&jh7110_stgcrg_init
+ },
+ { .compatible = "starfive,jh7110-aoncrg",
+ .data = (ulong)&jh7110_aoncrg_init
+ },
+ { }
+};
+
+U_BOOT_DRIVER(jh7110_clk) = {
+ .name = "jh7110_clk",
+ .id = UCLASS_CLK,
+ .of_match = jh7110_clk_of_match,
+ .probe = jh7110_clk_probe,
+ .ops = &ccf_clk_ops,
+ .priv_auto = sizeof(struct jh7110_clk_priv),
+ .bind = jh7110_clk_bind,
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Starfive, Inc.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ *
+ */
+
+#ifndef __CLK_STARFIVE_H
+#define __CLK_STARFIVE_H
+
+enum starfive_pll_type {
+ PLL0 = 0,
+ PLL1,
+ PLL2,
+ PLL_MAX = PLL2
+};
+
+struct starfive_pllx_rate {
+ u64 rate;
+ u32 prediv;
+ u32 fbdiv;
+ u32 frac;
+};
+
+struct starfive_pllx_offset {
+ u32 pd;
+ u32 prediv;
+ u32 fbdiv;
+ u32 frac;
+ u32 postdiv1;
+ u32 dacpd;
+ u32 dsmpd;
+ u32 pd_mask;
+ u32 prediv_mask;
+ u32 fbdiv_mask;
+ u32 frac_mask;
+ u32 postdiv1_mask;
+ u32 dacpd_mask;
+ u32 dsmpd_mask;
+};
+
+struct starfive_pllx_clk {
+ enum starfive_pll_type type;
+ const struct starfive_pllx_offset *offset;
+ const struct starfive_pllx_rate *rate_table;
+ int rate_count;
+ int flags;
+};
+
+extern struct starfive_pllx_clk starfive_jh7110_pll0;
+extern struct starfive_pllx_clk starfive_jh7110_pll1;
+extern struct starfive_pllx_clk starfive_jh7110_pll2;
+
+struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
+ void __iomem *base, void __iomem *sysreg,
+ const struct starfive_pllx_clk *pll_clk);
+#endif
}
str = ofnode_read_string(node, "nand-ecc-algo");
- if (str && !strcmp(str, "bch")) {
- ecc_algo = NAND_ECC_BCH;
- if (ecc_mode == NAND_ECC_SOFT)
- ecc_mode = NAND_ECC_SOFT_BCH;
- } else if (!strcmp(str, "hamming")) {
- ecc_algo = NAND_ECC_HAMMING;
+ if (str) {
+ /*
+ * If we are in NAND_ECC_SOFT mode, just alter the
+ * soft mode to BCH here. No change of algorithm.
+ */
+ if (ecc_mode == NAND_ECC_SOFT) {
+ if (!strcmp(str, "bch"))
+ ecc_mode = NAND_ECC_SOFT_BCH;
+ } else {
+ if (!strcmp(str, "bch")) {
+ ecc_algo = NAND_ECC_BCH;
+ } else if (!strcmp(str, "hamming")) {
+ ecc_algo = NAND_ECC_HAMMING;
+ }
+ }
}
ecc_strength = ofnode_read_s32_default(node,
return -EINVAL;
}
- chip->ecc.algo = ecc_algo;
+ /*
+ * Chip drivers may have assigned default algorithms here,
+ * onlt override it if we have found something explicitly
+ * specified in the device tree.
+ */
+ if (ecc_algo != NAND_ECC_UNKNOWN)
+ chip->ecc.algo = ecc_algo;
if (ecc_mode >= 0)
chip->ecc.mode = ecc_mode;
if (IS_ERR(sdrt))
return PTR_ERR(sdrt);
+ if (sdrt->tRC_min < 30000)
+ return -EOPNOTSUPP;
+
if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
return 0;
source "drivers/pinctrl/rockchip/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
+source "drivers/pinctrl/starfive/Kconfig"
endmenu
obj-$(CONFIG_$(SPL_)PINCTRL_STMFX) += pinctrl-stmfx.o
obj-y += broadcom/
obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
+obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/
[STM32_GPIO_OTYPE_OD] = "open-drain",
};
+static const char * const pinmux_speed[] = {
+ [STM32_GPIO_SPEED_2M] = "Low speed",
+ [STM32_GPIO_SPEED_25M] = "Medium speed",
+ [STM32_GPIO_SPEED_50M] = "High speed",
+ [STM32_GPIO_SPEED_100M] = "Very-high speed",
+};
+
static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
int af_num;
unsigned int gpio_idx;
u32 pupd, otype;
+ u8 speed;
/* look up for the bank which owns the requested pin */
gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
priv = dev_get_priv(gpio_dev);
pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
+ speed = (readl(&priv->regs->ospeedr) >> gpio_idx * 2) & OSPEED_MASK;
switch (mode) {
case GPIOF_UNKNOWN:
break;
case GPIOF_FUNC:
af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
- snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num,
- pinmux_otype[otype], pinmux_bias[pupd]);
+ snprintf(buf, size, "%s %d %s %s %s", pinmux_mode[mode], af_num,
+ pinmux_otype[otype], pinmux_bias[pupd],
+ pinmux_speed[speed]);
break;
case GPIOF_OUTPUT:
- snprintf(buf, size, "%s %s %s %s",
+ snprintf(buf, size, "%s %s %s %s %s",
pinmux_mode[mode], pinmux_otype[otype],
- pinmux_bias[pupd], label ? label : "");
+ pinmux_bias[pupd], label ? label : "",
+ pinmux_speed[speed]);
break;
case GPIOF_INPUT:
snprintf(buf, size, "%s %s %s", pinmux_mode[mode],
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only
+
+config SPL_PINCTRL_STARFIVE
+ bool "Support Pinctrl driver for StarFive SoC in SPL"
+ depends on SPL_PINCTRL_FULL && STARFIVE_JH7110
+ help
+ Enable support pin control driver for StarFive SoC.
+
+config SPL_PINCTRL_STARFIVE_JH7110
+ bool "Support Pinctrl and GPIO driver for StarFive JH7110 SoC in SPL"
+ depends on SPL_PINCTRL_STARFIVE
+ help
+ Enable support pinctrl and gpio driver for StarFive JH7110 in SPL.
+
+config PINCTRL_STARFIVE
+ bool "Pinctrl driver for StarFive SoC"
+ depends on PINCTRL_FULL && STARFIVE_JH7110
+ help
+ Say yes here to support pin control on the StarFive RISC-V SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JH7110
+ bool "Pinctrl and GPIO driver for StarFive JH7110 SoC"
+ depends on PINCTRL_STARFIVE
+ help
+ This selects the pinctrl driver for JH7110 starfive.
--- /dev/null
+
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_$(SPL_TPL_)PINCTRL_STARFIVE) += pinctrl-starfive.o
+# SoC Drivers
+obj-$(CONFIG_$(SPL_TPL_)PINCTRL_STARFIVE_JH7110) += pinctrl-jh7110-sys.o pinctrl-jh7110-aon.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ * Author: Jianlong Huang <jianlong.huang@starfivetech.com>
+ */
+
+#include <dm/read.h>
+#include <dm/device_compat.h>
+#include <linux/io.h>
+
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+#include "pinctrl-starfive.h"
+
+#define JH7110_AON_NGPIO 4
+#define JH7110_AON_GC_BASE 64
+
+/* registers */
+#define JH7110_AON_DOEN 0x0
+#define JH7110_AON_DOUT 0x4
+#define JH7110_AON_GPI 0x8
+#define JH7110_AON_GPIOIN 0x2c
+
+#define JH7110_AON_GPIOEN 0xc
+#define JH7110_AON_GPIOIS 0x10
+#define JH7110_AON_GPIOIC 0x14
+#define JH7110_AON_GPIOIBE 0x18
+#define JH7110_AON_GPIOIEV 0x1c
+#define JH7110_AON_GPIOIE 0x20
+#define JH7110_AON_GPIORIS 0x28
+#define JH7110_AON_GPIOMIS 0x28
+
+#define AON_GPO_PDA_0_5_CFG 0x30
+
+static int jh7110_aon_set_one_pin_mux(struct udevice *dev, unsigned int pin,
+ unsigned int din, u32 dout,
+ u32 doen, u32 func)
+{
+ struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+
+ if (pin < priv->info->ngpios && func == 0)
+ starfive_set_gpiomux(dev, pin, din, dout, doen);
+
+ return 0;
+}
+
+static int jh7110_aon_get_padcfg_base(struct udevice *dev,
+ unsigned int pin)
+{
+ if (pin < PAD_GMAC0_MDC)
+ return AON_GPO_PDA_0_5_CFG;
+
+ return -1;
+}
+
+static void jh7110_aon_init_hw(struct udevice *dev)
+{
+ struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+
+ /* mask all GPIO interrupts */
+ writel(0, priv->base + JH7110_AON_GPIOIE);
+ /* clear edge interrupt flags */
+ writel(0, priv->base + JH7110_AON_GPIOIC);
+ writel(0x0f, priv->base + JH7110_AON_GPIOIC);
+ /* enable GPIO interrupts */
+ writel(1, priv->base + JH7110_AON_GPIOEN);
+}
+
+const struct starfive_pinctrl_soc_info jh7110_aon_pinctrl_info = {
+ /* pin conf */
+ .set_one_pinmux = jh7110_aon_set_one_pin_mux,
+ .get_padcfg_base = jh7110_aon_get_padcfg_base,
+
+ /* gpio dout/doen/din/gpioinput register */
+ .dout_reg_base = JH7110_AON_DOUT,
+ .dout_mask = GENMASK(3, 0),
+ .doen_reg_base = JH7110_AON_DOEN,
+ .doen_mask = GENMASK(2, 0),
+ .gpi_reg_base = JH7110_AON_GPI,
+ .gpi_mask = GENMASK(3, 0),
+ .gpioin_reg_base = JH7110_AON_GPIOIN,
+
+ /* gpio */
+ .gpio_bank_name = "RGPIO",
+ .ngpios = JH7110_AON_NGPIO,
+ .gpio_init_hw = jh7110_aon_init_hw,
+};
+
+static int jh7110_aon_pinctrl_probe(struct udevice *dev)
+{
+ struct starfive_pinctrl_soc_info *info =
+ (struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+ return starfive_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id jh7110_aon_pinctrl_ids[] = {
+ /* JH7110 aon pinctrl */
+ { .compatible = "starfive,jh7110-aon-pinctrl",
+ .data = (ulong)&jh7110_aon_pinctrl_info, },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(jh7110_aon_pinctrl) = {
+ .name = "jh7110-aon-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = jh7110_aon_pinctrl_ids,
+ .priv_auto = sizeof(struct starfive_pinctrl_priv),
+ .ops = &starfive_pinctrl_ops,
+ .probe = jh7110_aon_pinctrl_probe,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ * Author: Jianlong Huang <jianlong.huang@starfivetech.com>
+ */
+
+#include <dm/read.h>
+#include <dm/device_compat.h>
+#include <linux/io.h>
+
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+#include "pinctrl-starfive.h"
+
+#define JH7110_SYS_NGPIO 64
+#define JH7110_SYS_GC_BASE 0
+
+/* registers */
+#define JH7110_SYS_DOEN 0x000
+#define JH7110_SYS_DOUT 0x040
+#define JH7110_SYS_GPI 0x080
+#define JH7110_SYS_GPIOIN 0x118
+
+#define JH7110_SYS_GPIOEN 0x0dc
+#define JH7110_SYS_GPIOIS0 0x0e0
+#define JH7110_SYS_GPIOIS1 0x0e4
+#define JH7110_SYS_GPIOIC0 0x0e8
+#define JH7110_SYS_GPIOIC1 0x0ec
+#define JH7110_SYS_GPIOIBE0 0x0f0
+#define JH7110_SYS_GPIOIBE1 0x0f4
+#define JH7110_SYS_GPIOIEV0 0x0f8
+#define JH7110_SYS_GPIOIEV1 0x0fc
+#define JH7110_SYS_GPIOIE0 0x100
+#define JH7110_SYS_GPIOIE1 0x104
+#define JH7110_SYS_GPIORIS0 0x108
+#define JH7110_SYS_GPIORIS1 0x10c
+#define JH7110_SYS_GPIOMIS0 0x110
+#define JH7110_SYS_GPIOMIS1 0x114
+
+#define SYS_GPO_PDA_0_74_CFG 0x120
+#define SYS_GPO_PDA_89_94_CFG 0x284
+
+static const struct starfive_pinctrl_pin jh7110_sys_pins[] = {
+ STARFIVE_PINCTRL(PAD_GPIO0, "GPIO0"),
+ STARFIVE_PINCTRL(PAD_GPIO1, "GPIO1"),
+ STARFIVE_PINCTRL(PAD_GPIO2, "GPIO2"),
+ STARFIVE_PINCTRL(PAD_GPIO3, "GPIO3"),
+ STARFIVE_PINCTRL(PAD_GPIO4, "GPIO4"),
+ STARFIVE_PINCTRL(PAD_GPIO5, "GPIO5"),
+ STARFIVE_PINCTRL(PAD_GPIO6, "GPIO6"),
+ STARFIVE_PINCTRL(PAD_GPIO7, "GPIO7"),
+ STARFIVE_PINCTRL(PAD_GPIO8, "GPIO8"),
+ STARFIVE_PINCTRL(PAD_GPIO9, "GPIO9"),
+ STARFIVE_PINCTRL(PAD_GPIO10, "GPIO10"),
+ STARFIVE_PINCTRL(PAD_GPIO11, "GPIO11"),
+ STARFIVE_PINCTRL(PAD_GPIO12, "GPIO12"),
+ STARFIVE_PINCTRL(PAD_GPIO13, "GPIO13"),
+ STARFIVE_PINCTRL(PAD_GPIO14, "GPIO14"),
+ STARFIVE_PINCTRL(PAD_GPIO15, "GPIO15"),
+ STARFIVE_PINCTRL(PAD_GPIO16, "GPIO16"),
+ STARFIVE_PINCTRL(PAD_GPIO17, "GPIO17"),
+ STARFIVE_PINCTRL(PAD_GPIO18, "GPIO18"),
+ STARFIVE_PINCTRL(PAD_GPIO19, "GPIO19"),
+ STARFIVE_PINCTRL(PAD_GPIO20, "GPIO20"),
+ STARFIVE_PINCTRL(PAD_GPIO21, "GPIO21"),
+ STARFIVE_PINCTRL(PAD_GPIO22, "GPIO22"),
+ STARFIVE_PINCTRL(PAD_GPIO23, "GPIO23"),
+ STARFIVE_PINCTRL(PAD_GPIO24, "GPIO24"),
+ STARFIVE_PINCTRL(PAD_GPIO25, "GPIO25"),
+ STARFIVE_PINCTRL(PAD_GPIO26, "GPIO26"),
+ STARFIVE_PINCTRL(PAD_GPIO27, "GPIO27"),
+ STARFIVE_PINCTRL(PAD_GPIO28, "GPIO28"),
+ STARFIVE_PINCTRL(PAD_GPIO29, "GPIO29"),
+ STARFIVE_PINCTRL(PAD_GPIO30, "GPIO30"),
+ STARFIVE_PINCTRL(PAD_GPIO31, "GPIO31"),
+ STARFIVE_PINCTRL(PAD_GPIO32, "GPIO32"),
+ STARFIVE_PINCTRL(PAD_GPIO33, "GPIO33"),
+ STARFIVE_PINCTRL(PAD_GPIO34, "GPIO34"),
+ STARFIVE_PINCTRL(PAD_GPIO35, "GPIO35"),
+ STARFIVE_PINCTRL(PAD_GPIO36, "GPIO36"),
+ STARFIVE_PINCTRL(PAD_GPIO37, "GPIO37"),
+ STARFIVE_PINCTRL(PAD_GPIO38, "GPIO38"),
+ STARFIVE_PINCTRL(PAD_GPIO39, "GPIO39"),
+ STARFIVE_PINCTRL(PAD_GPIO40, "GPIO40"),
+ STARFIVE_PINCTRL(PAD_GPIO41, "GPIO41"),
+ STARFIVE_PINCTRL(PAD_GPIO42, "GPIO42"),
+ STARFIVE_PINCTRL(PAD_GPIO43, "GPIO43"),
+ STARFIVE_PINCTRL(PAD_GPIO44, "GPIO44"),
+ STARFIVE_PINCTRL(PAD_GPIO45, "GPIO45"),
+ STARFIVE_PINCTRL(PAD_GPIO46, "GPIO46"),
+ STARFIVE_PINCTRL(PAD_GPIO47, "GPIO47"),
+ STARFIVE_PINCTRL(PAD_GPIO48, "GPIO48"),
+ STARFIVE_PINCTRL(PAD_GPIO49, "GPIO49"),
+ STARFIVE_PINCTRL(PAD_GPIO50, "GPIO50"),
+ STARFIVE_PINCTRL(PAD_GPIO51, "GPIO51"),
+ STARFIVE_PINCTRL(PAD_GPIO52, "GPIO52"),
+ STARFIVE_PINCTRL(PAD_GPIO53, "GPIO53"),
+ STARFIVE_PINCTRL(PAD_GPIO54, "GPIO54"),
+ STARFIVE_PINCTRL(PAD_GPIO55, "GPIO55"),
+ STARFIVE_PINCTRL(PAD_GPIO56, "GPIO56"),
+ STARFIVE_PINCTRL(PAD_GPIO57, "GPIO57"),
+ STARFIVE_PINCTRL(PAD_GPIO58, "GPIO58"),
+ STARFIVE_PINCTRL(PAD_GPIO59, "GPIO59"),
+ STARFIVE_PINCTRL(PAD_GPIO60, "GPIO60"),
+ STARFIVE_PINCTRL(PAD_GPIO61, "GPIO61"),
+ STARFIVE_PINCTRL(PAD_GPIO62, "GPIO62"),
+ STARFIVE_PINCTRL(PAD_GPIO63, "GPIO63"),
+ STARFIVE_PINCTRL(PAD_SD0_CLK, "SD0_CLK"),
+ STARFIVE_PINCTRL(PAD_SD0_CMD, "SD0_CMD"),
+ STARFIVE_PINCTRL(PAD_SD0_DATA0, "SD0_DATA0"),
+ STARFIVE_PINCTRL(PAD_SD0_DATA1, "SD0_DATA1"),
+ STARFIVE_PINCTRL(PAD_SD0_DATA2, "SD0_DATA2"),
+ STARFIVE_PINCTRL(PAD_SD0_DATA3, "SD0_DATA3"),
+ STARFIVE_PINCTRL(PAD_SD0_DATA4, "SD0_DATA4"),
+ STARFIVE_PINCTRL(PAD_SD0_DATA5, "SD0_DATA5"),
+ STARFIVE_PINCTRL(PAD_SD0_DATA6, "SD0_DATA6"),
+ STARFIVE_PINCTRL(PAD_SD0_DATA7, "SD0_DATA7"),
+ STARFIVE_PINCTRL(PAD_SD0_STRB, "SD0_STRB"),
+ STARFIVE_PINCTRL(PAD_GMAC1_MDC, "GMAC1_MDC"),
+ STARFIVE_PINCTRL(PAD_GMAC1_MDIO, "GMAC1_MDIO"),
+ STARFIVE_PINCTRL(PAD_GMAC1_RXD0, "GMAC1_RXD0"),
+ STARFIVE_PINCTRL(PAD_GMAC1_RXD1, "GMAC1_RXD1"),
+ STARFIVE_PINCTRL(PAD_GMAC1_RXD2, "GMAC1_RXD2"),
+ STARFIVE_PINCTRL(PAD_GMAC1_RXD3, "GMAC1_RXD3"),
+ STARFIVE_PINCTRL(PAD_GMAC1_RXDV, "GMAC1_RXDV"),
+ STARFIVE_PINCTRL(PAD_GMAC1_RXC, "GMAC1_RXC"),
+ STARFIVE_PINCTRL(PAD_GMAC1_TXD0, "GMAC1_TXD0"),
+ STARFIVE_PINCTRL(PAD_GMAC1_TXD1, "GMAC1_TXD1"),
+ STARFIVE_PINCTRL(PAD_GMAC1_TXD2, "GMAC1_TXD2"),
+ STARFIVE_PINCTRL(PAD_GMAC1_TXD3, "GMAC1_TXD3"),
+ STARFIVE_PINCTRL(PAD_GMAC1_TXEN, "GMAC1_TXEN"),
+ STARFIVE_PINCTRL(PAD_GMAC1_TXC, "GMAC1_TXC"),
+ STARFIVE_PINCTRL(PAD_QSPI_SCLK, "QSPI_SCLK"),
+ STARFIVE_PINCTRL(PAD_QSPI_CS0, "QSPI_CS0"),
+ STARFIVE_PINCTRL(PAD_QSPI_DATA0, "QSPI_DATA0"),
+ STARFIVE_PINCTRL(PAD_QSPI_DATA1, "QSPI_DATA1"),
+ STARFIVE_PINCTRL(PAD_QSPI_DATA2, "QSPI_DATA2"),
+ STARFIVE_PINCTRL(PAD_QSPI_DATA3, "QSPI_DATA3"),
+};
+
+struct jh7110_func_sel {
+ u16 offset;
+ u8 shift;
+ u8 max;
+};
+
+static const struct jh7110_func_sel
+ jh7110_sys_func_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
+ [PAD_GMAC1_RXC] = { 0x29c, 0, 1 },
+ [PAD_GPIO10] = { 0x29c, 2, 3 },
+ [PAD_GPIO11] = { 0x29c, 5, 3 },
+ [PAD_GPIO12] = { 0x29c, 8, 3 },
+ [PAD_GPIO13] = { 0x29c, 11, 3 },
+ [PAD_GPIO14] = { 0x29c, 14, 3 },
+ [PAD_GPIO15] = { 0x29c, 17, 3 },
+ [PAD_GPIO16] = { 0x29c, 20, 3 },
+ [PAD_GPIO17] = { 0x29c, 23, 3 },
+ [PAD_GPIO18] = { 0x29c, 26, 3 },
+ [PAD_GPIO19] = { 0x29c, 29, 3 },
+
+ [PAD_GPIO20] = { 0x2a0, 0, 3 },
+ [PAD_GPIO21] = { 0x2a0, 3, 3 },
+ [PAD_GPIO22] = { 0x2a0, 6, 3 },
+ [PAD_GPIO23] = { 0x2a0, 9, 3 },
+ [PAD_GPIO24] = { 0x2a0, 12, 3 },
+ [PAD_GPIO25] = { 0x2a0, 15, 3 },
+ [PAD_GPIO26] = { 0x2a0, 18, 3 },
+ [PAD_GPIO27] = { 0x2a0, 21, 3 },
+ [PAD_GPIO28] = { 0x2a0, 24, 3 },
+ [PAD_GPIO29] = { 0x2a0, 27, 3 },
+
+ [PAD_GPIO30] = { 0x2a4, 0, 3 },
+ [PAD_GPIO31] = { 0x2a4, 3, 3 },
+ [PAD_GPIO32] = { 0x2a4, 6, 3 },
+ [PAD_GPIO33] = { 0x2a4, 9, 3 },
+ [PAD_GPIO34] = { 0x2a4, 12, 3 },
+ [PAD_GPIO35] = { 0x2a4, 15, 3 },
+ [PAD_GPIO36] = { 0x2a4, 17, 3 },
+ [PAD_GPIO37] = { 0x2a4, 20, 3 },
+ [PAD_GPIO38] = { 0x2a4, 23, 3 },
+ [PAD_GPIO39] = { 0x2a4, 26, 3 },
+ [PAD_GPIO40] = { 0x2a4, 29, 3 },
+
+ [PAD_GPIO41] = { 0x2a8, 0, 3 },
+ [PAD_GPIO42] = { 0x2a8, 3, 3 },
+ [PAD_GPIO43] = { 0x2a8, 6, 3 },
+ [PAD_GPIO44] = { 0x2a8, 9, 3 },
+ [PAD_GPIO45] = { 0x2a8, 12, 3 },
+ [PAD_GPIO46] = { 0x2a8, 15, 3 },
+ [PAD_GPIO47] = { 0x2a8, 18, 3 },
+ [PAD_GPIO48] = { 0x2a8, 21, 3 },
+ [PAD_GPIO49] = { 0x2a8, 24, 3 },
+ [PAD_GPIO50] = { 0x2a8, 27, 3 },
+ [PAD_GPIO51] = { 0x2a8, 30, 3 },
+
+ [PAD_GPIO52] = { 0x2ac, 0, 3 },
+ [PAD_GPIO53] = { 0x2ac, 2, 3 },
+ [PAD_GPIO54] = { 0x2ac, 4, 3 },
+ [PAD_GPIO55] = { 0x2ac, 6, 3 },
+ [PAD_GPIO56] = { 0x2ac, 9, 3 },
+ [PAD_GPIO57] = { 0x2ac, 12, 3 },
+ [PAD_GPIO58] = { 0x2ac, 15, 3 },
+ [PAD_GPIO59] = { 0x2ac, 18, 3 },
+ [PAD_GPIO60] = { 0x2ac, 21, 3 },
+ [PAD_GPIO61] = { 0x2ac, 24, 3 },
+ [PAD_GPIO62] = { 0x2ac, 27, 3 },
+ [PAD_GPIO63] = { 0x2ac, 30, 3 },
+
+ [PAD_GPIO6] = { 0x2b0, 0, 3 },
+ [PAD_GPIO7] = { 0x2b0, 2, 3 },
+ [PAD_GPIO8] = { 0x2b0, 5, 3 },
+ [PAD_GPIO9] = { 0x2b0, 8, 3 },
+};
+
+struct jh7110_vin_group_sel {
+ u16 offset;
+ u8 shift;
+ u8 group;
+};
+
+static const struct jh7110_vin_group_sel
+ jh7110_sys_vin_group_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
+ [PAD_GPIO6] = { 0x2b4, 21, 0 },
+ [PAD_GPIO7] = { 0x2b4, 18, 0 },
+ [PAD_GPIO8] = { 0x2b4, 15, 0 },
+ [PAD_GPIO9] = { 0x2b0, 11, 0 },
+ [PAD_GPIO10] = { 0x2b0, 20, 0 },
+ [PAD_GPIO11] = { 0x2b0, 23, 0 },
+ [PAD_GPIO12] = { 0x2b0, 26, 0 },
+ [PAD_GPIO13] = { 0x2b0, 29, 0 },
+ [PAD_GPIO14] = { 0x2b4, 0, 0 },
+ [PAD_GPIO15] = { 0x2b4, 3, 0 },
+ [PAD_GPIO16] = { 0x2b4, 6, 0 },
+ [PAD_GPIO17] = { 0x2b4, 9, 0 },
+ [PAD_GPIO18] = { 0x2b4, 12, 0 },
+ [PAD_GPIO19] = { 0x2b0, 14, 0 },
+ [PAD_GPIO20] = { 0x2b0, 17, 0 },
+
+ [PAD_GPIO21] = { 0x2b4, 21, 1 },
+ [PAD_GPIO22] = { 0x2b4, 18, 1 },
+ [PAD_GPIO23] = { 0x2b4, 15, 1 },
+ [PAD_GPIO24] = { 0x2b0, 11, 1 },
+ [PAD_GPIO25] = { 0x2b0, 20, 1 },
+ [PAD_GPIO26] = { 0x2b0, 23, 1 },
+ [PAD_GPIO27] = { 0x2b0, 26, 1 },
+ [PAD_GPIO28] = { 0x2b0, 29, 1 },
+ [PAD_GPIO29] = { 0x2b4, 0, 1 },
+ [PAD_GPIO30] = { 0x2b4, 3, 1 },
+ [PAD_GPIO31] = { 0x2b4, 6, 1 },
+ [PAD_GPIO32] = { 0x2b4, 9, 1 },
+ [PAD_GPIO33] = { 0x2b4, 12, 1 },
+ [PAD_GPIO34] = { 0x2b0, 14, 1 },
+ [PAD_GPIO35] = { 0x2b0, 17, 1 },
+
+ [PAD_GPIO36] = { 0x2b4, 21, 2 },
+ [PAD_GPIO37] = { 0x2b4, 18, 2 },
+ [PAD_GPIO38] = { 0x2b4, 15, 2 },
+ [PAD_GPIO39] = { 0x2b0, 11, 2 },
+ [PAD_GPIO40] = { 0x2b0, 20, 2 },
+ [PAD_GPIO41] = { 0x2b0, 23, 2 },
+ [PAD_GPIO42] = { 0x2b0, 26, 2 },
+ [PAD_GPIO43] = { 0x2b0, 29, 2 },
+ [PAD_GPIO44] = { 0x2b4, 0, 2 },
+ [PAD_GPIO45] = { 0x2b4, 3, 2 },
+ [PAD_GPIO46] = { 0x2b4, 6, 2 },
+ [PAD_GPIO47] = { 0x2b4, 9, 2 },
+ [PAD_GPIO48] = { 0x2b4, 12, 2 },
+ [PAD_GPIO49] = { 0x2b0, 14, 2 },
+ [PAD_GPIO50] = { 0x2b0, 17, 2 },
+};
+
+static void jh7110_set_function(struct udevice *dev,
+ unsigned int pin, u32 func)
+{
+ const struct jh7110_func_sel *fs = &jh7110_sys_func_sel[pin];
+ struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+ void __iomem *reg;
+ u32 mask;
+
+ if (!fs->offset)
+ return;
+
+ if (func > fs->max)
+ return;
+
+ reg = priv->base + fs->offset;
+ func = func << fs->shift;
+ mask = 0x3U << fs->shift;
+
+ func |= readl(reg) & ~mask;
+ writel(func, reg);
+}
+
+static void jh7110_set_vin_group(struct udevice *dev, unsigned int pin)
+{
+ const struct jh7110_vin_group_sel *gs =
+ &jh7110_sys_vin_group_sel[pin];
+ struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+ void __iomem *reg;
+ u32 mask;
+ u32 grp;
+
+ if (!gs->offset)
+ return;
+
+ reg = priv->base + gs->offset;
+ grp = gs->group << gs->shift;
+ mask = 0x3U << gs->shift;
+
+ grp |= readl(reg) & ~mask;
+ writel(grp, reg);
+}
+
+static int jh7110_sys_set_one_pin_mux(struct udevice *dev, unsigned int pin,
+ unsigned int din, u32 dout, u32 doen, u32 func)
+{
+ struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+
+ if (pin < priv->info->ngpios && func == 0)
+ starfive_set_gpiomux(dev, pin, din, dout, doen);
+
+ jh7110_set_function(dev, pin, func);
+
+ if (pin < priv->info->ngpios && func == 2)
+ jh7110_set_vin_group(dev, pin);
+
+ return 0;
+}
+
+static int jh7110_sys_get_padcfg_base(struct udevice *dev,
+ unsigned int pin)
+{
+ if (pin < PAD_GMAC1_MDC)
+ return SYS_GPO_PDA_0_74_CFG;
+ else if (pin > PAD_GMAC1_TXC && pin <= PAD_QSPI_DATA3)
+ return SYS_GPO_PDA_89_94_CFG;
+ else
+ return -1;
+}
+
+static void jh7110_sys_init_hw(struct udevice *dev)
+{
+ struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+
+ /* mask all GPIO interrupts */
+ writel(0U, priv->base + JH7110_SYS_GPIOIE0);
+ writel(0U, priv->base + JH7110_SYS_GPIOIE1);
+ /* clear edge interrupt flags */
+ writel(~0U, priv->base + JH7110_SYS_GPIOIC0);
+ writel(~0U, priv->base + JH7110_SYS_GPIOIC1);
+ /* enable GPIO interrupts */
+ writel(1U, priv->base + JH7110_SYS_GPIOEN);
+}
+
+const struct starfive_pinctrl_soc_info jh7110_sys_pinctrl_info = {
+ /* pin conf */
+ .set_one_pinmux = jh7110_sys_set_one_pin_mux,
+ .get_padcfg_base = jh7110_sys_get_padcfg_base,
+
+ /* gpio dout/doen/din/gpioinput register */
+ .dout_reg_base = JH7110_SYS_DOUT,
+ .dout_mask = GENMASK(6, 0),
+ .doen_reg_base = JH7110_SYS_DOEN,
+ .doen_mask = GENMASK(5, 0),
+ .gpi_reg_base = JH7110_SYS_GPI,
+ .gpi_mask = GENMASK(6, 0),
+ .gpioin_reg_base = JH7110_SYS_GPIOIN,
+
+ /* gpio */
+ .gpio_bank_name = "GPIO",
+ .ngpios = JH7110_SYS_NGPIO,
+ .gpio_init_hw = jh7110_sys_init_hw,
+};
+
+static int jh7110_sys_pinctrl_probe(struct udevice *dev)
+{
+ struct starfive_pinctrl_soc_info *info =
+ (struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+ return starfive_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id jh7110_sys_pinctrl_ids[] = {
+ /* JH7110 sys pinctrl */
+ { .compatible = "starfive,jh7110-sys-pinctrl",
+ .data = (ulong)&jh7110_sys_pinctrl_info, },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(jh7110_sys_pinctrl) = {
+ .name = "jh7110-sys-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = jh7110_sys_pinctrl_ids,
+ .priv_auto = sizeof(struct starfive_pinctrl_priv),
+ .ops = &starfive_pinctrl_ops,
+ .probe = jh7110_sys_pinctrl_probe,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pinctrl / GPIO driver for StarFive JH7100 SoC
+ *
+ * Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd.
+ * Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ * Author: Jianlong Huang <jianlong.huang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <asm-generic/gpio.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <dm/device_compat.h>
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+
+#include "pinctrl-starfive.h"
+
+/* pad control bits */
+#define STARFIVE_PADCFG_POS BIT(7)
+#define STARFIVE_PADCFG_SMT BIT(6)
+#define STARFIVE_PADCFG_SLEW BIT(5)
+#define STARFIVE_PADCFG_PD BIT(4)
+#define STARFIVE_PADCFG_PU BIT(3)
+#define STARFIVE_PADCFG_BIAS (STARFIVE_PADCFG_PD | STARFIVE_PADCFG_PU)
+#define STARFIVE_PADCFG_DS_MASK GENMASK(2, 1)
+#define STARFIVE_PADCFG_DS_2MA (0U << 1)
+#define STARFIVE_PADCFG_DS_4MA BIT(1)
+#define STARFIVE_PADCFG_DS_8MA (2U << 1)
+#define STARFIVE_PADCFG_DS_12MA (3U << 1)
+#define STARFIVE_PADCFG_IE BIT(0)
+#define GPIO_NUM_PER_WORD 32
+
+/*
+ * The packed pinmux values from the device tree look like this:
+ *
+ * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
+ * | din | dout | doen | function | pin |
+ */
+static unsigned int starfive_pinmux_din(u32 v)
+{
+ return (v & GENMASK(31, 24)) >> 24;
+}
+
+static u32 starfive_pinmux_dout(u32 v)
+{
+ return (v & GENMASK(23, 16)) >> 16;
+}
+
+static u32 starfive_pinmux_doen(u32 v)
+{
+ return (v & GENMASK(15, 10)) >> 10;
+}
+
+static u32 starfive_pinmux_function(u32 v)
+{
+ return (v & GENMASK(9, 8)) >> 8;
+}
+
+static unsigned int starfive_pinmux_pin(u32 v)
+{
+ return v & GENMASK(7, 0);
+}
+
+void starfive_set_gpiomux(struct udevice *dev, unsigned int pin,
+ unsigned int din, u32 dout, u32 doen)
+{
+ struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct starfive_pinctrl_soc_info *info = priv->info;
+
+ unsigned int offset = 4 * (pin / 4);
+ unsigned int shift = 8 * (pin % 4);
+ u32 dout_mask = info->dout_mask << shift;
+ u32 done_mask = info->doen_mask << shift;
+ u32 ival, imask;
+ void __iomem *reg_dout;
+ void __iomem *reg_doen;
+ void __iomem *reg_din;
+
+ reg_dout = priv->base + info->dout_reg_base + offset;
+ reg_doen = priv->base + info->doen_reg_base + offset;
+ dout <<= shift;
+ doen <<= shift;
+ if (din != GPI_NONE) {
+ unsigned int ioffset = 4 * (din / 4);
+ unsigned int ishift = 8 * (din % 4);
+
+ reg_din = priv->base + info->gpi_reg_base + ioffset;
+ ival = (pin + 2) << ishift;
+ imask = info->gpi_mask << ishift;
+ } else {
+ reg_din = NULL;
+ }
+
+ dout |= readl(reg_dout) & ~dout_mask;
+ writel(dout, reg_dout);
+ doen |= readl(reg_doen) & ~done_mask;
+ writel(doen, reg_doen);
+ if (reg_din) {
+ ival |= readl(reg_din) & ~imask;
+ writel(ival, reg_din);
+ }
+}
+
+static const struct pinconf_param starfive_pinconf_params[] = {
+ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+ { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
+ { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
+ { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
+ { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
+ { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
+ { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
+ { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
+ { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
+};
+
+static const u8 starfive_drive_strength_mA[4] = { 2, 4, 8, 12 };
+
+static u32 starfive_padcfg_ds_from_mA(u32 v)
+{
+ int i;
+
+ for (i = 0; i < 3; i++) {
+ if (v <= starfive_drive_strength_mA[i])
+ break;
+ }
+ return i << 1;
+}
+
+static void starfive_padcfg_rmw(struct udevice *dev,
+ unsigned int pin, u32 mask, u32 value)
+{
+ struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+ struct starfive_pinctrl_soc_info *info = priv->info;
+ void __iomem *reg;
+ int padcfg_base;
+
+ if (!info->get_padcfg_base)
+ return;
+
+ padcfg_base = info->get_padcfg_base(dev, pin);
+ if (padcfg_base < 0)
+ return;
+
+ reg = priv->base + padcfg_base + 4 * pin;
+ value &= mask;
+
+ value |= readl(reg) & ~mask;
+ writel(value, reg);
+}
+
+static int starfive_pinconf_set(struct udevice *dev, unsigned int pin,
+ unsigned int param, unsigned int arg)
+{
+ u16 mask = 0;
+ u16 value = 0;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ mask |= STARFIVE_PADCFG_BIAS;
+ value &= ~STARFIVE_PADCFG_BIAS;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (arg == 0)
+ return -EINVAL;
+ mask |= STARFIVE_PADCFG_BIAS;
+ value = (value & ~STARFIVE_PADCFG_BIAS) | STARFIVE_PADCFG_PD;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (arg == 0)
+ return -EINVAL;
+ mask |= STARFIVE_PADCFG_BIAS;
+ value = (value & ~STARFIVE_PADCFG_BIAS) | STARFIVE_PADCFG_PU;
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ mask |= STARFIVE_PADCFG_DS_MASK;
+ value = (value & ~STARFIVE_PADCFG_DS_MASK) |
+ starfive_padcfg_ds_from_mA(arg);
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ mask |= STARFIVE_PADCFG_IE;
+ if (arg)
+ value |= STARFIVE_PADCFG_IE;
+ else
+ value &= ~STARFIVE_PADCFG_IE;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ mask |= STARFIVE_PADCFG_SMT;
+ if (arg)
+ value |= STARFIVE_PADCFG_SMT;
+ else
+ value &= ~STARFIVE_PADCFG_SMT;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ mask |= STARFIVE_PADCFG_SLEW;
+ if (arg)
+ value |= STARFIVE_PADCFG_SLEW;
+ else
+ value &= ~STARFIVE_PADCFG_SLEW;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ starfive_padcfg_rmw(dev, pin, mask, value);
+
+ return 0;
+}
+
+static int starfive_property_set(struct udevice *dev, u32 pinmux_group)
+{
+ struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+ struct starfive_pinctrl_soc_info *info = priv->info;
+
+ if (info->set_one_pinmux)
+ info->set_one_pinmux(dev,
+ starfive_pinmux_pin(pinmux_group),
+ starfive_pinmux_din(pinmux_group),
+ starfive_pinmux_dout(pinmux_group),
+ starfive_pinmux_doen(pinmux_group),
+ starfive_pinmux_function(pinmux_group));
+
+ return starfive_pinmux_pin(pinmux_group);
+}
+
+const struct pinctrl_ops starfive_pinctrl_ops = {
+ .set_state = pinctrl_generic_set_state,
+ .pinconf_num_params = ARRAY_SIZE(starfive_pinconf_params),
+ .pinconf_params = starfive_pinconf_params,
+ .pinconf_set = starfive_pinconf_set,
+ .pinmux_property_set = starfive_property_set,
+};
+
+static int starfive_gpio_get_direction(struct udevice *dev, unsigned int off)
+{
+ struct udevice *pdev = dev->parent;
+ struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+ struct starfive_pinctrl_soc_info *info = priv->info;
+
+ unsigned int offset = 4 * (off / 4);
+ unsigned int shift = 8 * (off % 4);
+ u32 doen = readl(priv->base + info->doen_reg_base + offset);
+
+ doen = (doen >> shift) & info->doen_mask;
+
+ return doen == GPOEN_ENABLE ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static int starfive_gpio_direction_input(struct udevice *dev, unsigned int off)
+{
+ struct udevice *pdev = dev->parent;
+ struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+ struct starfive_pinctrl_soc_info *info = priv->info;
+
+ /* enable input and schmitt trigger */
+ starfive_padcfg_rmw(pdev, off,
+ STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT,
+ STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT);
+
+ if (info->set_one_pinmux)
+ info->set_one_pinmux(pdev, off,
+ GPI_NONE, GPOUT_LOW, GPOEN_DISABLE, 0);
+
+ return 0;
+}
+
+static int starfive_gpio_direction_output(struct udevice *dev,
+ unsigned int off, int val)
+{
+ struct udevice *pdev = dev->parent;
+ struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+ struct starfive_pinctrl_soc_info *info = priv->info;
+
+ if (info->set_one_pinmux)
+ info->set_one_pinmux(pdev, off,
+ GPI_NONE, val ? GPOUT_HIGH : GPOUT_LOW,
+ GPOEN_ENABLE, 0);
+
+ /* disable input, schmitt trigger and bias */
+ starfive_padcfg_rmw(pdev, off,
+ STARFIVE_PADCFG_IE | STARFIVE_PADCFG_SMT
+ | STARFIVE_PADCFG_BIAS,
+ 0);
+
+ return 0;
+}
+
+static int starfive_gpio_get_value(struct udevice *dev, unsigned int off)
+{
+ struct udevice *pdev = dev->parent;
+ struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+ struct starfive_pinctrl_soc_info *info = priv->info;
+
+ void __iomem *reg = priv->base + info->gpioin_reg_base
+ + 4 * (off / GPIO_NUM_PER_WORD);
+
+ return !!(readl(reg) & BIT(off % GPIO_NUM_PER_WORD));
+}
+
+static int starfive_gpio_set_value(struct udevice *dev,
+ unsigned int off, int val)
+{
+ struct udevice *pdev = dev->parent;
+ struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+ struct starfive_pinctrl_soc_info *info = priv->info;
+
+ unsigned int offset = 4 * (off / 4);
+ unsigned int shift = 8 * (off % 4);
+ void __iomem *reg_dout = priv->base + info->dout_reg_base + offset;
+ u32 dout = (val ? GPOUT_HIGH : GPOUT_LOW) << shift;
+ u32 mask = info->dout_mask << shift;
+
+ dout |= readl(reg_dout) & ~mask;
+ writel(dout, reg_dout);
+
+ return 0;
+}
+
+static int starfive_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv;
+ struct udevice *pdev = dev->parent;
+ struct starfive_pinctrl_priv *priv = dev_get_priv(pdev);
+ struct starfive_pinctrl_soc_info *info = priv->info;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = info->gpio_bank_name;
+ uc_priv->gpio_count = info->ngpios;
+
+ if (!info->gpio_init_hw)
+ return -ENXIO;
+
+ info->gpio_init_hw(pdev);
+
+ return 0;
+}
+
+static const struct dm_gpio_ops starfive_gpio_ops = {
+ .get_function = starfive_gpio_get_direction,
+ .direction_input = starfive_gpio_direction_input,
+ .direction_output = starfive_gpio_direction_output,
+ .get_value = starfive_gpio_get_value,
+ .set_value = starfive_gpio_set_value,
+};
+
+static struct driver starfive_gpio_driver = {
+ .name = "starfive_gpio",
+ .id = UCLASS_GPIO,
+ .probe = starfive_gpio_probe,
+ .ops = &starfive_gpio_ops,
+};
+
+static int starfive_gpiochip_register(struct udevice *parent)
+{
+ struct uclass_driver *drv;
+ struct udevice *dev;
+ int ret;
+ ofnode node;
+
+ drv = lists_uclass_lookup(UCLASS_GPIO);
+ if (!drv)
+ return -ENOENT;
+
+ node = dev_ofnode(parent);
+ ret = device_bind_with_driver_data(parent, &starfive_gpio_driver,
+ "starfive_gpio", 0, node, &dev);
+
+ return (ret == 0) ? 0 : ret;
+}
+
+int starfive_pinctrl_probe(struct udevice *dev,
+ const struct starfive_pinctrl_soc_info *info)
+{
+ struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ /* Bind pinctrl_info from .data to priv */
+ priv->info =
+ (struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+ if (!priv->info)
+ return -EINVAL;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ /* gpiochip register */
+ ret = starfive_gpiochip_register(dev);
+
+ return (ret == 0) ? 0 : ret;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Pinctrl / GPIO driver for StarFive SoC
+ *
+ * Copyright (C) 2022 Shanghai StarFive Technology Co., Ltd.
+ * Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
+ * Author: Jianlong Huang <jianlong.huang@starfivetech.com>
+ */
+
+#define STARFIVE_PINCTRL(a, b) { .number = a, .name = b }
+
+extern const struct pinctrl_ops starfive_pinctrl_ops;
+
+struct starfive_pinctrl_pin {
+ unsigned int number;
+ const char *name;
+};
+
+struct starfive_pinctrl_soc_info {
+ /* pinctrl */
+ int (*set_one_pinmux)(struct udevice *dev, unsigned int pin,
+ unsigned int din, u32 dout, u32 doen, u32 func);
+ int (*get_padcfg_base)(struct udevice *dev,
+ unsigned int pin);
+
+ /* gpio dout/doen/din/gpioinput register */
+ unsigned int dout_reg_base;
+ unsigned int dout_mask;
+ unsigned int doen_reg_base;
+ unsigned int doen_mask;
+ unsigned int gpi_reg_base;
+ unsigned int gpi_mask;
+ unsigned int gpioin_reg_base;
+
+ /* gpio */
+ const char *gpio_bank_name;
+ int ngpios;
+ void (*gpio_init_hw)(struct udevice *dev);
+};
+
+/*
+ * struct starfive_pinctrl_priv - private data for Starfive pinctrl driver
+ *
+ * @padctl_base: base address of the pinctrl device
+ * @info: SoC specific data & function
+ */
+struct starfive_pinctrl_priv {
+ void __iomem *base;
+ struct starfive_pinctrl_soc_info *info;
+};
+
+void starfive_set_gpiomux(struct udevice *dev, unsigned int pin,
+ unsigned int din, u32 dout, u32 doen);
+int starfive_pinctrl_probe(struct udevice *dev,
+ const struct starfive_pinctrl_soc_info *info);
source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
source "drivers/ram/octeon/Kconfig"
+source "drivers/ram/starfive/Kconfig"
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
obj-$(CONFIG_RAM_SIFIVE) += sifive/
-
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/
+endif
obj-$(CONFIG_ARCH_OCTEON) += octeon/
--- /dev/null
+config SPL_STARFIVE_DDR
+ bool "StarFive DDR driver in SPL"
+ depends on SPL_RAM && STARFIVE_JH7110
+ help
+ This enables DDR support for the platforms based on StarFive JH7110 SoC.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 StarFive, Inc
+#
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_start.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_train.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive_ddr.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_utils.o
+obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrcsr_boot.o
+endif
\ No newline at end of file
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/regs.h>
+#include <linux/delay.h>
+#include <wait_bit.h>
+
+#include "starfive_ddr.h"
+
+#define REGOFFSET(offset) ((offset) / 4)
+
+static const struct ddr_reg_cfg ddr_csr_cfg[] = {
+ {0x0, 0x0, 0x00000001, REGSETALL},
+ {0xf00, 0x0, 0x40001030, (OFFSET_SEL | F_SET | REG4G | REG8G)},
+ {0xf00, 0x0, 0x40001030, (OFFSET_SEL | F_SET | REG2G)},
+ {0xf04, 0x0, 0x00000001, (OFFSET_SEL | F_SET | REG4G | REG8G)},
+ {0xf04, 0x0, 0x00800001, (OFFSET_SEL | F_SET | REG2G)},
+ {0xf10, 0x0, 0x00400000, (OFFSET_SEL | REGSETALL)},
+ {0xf14, 0x0, 0x043fffff, (OFFSET_SEL | REGSETALL)},
+ {0xf18, 0x0, 0x00000000, (OFFSET_SEL | REGSETALL)},
+ {0xf30, 0x0, 0x1f000041, (OFFSET_SEL | REGSETALL)},
+ {0xf34, 0x0, 0x1f000041, (OFFSET_SEL | F_SET | REG4G | REG8G)},
+ {0x110, 0x0, 0xc0000001, (OFFSET_SEL | REGSETALL)},
+ {0x114, 0x0, 0xffffffff, (OFFSET_SEL | REGSETALL)},
+ {0x10c, 0x0, 0x00000505, REGSETALL},
+ {0x11c, 0x0, 0x00000000, REGSETALL},
+ {0x500, 0x0, 0x00000201, REGSETALL},
+ {0x514, 0x0, 0x00000100, REGSETALL},
+ {0x6a8, 0x0, 0x00040000, REGSETALL},
+ {0xea8, 0x0, 0x00040000, REGSETALL},
+ {0x504, 0x0, 0x40000000, REGSETALL}
+};
+
+static const struct ddr_reg_cfg ddr_csr_cfg1[] = {
+ {0x310, 0x0, 0x00020000, REGSETALL},
+ {0x310, 0x0, 0x00020001, REGSETALL},
+ {0x600, 0x0, 0x002e0176, REGSETALL},
+ {0x604, 0x0, 0x002e0176, REGSETALL},
+ {0x608, 0x0, 0x001700bb, REGSETALL},
+ {0x60c, 0x0, 0x000b005d, REGSETALL},
+ {0x610, 0x0, 0x0005002e, REGSETALL},
+ {0x614, 0x0, 0x00020017, REGSETALL},
+ {0x618, 0x0, 0x00020017, REGSETALL},
+ {0x61c, 0x0, 0x00020017, REGSETALL},
+ {0x678, 0x0, 0x00000019, REGSETALL},
+ {0x100, 0x0, 0x000000f8, REGSETALL},
+ {0x620, 0x0, 0x03030404, REGSETALL},
+ {0x624, 0x0, 0x04030505, REGSETALL},
+ {0x628, 0x0, 0x07030884, REGSETALL},
+ {0x62c, 0x0, 0x13150401, REGSETALL},
+ {0x630, 0x0, 0x17150604, REGSETALL},
+ {0x634, 0x0, 0x00110000, REGSETALL},
+ {0x638, 0x0, 0x200a0a08, REGSETALL},
+ {0x63c, 0x0, 0x1730f803, REGSETALL},
+ {0x640, 0x0, 0x000a0c00, REGSETALL},
+ {0x644, 0x0, 0xa005000a, REGSETALL},
+ {0x648, 0x0, 0x00000000, REGSETALL},
+ {0x64c, 0x0, 0x00081306, REGSETALL},
+ {0x650, 0x0, 0x04070304, REGSETALL},
+ {0x654, 0x0, 0x00000404, REGSETALL},
+ {0x658, 0x0, 0x00000060, REGSETALL},
+ {0x65c, 0x0, 0x00030008, REGSETALL},
+ {0x660, 0x0, 0x00000000, REGSETALL},
+ {0x680, 0x0, 0x00000603, REGSETALL},
+ {0x684, 0x0, 0x01000202, REGSETALL},
+ {0x688, 0x0, 0x0413040d, REGSETALL},
+ {0x68c, 0x0, 0x20002420, REGSETALL},
+ {0x690, 0x0, 0x00140000, REGSETALL},
+ {0x69c, 0x0, 0x01240074, REGSETALL},
+ {0x6a0, 0x0, 0x00000000, REGSETALL},
+ {0x6a4, 0x0, 0x20240c00, REGSETALL},
+ {0x6a8, 0x0, 0x00040000, REGSETALL},
+ {0x4, 0x0, 0x30010006, (F_SET | REG4G | REG8G)},
+ {0x4, 0x0, 0x10010006, (F_SET | REG2G)},
+ {0xc, 0x0, 0x00000002, REGSETALL},
+ {0x4, 0x0, 0x30020000, (F_SET | REG4G | REG8G)},
+ {0x4, 0x0, 0x10020000, (F_SET | REG2G)},
+ {0xc, 0x0, 0x00000002, REGSETALL},
+ {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)},
+ {0x4, 0x0, 0x10030031, (F_SET | REG2G)},
+ {0xc, 0x0, 0x00000002, REGSETALL},
+ {0x4, 0x0, 0x300b0033, (F_SET | REG4G | REG8G)},
+ {0x4, 0x0, 0x100b0033, (F_SET | REG2G)},
+ {0xc, 0x0, 0x00000002, REGSETALL},
+ {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)},
+ {0x4, 0x0, 0x10160016, (F_SET | REG2G)},
+ {0xc, 0x0, 0x00000002, REGSETALL},
+ {0x10, 0x0, 0x00000010, REGSETALL},
+ {0x14, 0x0, 0x00000001, REGSETALL},
+};
+
+static const struct ddr_reg_cfg ddr_csr_cfg2[] = {
+ {0xb8, 0xf0ffffff, 0x3000000, REGCLRSETALL},
+ {0x84, 0xFEFFFFFF, 0x0, REGCLRSETALL},
+ {0xb0, 0xFFFEFFFF, 0x0, REGCLRSETALL},
+ {0xb0, 0xFEFFFFFF, 0x0, REGCLRSETALL},
+ {0xb4, 0xffffffff, 0x1, REGCLRSETALL},
+ {0x248, 0xffffffff, 0x3000000, REGCLRSETALL},
+ {0x24c, 0xffffffff, 0x300, REGCLRSETALL},
+ {0x24c, 0xffffffff, 0x3000000, REGCLRSETALL},
+ {0xb0, 0xffffffff, 0x100, REGCLRSETALL},
+ {0xb8, 0xFFF0FFFF, 0x30000, REGCLRSETALL},
+ {0x84, 0xFFFEFFFF, 0x0, REGCLRSETALL},
+ {0xac, 0xFFFEFFFF, 0x0, REGCLRSETALL},
+ {0xac, 0xFEFFFFFF, 0x0, REGCLRSETALL},
+ {0xb0, 0xffffffff, 0x1, REGCLRSETALL},
+ {0x248, 0xffffffff, 0x30000, REGCLRSETALL},
+ {0x24c, 0xffffffff, 0x3, REGCLRSETALL},
+ {0x24c, 0xffffffff, 0x30000, REGCLRSETALL},
+ {0x250, 0xffffffff, 0x3000000, REGCLRSETALL},
+ {0x254, 0xffffffff, 0x3000000, REGCLRSETALL},
+ {0x258, 0xffffffff, 0x3000000, REGCLRSETALL},
+ {0xac, 0xffffffff, 0x100, REGCLRSETALL},
+ {0x10c, 0xFFFFF0FF, 0x300, REGCLRSETALL},
+ {0x110, 0xFFFFFEFF, 0x0, REGCLRSETALL},
+ {0x11c, 0xFFFEFFFF, 0x0, REGCLRSETALL},
+ {0x11c, 0xFEFFFFFF, 0x0, REGCLRSETALL},
+ {0x120, 0xffffffff, 0x100, REGCLRSETALL},
+ {0x2d0, 0xffffffff, 0x300, REGCLRSETALL},
+ {0x2dc, 0xffffffff, 0x300, REGCLRSETALL},
+ {0x2e8, 0xffffffff, 0x300, REGCLRSETALL},
+};
+
+static const struct ddr_reg_cfg ddr_csr_cfg3[] = {
+ {0x100, 0x0, 0x000000e0, REGSETALL},
+ {0x620, 0x0, 0x04041417, REGSETALL},
+ {0x624, 0x0, 0x09110609, REGSETALL},
+ {0x628, 0x0, 0x442d0994, REGSETALL},
+ {0x62c, 0x0, 0x271e102b, REGSETALL},
+ {0x630, 0x0, 0x291b140a, REGSETALL},
+ {0x634, 0x0, 0x001c0000, REGSETALL},
+ {0x638, 0x0, 0x200f0f08, REGSETALL},
+ {0x63c, 0x0, 0x29420a06, REGSETALL},
+ {0x640, 0x0, 0x019e1fc1, REGSETALL},
+ {0x644, 0x0, 0x10cb0196, REGSETALL},
+ {0x648, 0x0, 0x00000000, REGSETALL},
+ {0x64c, 0x0, 0x00082714, REGSETALL},
+ {0x650, 0x0, 0x16442f0d, REGSETALL},
+ {0x654, 0x0, 0x00001916, REGSETALL},
+ {0x658, 0x0, 0x00000060, REGSETALL},
+ {0x65c, 0x0, 0x00600020, REGSETALL},
+ {0x660, 0x0, 0x00000000, REGSETALL},
+ {0x680, 0x0, 0x0c00040f, REGSETALL},
+ {0x684, 0x0, 0x03000604, REGSETALL},
+ {0x688, 0x0, 0x0515040d, REGSETALL},
+ {0x68c, 0x0, 0x20002c20, REGSETALL},
+ {0x690, 0x0, 0x00140000, REGSETALL},
+ {0x69c, 0x0, 0x01240074, REGSETALL},
+ {0x6a0, 0x0, 0x00000000, REGSETALL},
+ {0x6a4, 0x0, 0x202c0c00, REGSETALL},
+ {0x6a8, 0x0, 0x00040000, REGSETALL},
+ {0x4, 0x0, 0x30010036, (F_SET | REG4G | REG8G)},
+ {0x4, 0x0, 0x10010036, (F_SET | REG2G)},
+ {0xc, 0x0, 0x00000002, REGSETALL},
+ {0x4, 0x0, 0x3002001b, (F_SET | REG4G | REG8G)},
+ {0x4, 0x0, 0x10010036, (F_SET | REG2G)},
+ {0xc, 0x0, 0x00000002, REGSETALL},
+ {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)},
+ {0x4, 0x0, 0x10030031, (F_SET | REG2G)},
+ {0xc, 0x0, 0x00000002, REGSETALL},
+ {0x4, 0x0, 0x300b0066, (F_SET | REG4G)},
+ {0x4, 0x0, 0x300b0036, (F_SET | REG8G)},
+ {0x4, 0x0, 0x100b0066, (F_SET | REG2G)},
+ {0xc, 0x0, 0x00000002, REGSETALL},
+ {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)},
+ {0x4, 0x0, 0x10160016, (F_SET | REG2G)},
+ {0xc, 0x0, 0x00000002, REGSETALL},
+ {0x410, 0x0, 0x00101010, REGSETALL},
+ {0x420, 0x0, 0x0c181006, REGSETALL},
+ {0x424, 0x0, 0x20200820, REGSETALL},
+ {0x428, 0x0, 0x80000020, REGSETALL},
+ {0x0, 0x0, 0x00000001, REGSETALL},
+ {0x108, 0x0, 0x00003000, REGSETALL},
+ {0x704, 0x0, 0x00000007, REGSETALL | OFFSET_SEL},
+ {0x330, 0x0, 0x09313fff, (F_SET | REG4G | REG8G)},
+ {0x330, 0x0, 0x09311fff, (F_SET | REG2G)},
+ {0x508, 0x0, 0x00000033, (F_SET | REG4G | REG8G)},
+ {0x508, 0x0, 0x00000013, (F_SET | REG2G)},
+ {0x324, 0x0, 0x00002000, REGSETALL},
+ {0x104, 0x0, 0x90000000, REGSETALL},
+ {0x510, 0x0, 0x00000100, REGSETALL},
+ {0x514, 0x0, 0x00000000, REGSETALL},
+ {0x700, 0x0, 0x00000003, REGSETALL | OFFSET_SEL},
+ {0x514, 0x0, 0x00000600, REGSETALL},
+ {0x20, 0x0, 0x00000001, REGSETALL},
+};
+
+static void ddr_csr_set(u32 *csrreg, u32 *secreg, const struct ddr_reg_cfg *data,
+ u32 len, u32 mask)
+{
+ u32 *addr;
+ u32 i;
+
+ for (i = 0; i < len; i++) {
+ if (!(data[i].flag & mask))
+ continue;
+
+ if (data[i].flag & OFFSET_SEL)
+ addr = secreg + REGOFFSET(data[i].offset);
+ else
+ addr = csrreg + REGOFFSET(data[i].offset);
+
+ if (data[i].flag & F_CLRSET)
+ DDR_REG_TRIGGER(addr, data[i].mask, data[i].val);
+ else
+ out_le32(addr, data[i].val);
+ }
+}
+
+void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
+{
+ u32 len;
+ u32 val;
+ u32 mask;
+ int ret;
+
+ switch (size) {
+ case DDR_SIZE_2G:
+ mask = REG2G;
+ break;
+
+ case DDR_SIZE_4G:
+ mask = REG4G;
+ break;
+
+ case DDR_SIZE_8G:
+ mask = REG8G;
+ break;
+
+ case DDR_SIZE_16G:
+ default:
+ return;
+ };
+
+ len = ARRAY_SIZE(ddr_csr_cfg);
+ ddr_csr_set(csrreg, secreg, ddr_csr_cfg, len, mask);
+
+ ret = wait_for_bit_le32(csrreg + REGOFFSET(0x504), BIT(31),
+ true, 1000, false);
+ if (ret)
+ return;
+
+ out_le32(csrreg + REGOFFSET(0x504), 0x0);
+ out_le32(csrreg + REGOFFSET(0x50c), 0x0);
+ udelay(300);
+ out_le32(csrreg + REGOFFSET(0x50c), 0x1);
+ mdelay(3);
+
+ switch (size) {
+ case DDR_SIZE_2G:
+ out_le32(csrreg + REGOFFSET(0x10), 0x1c);
+ break;
+
+ case DDR_SIZE_8G:
+ case DDR_SIZE_4G:
+ out_le32(csrreg + REGOFFSET(0x10), 0x3c);
+ break;
+
+ case DDR_SIZE_16G:
+ default:
+ break;
+ };
+
+ out_le32(csrreg + REGOFFSET(0x14), 0x1);
+ udelay(4);
+
+ len = ARRAY_SIZE(ddr_csr_cfg1);
+ ddr_csr_set(csrreg, secreg, ddr_csr_cfg1, len, mask);
+
+ udelay(4);
+ out_le32(csrreg + REGOFFSET(0x10), 0x11);
+ out_le32(csrreg + REGOFFSET(0x14), 0x1);
+
+ switch (size) {
+ case DDR_SIZE_4G:
+ case DDR_SIZE_8G:
+ out_le32(csrreg + REGOFFSET(0x10), 0x20);
+ out_le32(csrreg + REGOFFSET(0x14), 0x1);
+ udelay(4);
+ out_le32(csrreg + REGOFFSET(0x10), 0x21);
+ out_le32(csrreg + REGOFFSET(0x14), 0x1);
+ break;
+
+ case DDR_SIZE_2G:
+ case DDR_SIZE_16G:
+ default:
+ break;
+ };
+
+ out_le32(csrreg + REGOFFSET(0x514), 0x0);
+ ret = wait_for_bit_le32(csrreg + REGOFFSET(0x518), BIT(1),
+ true, 1000, false);
+ if (ret)
+ return;
+
+ val = in_le32(csrreg + REGOFFSET(0x518));
+ while ((val & 0x2) != 0x0) {
+ val = in_le32(phyreg + 1);
+
+ if ((val & 0x20) == 0x20) {
+ switch (val & 0x1f) {
+ case 0: /* ddrc_clock=12M */
+ DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
+ break;
+ case 1: /* ddrc_clock=200M */
+ DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV8);
+ break;
+ case 2: /* ddrc_clock=800M */
+ DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV2);
+ break;
+ default:
+ break;
+ };
+
+ out_le32(phyreg + 2, 0x1);
+ ret = wait_for_bit_le32(phyreg + 2, BIT(0), false, 1000, false);
+ if (ret)
+ return;
+ }
+
+ udelay(1);
+ val = in_le32(csrreg + REGOFFSET(0x518));
+ };
+
+ val = in_le32(phyreg + 2048 + 83);
+ val = in_le32(phyreg + 2048 + 84);
+ out_le32(phyreg + 2048 + 84, val & 0xF8000000);
+
+ len = ARRAY_SIZE(ddr_csr_cfg2);
+ ddr_csr_set(phyreg + PHY_BASE_ADDR, secreg, ddr_csr_cfg2, len, mask);
+
+ len = ARRAY_SIZE(ddr_csr_cfg3);
+ ddr_csr_set(csrreg, secreg, ddr_csr_cfg3, len, mask);
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "starfive_ddr.h"
+
+static const struct ddr_reg_cfg ddr_start_cfg[] = {
+ {89, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
+ {78, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
+ {345, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
+ {334, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
+ {601, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
+ {590, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
+ {857, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
+ {846, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
+ {1793, 0xfffffeff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
+ {1793, 0xfffcffff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
+ {125, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
+ {102, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
+ {105, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
+ {92, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
+ {94, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
+ {96, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
+ {89, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
+ {381, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
+ {358, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
+ {361, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
+ {348, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
+ {350, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
+ {352, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
+ {345, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
+ {637, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
+ {614, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
+ {617, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
+ {604, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
+ {606, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
+ {608, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
+ {601, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
+ {893, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
+ {870, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
+ {873, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
+ {860, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
+ {862, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
+ {864, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
+ {857, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
+ {1895, 0xffffe000, 0x00001342, (OFFSET_SEL | REGCLRSETALL)},
+ {1835, 0xfffff0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
+ {1793, 0xfffffeff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
+ {62, 0xfffffeff, 0x0, REGCLRSETALL},
+ {66, 0xfffffeff, 0x0, REGCLRSETALL},
+ {166, 0xffffff80, 0x00000001, REGCLRSETALL},
+ {62, 0xfff0ffff, 0x00010000, REGCLRSETALL},
+ {62, 0xf0ffffff, 0x01000000, REGCLRSETALL},
+ {166, 0xffff80ff, 0x00000100, REGCLRSETALL},
+ {179, 0xff80ffff, 0x00010000, REGCLRSETALL},
+ {67, 0xffe0ffff, 0x00010000, REGCLRSETALL},
+ {67, 0xe0ffffff, 0x01000000, REGCLRSETALL},
+ {179, 0x80ffffff, 0x01000000, REGCLRSETALL},
+ {166, 0xff80ffff, 0x00010000, REGCLRSETALL},
+ {62, 0xfff0ffff, 0x00010000, REGCLRSETALL},
+ {62, 0xf0ffffff, 0x01000000, REGCLRSETALL},
+ {166, 0x80ffffff, 0x01000000, REGCLRSETALL},
+ {182, 0xff80ffff, 0x00010000, REGCLRSETALL},
+ {67, 0xffe0ffff, 0x00010000, REGCLRSETALL},
+ {67, 0xe0ffffff, 0x01000000, REGCLRSETALL},
+ {182, 0x80ffffff, 0x01000000, REGCLRSETALL},
+ {167, 0xffffff80, 0x00000017, REGCLRSETALL},
+ {62, 0xfff0ffff, 0x00010000, REGCLRSETALL},
+ {62, 0xf0ffffff, 0x01000000, REGCLRSETALL},
+ {167, 0xffff80ff, 0x00001700, REGCLRSETALL},
+ {185, 0xff80ffff, 0x00200000, REGCLRSETALL},
+ {67, 0xffe0ffff, 0x00010000, REGCLRSETALL},
+ {67, 0xe0ffffff, 0x01000000, REGCLRSETALL},
+ {185, 0x80ffffff, 0x20000000, REGCLRSETALL},
+ {10, 0xffffffe0, 0x00000002, REGCLRSETALL},
+ {0, 0xfffffffe, 0x00000001, REGCLRSETALL},
+ {11, 0xfffffff0, 0x00000005, (F_CLRSET | REG2G)},
+ {247, 0xffffffff, 0x00000008, REGCLRSETALL},
+ {249, 0xffffffff, 0x00000800, REGCLRSETALL},
+ {252, 0xffffffff, 0x00000008, REGCLRSETALL},
+ {254, 0xffffffff, 0x00000800, REGCLRSETALL},
+ {281, 0xffffffff, 0x33000000, REGCLRSETALL},
+ {305, 0xffffffff, 0x33000000, REGCLRSETALL},
+ {329, 0xffffffff, 0x33000000, REGCLRSETALL},
+ {353, 0xffffffff, 0x33000000, REGCLRSETALL},
+ {289, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
+ {313, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
+ {337, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
+ {361, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
+ {289, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
+ {313, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
+ {337, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
+ {361, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
+ {282, 0xffffffff, 0x00160000, REGCLRSETALL},
+ {306, 0xffffffff, 0x00160000, REGCLRSETALL},
+ {330, 0xffffffff, 0x00160000, REGCLRSETALL},
+ {354, 0xffffffff, 0x00160000, REGCLRSETALL},
+ {290, 0xffffffff, 0x00160000, REGCLRSETALL},
+ {314, 0xffffffff, 0x00160000, REGCLRSETALL},
+ {338, 0xffffffff, 0x00160000, REGCLRSETALL},
+ {362, 0xffffffff, 0x00160000, REGCLRSETALL},
+ {282, 0xffffff00, 0x17, REGCLRSETALL},
+ {306, 0xffffff00, 0x17, REGCLRSETALL},
+ {330, 0xffffff00, 0x17, REGCLRSETALL},
+ {354, 0xffffff00, 0x17, REGCLRSETALL},
+ {290, 0xffffff00, 0x17, REGCLRSETALL},
+ {314, 0xffffff00, 0x17, REGCLRSETALL},
+ {338, 0xffffff00, 0x17, REGCLRSETALL},
+ {362, 0xffffff00, 0x17, REGCLRSETALL},
+ {282, 0xffff00ff, 0x2000, REGCLRSETALL},
+ {306, 0xffff00ff, 0x2000, REGCLRSETALL},
+ {330, 0xffff00ff, 0x2000, REGCLRSETALL},
+ {354, 0xffff00ff, 0x2000, REGCLRSETALL},
+ {290, 0xffff00ff, 0x2000, REGCLRSETALL},
+ {314, 0xffff00ff, 0x2000, REGCLRSETALL},
+ {338, 0xffff00ff, 0x2000, REGCLRSETALL},
+ {362, 0xffff00ff, 0x2000, REGCLRSETALL},
+ {65, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
+ {321, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
+ {577, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
+ {833, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
+ {96, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
+ {352, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
+ {608, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
+ {864, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
+ {96, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
+ {352, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
+ {608, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
+ {864, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
+ {33, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
+ {289, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
+ {545, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
+ {801, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
+ {1038, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)},
+ {1294, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)},
+ {1550, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)},
+ {83, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
+ {339, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
+ {595, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
+ {851, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
+ {1062, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
+ {1318, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
+ {1574, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
+ {1892, 0xfffc0000, 0x15547, (OFFSET_SEL | REGCLRSETALL)},
+ {1893, 0xfffc0000, 0x7, (OFFSET_SEL | REGCLRSETALL)},
+ {1852, 0xffffe000, 0x07a, (OFFSET_SEL | REGCLRSETALL)},
+ {1853, 0xffffffff, 0x0100, (OFFSET_SEL | REGCLRSETALL)},
+ {1822, 0xffffffff, 0xFF, (OFFSET_SEL | REGCLRSETALL)},
+ {1896, 0xfffffc00, 0x03d5, (OFFSET_SEL | REGCLRSETALL)},
+ {91, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
+ {347, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
+ {603, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
+ {859, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
+ {1912, 0x0, 0xcc3bfc7, (OFFSET_SEL | REGSETALL)},
+ {1913, 0x0, 0xff8f, (OFFSET_SEL | REGSETALL)},
+ {1914, 0x0, 0x33f07ff, (OFFSET_SEL | REGSETALL)},
+ {1915, 0x0, 0xc3c37ff, (OFFSET_SEL | REGSETALL)},
+ {1916, 0x0, 0x1fffff10, (OFFSET_SEL | REGSETALL)},
+ {1917, 0x0, 0x230070, (OFFSET_SEL | REGSETALL)},
+ {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG4G | REG2G | F_SET)},
+ {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG8G | F_SET)},
+ {1919, 0x0, 0xe10, (OFFSET_SEL | REGSETALL)},
+ {1920, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
+ {1921, 0x0, 0x188411, (OFFSET_SEL | REGSETALL)},
+ {1922, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
+ {1923, 0x0, 0x180400, (OFFSET_SEL | REGSETALL)},
+ {1924, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
+ {1925, 0x0, 0x180400, (OFFSET_SEL | REGSETALL)},
+ {1926, 0x0, 0x1fffffcf, (OFFSET_SEL | REGSETALL)},
+ {1927, 0x0, 0x188400, (OFFSET_SEL | REGSETALL)},
+ {1928, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
+ {1929, 0x0, 0x4188411, (OFFSET_SEL | REGSETALL)},
+ {1837, 0x0, 0x24410, (OFFSET_SEL | REGSETALL)},
+ {1840, 0x0, 0x24410, (OFFSET_SEL | REGSETALL)},
+ {1842, 0x0, 0x2ffff, (OFFSET_SEL | REGSETALL)},
+ {76, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
+ {332, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
+ {588, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
+ {844, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
+ {77, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
+ {333, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
+ {589, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
+ {845, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
+ {1062, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
+ {1318, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
+ {1574, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
+ {1062, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
+ {1318, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
+ {1574, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
+ {1028, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)},
+ {1284, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)},
+ {1540, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)},
+ {1848, 0x0, 0x3cf07f8, (OFFSET_SEL | REGSETALL)},
+ {1849, 0x0, 0x3f, (OFFSET_SEL | REGSETALL)},
+ {1850, 0x0, 0x1fffff, (OFFSET_SEL | REGSETALL)},
+ {1851, 0x0, 0x060000, (OFFSET_SEL | REGSETALL)},
+ {130, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
+ {386, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
+ {642, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
+ {898, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
+ {131, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
+ {387, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
+ {643, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
+ {899, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
+ {29, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
+ {285, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
+ {541, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
+ {797, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
+ {30, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
+ {286, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
+ {542, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
+ {798, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
+ {31, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
+ {287, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
+ {543, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
+ {799, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
+ {1071, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
+ {1327, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
+ {1583, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
+ {1808, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
+ {1896, 0xfff0ffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
+};
+
+void ddr_reg_set(u32 *reg, const struct ddr_reg_cfg *data,
+ u32 len, u32 mask)
+{
+ u32 *addr;
+ u32 i;
+
+ for (i = 0; i < len; i++) {
+ if (!(data[i].flag & mask))
+ continue;
+
+ if (data[i].flag & OFFSET_SEL)
+ addr = reg + PHY_AC_BASE_ADDR + data[i].offset;
+ else
+ addr = reg + PHY_BASE_ADDR + data[i].offset;
+
+ if (data[i].flag & F_CLRSET)
+ DDR_REG_TRIGGER(addr, data[i].mask, data[i].val);
+ else if (data[i].flag & F_SET)
+ out_le32(addr, data[i].val);
+ else
+ out_le32(addr, in_le32(addr) + data[i].val);
+ }
+}
+
+void ddr_phy_start(u32 *phyreg, enum ddr_size_t size)
+{
+ u32 len;
+ u32 mask;
+
+ switch (size) {
+ case DDR_SIZE_2G:
+ mask = REG2G;
+ break;
+
+ case DDR_SIZE_4G:
+ mask = REG4G;
+ break;
+
+ case DDR_SIZE_8G:
+ mask = REG8G;
+ break;
+
+ case DDR_SIZE_16G:
+ default:
+ return;
+ };
+
+ len = ARRAY_SIZE(ddr_start_cfg);
+ ddr_reg_set(phyreg, ddr_start_cfg, len, mask);
+ out_le32(phyreg, 0x01);
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+static const u32 ddr_train_data[] = {
+ 0xb00,
+ 0x101,
+ 0x640000,
+ 0x1,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x1,
+ 0x7,
+ 0x10002,
+ 0x300080f,
+ 0x1,
+ 0x5,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x1010000,
+ 0x280a0000,
+ 0x0,
+ 0x1,
+ 0x3200000f,
+ 0x0,
+ 0x0,
+ 0x10102,
+ 0x1,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0xaa,
+ 0x55,
+ 0xb5,
+ 0x4a,
+ 0x56,
+ 0xa9,
+ 0xa9,
+ 0xb5,
+ 0x1000000,
+ 0x1000000,
+ 0x0,
+ 0xf0f0000,
+ 0x14,
+ 0x7d0,
+ 0x300,
+ 0x0,
+ 0x0,
+ 0x1000000,
+ 0x10101,
+ 0x0,
+ 0x30000,
+ 0x100,
+ 0x170f,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0xa140a01,
+ 0x204010a,
+ 0x2080510,
+ 0x40400,
+ 0x1000101,
+ 0x10100,
+ 0x2040f00,
+ 0x34000000,
+ 0x0,
+ 0x0,
+ 0x1000000,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x10100,
+ 0x80101,
+ 0x2000200,
+ 0x1000100,
+ 0x1000000,
+ 0x2000200,
+ 0x200,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0xe000004,
+ 0xc0d100f,
+ 0xa09080b,
+ 0x2010000,
+ 0x80103,
+ 0x200,
+ 0x0,
+ 0xf000000,
+ 0x4,
+ 0xa,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x30100,
+ 0x1010001,
+ 0x10200,
+ 0x4000103,
+ 0x1050001,
+ 0x10600,
+ 0x107,
+ 0x0,
+ 0x0,
+ 0x10001,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x10000,
+ 0x4,
+ 0x0,
+ 0x10000,
+ 0x0,
+ 0x3c0003,
+ 0x80100a0,
+ 0x16,
+ 0x2c,
+ 0x33,
+ 0x20043,
+ 0x2000200,
+ 0x4,
+ 0x60c,
+ 0xa1400,
+ 0x280000,
+ 0x6,
+ 0x46,
+ 0x70,
+ 0x610,
+ 0x12b,
+ 0x4001035,
+ 0x1010404,
+ 0x1e01,
+ 0x1e001e,
+ 0x1000100,
+ 0x100,
+ 0x0,
+ 0x5060403,
+ 0x1011108,
+ 0x1010101,
+ 0xf0a0a,
+ 0x0,
+ 0x0,
+ 0x4000000,
+ 0x4021008,
+ 0x4020206,
+ 0xc0034,
+ 0x100038,
+ 0x17003f,
+ 0x10001,
+ 0x10001,
+ 0x10005,
+ 0x20064,
+ 0x100010b,
+ 0x60006,
+ 0x650100,
+ 0x1000065,
+ 0x10c010c,
+ 0x1e1a1e1a,
+ 0x1011e1a,
+ 0xa070601,
+ 0xa07060d,
+ 0x100b080d,
+ 0xc00f,
+ 0xc01000,
+ 0xc01000,
+ 0x21000,
+ 0x120005,
+ 0x190064,
+ 0x10b,
+ 0x1100,
+ 0x1e1a0056,
+ 0x6000101,
+ 0x130204,
+ 0x1e1a0058,
+ 0x1000101,
+ 0x230408,
+ 0x1e1a005e,
+ 0x9000101,
+ 0x610,
+ 0x4040800,
+ 0x40100,
+ 0x3000277,
+ 0xa032001,
+ 0xa0a,
+ 0x80908,
+ 0x901,
+ 0x1100315c,
+ 0xa062002,
+ 0xa0a,
+ 0x141708,
+ 0x150d,
+ 0x2d00838e,
+ 0xf102004,
+ 0xf0b,
+ 0x8c,
+ 0x578,
+ 0xc20,
+ 0x7940,
+ 0x206a,
+ 0x14424,
+ 0x730006,
+ 0x3030133,
+ 0x4,
+ 0x0,
+ 0x4,
+ 0x1,
+ 0x5,
+ 0x2,
+ 0x6,
+ 0x50,
+ 0x1,
+ 0x5,
+ 0x28,
+ 0x73,
+ 0xd6,
+ 0x1,
+ 0x5,
+ 0x6b,
+ 0x1000133,
+ 0x140040,
+ 0x10001,
+ 0x1900040,
+ 0x1000c,
+ 0x42b0040,
+ 0x320,
+ 0x360014,
+ 0x1010101,
+ 0x2020101,
+ 0x8080404,
+ 0x67676767,
+ 0x67676767,
+ 0x67676767,
+ 0x67676767,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x5500,
+ 0x5a00,
+ 0x55003c,
+ 0x0,
+ 0x3c00005a,
+ 0x5500,
+ 0x5a00,
+ 0x55003c,
+ 0x0,
+ 0x3c00005a,
+ 0x18171615,
+ 0x14131211,
+ 0x7060504,
+ 0x3020100,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x1000000,
+ 0x4020201,
+ 0x80804,
+ 0x0,
+ 0x4,
+ 0x0,
+ 0x31,
+ 0x31,
+ 0x0,
+ 0x0,
+ 0x4d4d,
+ 0x0,
+ 0x14,
+ 0x9,
+ 0x31,
+ 0x31,
+ 0x0,
+ 0x0,
+ 0x4d4d,
+ 0x0,
+ 0x34,
+ 0x1b,
+ 0x31,
+ 0x31,
+ 0x0,
+ 0x0,
+ 0x4d4d,
+ 0x0,
+ 0x4,
+ 0x0,
+ 0x31,
+ 0x31,
+ 0x0,
+ 0x0,
+ 0x4d4d,
+ 0x0,
+ 0x14,
+ 0x9,
+ 0x31,
+ 0x31,
+ 0x0,
+ 0x0,
+ 0x4d4d,
+ 0x0,
+ 0x34,
+ 0x1b,
+ 0x31,
+ 0x31,
+ 0x0,
+ 0x0,
+ 0x4d4d,
+ 0x0,
+ 0x4,
+ 0x0,
+ 0x31,
+ 0x31,
+ 0x0,
+ 0x0,
+ 0x4d4d,
+ 0x0,
+ 0x14,
+ 0x9,
+ 0x31,
+ 0x31,
+ 0x0,
+ 0x0,
+ 0x4d4d,
+ 0x0,
+ 0x34,
+ 0x1b,
+ 0x31,
+ 0x31,
+ 0x0,
+ 0x0,
+ 0x4d4d,
+ 0x0,
+ 0x4,
+ 0x0,
+ 0x31,
+ 0x31,
+ 0x0,
+ 0x0,
+ 0x4d4d,
+ 0x0,
+ 0x14,
+ 0x9,
+ 0x31,
+ 0x31,
+ 0x0,
+ 0x0,
+ 0x4d4d,
+ 0x0,
+ 0x34,
+ 0x1b,
+ 0x31,
+ 0x31,
+ 0x0,
+ 0x0,
+ 0x4d4d,
+};
+
+void ddr_phy_train(u32 *phyreg)
+{
+ u32 i, len;
+
+ len = ARRAY_SIZE(ddr_train_data);
+ for (i = 0; i < len; i++)
+ out_le32(phyreg + i, ddr_train_data[i]);
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+static const u32 ddr_phy_data[] = {
+ 0x4f0,
+ 0x0,
+ 0x1030200,
+ 0x0,
+ 0x0,
+ 0x3000000,
+ 0x1000001,
+ 0x3000400,
+ 0x1000001,
+ 0x0,
+ 0x0,
+ 0x1000001,
+ 0x0,
+ 0xc00004,
+ 0xcc0008,
+ 0x660601,
+ 0x3,
+ 0x0,
+ 0x1,
+ 0xaaaa,
+ 0x5555,
+ 0xb5b5,
+ 0x4a4a,
+ 0x5656,
+ 0xa9a9,
+ 0xa9a9,
+ 0xb5b5,
+ 0x0,
+ 0x0,
+ 0x8000000,
+ 0x4000008,
+ 0x408,
+ 0xe4e400,
+ 0x71020,
+ 0xc0020,
+ 0x620,
+ 0x100,
+ 0x55555555,
+ 0xaaaaaaaa,
+ 0x55555555,
+ 0xaaaaaaaa,
+ 0x5555,
+ 0x1000100,
+ 0x800180,
+ 0x1,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x4,
+ 0x20,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x7ff0000,
+ 0x20008008,
+ 0x810,
+ 0x40100,
+ 0x0,
+ 0x1880c01,
+ 0x2003880c,
+ 0x20000125,
+ 0x7ff0200,
+ 0x101,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x20000,
+ 0x51515052,
+ 0x31c06000,
+ 0x11f0004,
+ 0xc0c001,
+ 0x3000000,
+ 0x30202,
+ 0x42100010,
+ 0x10c053e,
+ 0xf0c20,
+ 0x1000140,
+ 0xa30120,
+ 0xc00,
+ 0x210,
+ 0x200,
+ 0x2800000,
+ 0x80800101,
+ 0x3,
+ 0x76543210,
+ 0x8,
+ 0x2800280,
+ 0x2800280,
+ 0x2800280,
+ 0x2800280,
+ 0x280,
+ 0x8000,
+ 0x800080,
+ 0x800080,
+ 0x800080,
+ 0x800080,
+ 0x800080,
+ 0x800080,
+ 0x800080,
+ 0x800080,
+ 0x6e0080,
+ 0x1a00003,
+ 0x0,
+ 0x30000,
+ 0x80200,
+ 0x0,
+ 0x20202020,
+ 0x20202020,
+ 0x2020,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x4f0,
+ 0x0,
+ 0x1030200,
+ 0x0,
+ 0x0,
+ 0x3000000,
+ 0x1000001,
+ 0x3000400,
+ 0x1000001,
+ 0x0,
+ 0x0,
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+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x100,
+ 0x200,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x400000,
+ 0x80,
+ 0xdcba98,
+ 0x3000000,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x2a,
+ 0x15,
+ 0x15,
+ 0x2a,
+ 0x33,
+ 0xc,
+ 0xc,
+ 0x33,
+ 0x0,
+ 0x10000000,
+ 0x0,
+ 0x20202000,
+ 0x202020,
+ 0x20008008,
+ 0x810,
+ 0x0,
+ 0x255,
+ 0x30000,
+ 0x300,
+ 0x300,
+ 0x300,
+ 0x300,
+ 0x300,
+ 0x42080010,
+ 0x33e,
+ 0x1010002,
+ 0x80,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x100,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x50000,
+ 0x4000000,
+ 0x55,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0xf0001,
+ 0x280040,
+ 0x5002,
+ 0x10101,
+ 0x8008,
+ 0x81020,
+ 0x0,
+ 0x0,
+ 0x1000000,
+ 0x1,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x64,
+ 0x0,
+ 0x0,
+ 0x1010000,
+ 0x2020101,
+ 0x4040202,
+ 0x8080404,
+ 0xf0f0808,
+ 0xf0f0f0f,
+ 0x20200f0f,
+ 0x1b428000,
+ 0x4,
+ 0x1010000,
+ 0x1070501,
+ 0x54,
+ 0x4410,
+ 0x4410,
+ 0x4410,
+ 0x4410,
+ 0x4410,
+ 0x4410,
+ 0x4410,
+ 0x4410,
+ 0x4410,
+ 0x4410,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x64,
+ 0x0,
+ 0x108,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x3000000,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x4102035,
+ 0x41020,
+ 0x1c98c98,
+ 0x3f400000,
+ 0x3f3f1f3f,
+ 0x1f3f3f1f,
+ 0x1f3f3f,
+ 0x0,
+ 0x0,
+ 0x1,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x76543210,
+ 0x6010198,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x40700,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x2,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x1142,
+ 0x3020100,
+ 0x3000300,
+ 0x3000300,
+ 0x3000300,
+ 0x3000300,
+ 0x3000300,
+ 0x3000300,
+ 0x3000300,
+ 0x3000300,
+ 0x3000300,
+ 0x3000300,
+ 0x300,
+ 0x300,
+ 0x300,
+ 0x300,
+ 0x2,
+ 0x4011,
+ 0x4011,
+ 0x40,
+ 0x40,
+ 0x4011,
+ 0x1fff00,
+ 0x4011,
+ 0x4011,
+ 0x4011,
+ 0x4011,
+ 0x4011,
+ 0x4011,
+ 0x4011,
+ 0x4011,
+ 0x4011,
+ 0x4011,
+ 0x4011,
+ 0x1004011,
+ 0x200400,
+
+};
+
+void ddr_phy_util(u32 *phyreg)
+{
+ u32 i, len;
+
+ len = ARRAY_SIZE(ddr_phy_data);
+ for (i = 1792; i < len; i++)
+ out_le32(phyreg + i, ddr_phy_data[i]);
+
+ for (i = 0; i < 1792; i++)
+ out_le32(phyreg + i, ddr_phy_data[i]);
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <asm/arch/regs.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/bitops.h>
+#include <linux/sizes.h>
+#include <linux/delay.h>
+#include <ram.h>
+#include <reset.h>
+
+#include "starfive_ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct starfive_ddr_priv {
+ struct udevice *dev;
+ struct ram_info info;
+ void __iomem *ctrlreg;
+ void __iomem *phyreg;
+ struct reset_ctl_bulk rst;
+ struct clk clk;
+ u32 fre;
+};
+
+static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *priv)
+{
+ enum ddr_size_t size;
+
+ switch (priv->info.size) {
+ case SZ_2G:
+ size = DDR_SIZE_2G;
+ break;
+
+ case SZ_4G:
+ size = DDR_SIZE_4G;
+ break;
+
+ case 0x200000000:
+ size = DDR_SIZE_8G;
+ break;
+
+ case 0x400000000:
+ default:
+ pr_err("unsupport size %lx\n", priv->info.size);
+ return -EINVAL;
+ }
+
+ ddr_phy_train(priv->phyreg + (PHY_BASE_ADDR << 2));
+ ddr_phy_util(priv->phyreg + (PHY_AC_BASE_ADDR << 2));
+ ddr_phy_start(priv->phyreg, size);
+
+ DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
+ ddrcsr_boot(priv->ctrlreg, priv->ctrlreg + SEC_CTRL_ADDR,
+ priv->phyreg, size);
+
+ return 0;
+}
+
+static int starfive_ddr_probe(struct udevice *dev)
+{
+ struct starfive_ddr_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ u64 rate;
+ int ret;
+
+ /* Read memory base and size from DT */
+ fdtdec_setup_mem_size_base();
+ priv->info.base = gd->ram_base;
+ priv->info.size = gd->ram_size;
+
+ priv->dev = dev;
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->ctrlreg = (void __iomem *)addr;
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->phyreg = (void __iomem *)addr;
+ ret = dev_read_u32(dev, "clock-frequency", &priv->fre);
+ if (ret)
+ return ret;
+
+ switch (priv->fre) {
+ case 2133:
+ rate = 1066000000;
+ break;
+
+ case 2800:
+ rate = 1400000000;
+ break;
+
+ default:
+ pr_err("Unknown DDR frequency %d\n", priv->fre);
+ return -EINVAL;
+ };
+
+ ret = reset_get_bulk(dev, &priv->rst);
+ if (ret)
+ return ret;
+
+ ret = reset_deassert_bulk(&priv->rst);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret)
+ goto err_free_reset;
+
+ ret = clk_set_rate(&priv->clk, rate);
+ if (ret < 0)
+ goto err_free_reset;
+
+ ret = starfive_ddr_setup(dev, priv);
+ printf("DDR version: dc2e84f0.\n");
+
+ return ret;
+
+err_free_reset:
+ reset_release_bulk(&priv->rst);
+
+ return ret;
+}
+
+static int starfive_ddr_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct starfive_ddr_priv *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops starfive_ddr_ops = {
+ .get_info = starfive_ddr_get_info,
+};
+
+static const struct udevice_id starfive_ddr_ids[] = {
+ { .compatible = "starfive,jh7110-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(starfive_ddr) = {
+ .name = "starfive_ddr",
+ .id = UCLASS_RAM,
+ .of_match = starfive_ddr_ids,
+ .ops = &starfive_ddr_ops,
+ .probe = starfive_ddr_probe,
+ .priv_auto = sizeof(struct starfive_ddr_priv),
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#ifndef __STARFIVE_DDR_H__
+#define __STARFIVE_DDR_H__
+
+#define SEC_CTRL_ADDR 0x1000
+#define PHY_BASE_ADDR 0x800
+#define PHY_AC_BASE_ADDR 0x1000
+
+#define DDR_BUS_MASK GENMASK(29, 24)
+#define DDR_AXI_MASK BIT(31)
+#define DDR_BUS_OFFSET 0xAC
+#define DDR_AXI_OFFSET 0xB0
+
+#define DDR_BUS_OSC_DIV2 0
+#define DDR_BUS_PLL1_DIV2 1
+#define DDR_BUS_PLL1_DIV4 2
+#define DDR_BUS_PLL1_DIV8 3
+#define DDR_AXI_DISABLE 0
+#define DDR_AXI_ENABLE 1
+
+#define OFFSET_SEL BIT(31)
+#define REG2G BIT(30)
+#define REG4G BIT(29)
+#define REG8G BIT(28)
+#define F_ADDSET BIT(2)
+#define F_SET BIT(1)
+#define F_CLRSET BIT(0)
+#define REGALL (REG2G | REG4G | REG8G)
+#define REGSETALL (F_SET | REGALL)
+#define REGCLRSETALL (F_CLRSET | REGALL)
+#define REGADDSETALL (F_ADDSET | REGALL)
+
+struct ddr_reg_cfg {
+ u32 offset;
+ u32 mask;
+ u32 val;
+ u32 flag;
+};
+
+enum ddr_size_t {
+ DDR_SIZE_2G,
+ DDR_SIZE_4G,
+ DDR_SIZE_8G,
+ DDR_SIZE_16G,
+};
+
+void ddr_phy_train(u32 *phyreg);
+void ddr_phy_util(u32 *phyreg);
+void ddr_phy_start(u32 *phyreg, enum ddr_size_t size);
+void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size);
+
+#define DDR_REG_TRIGGER(addr, mask, value) \
+ out_le32((addr), (in_le32(addr) & (mask)) | (value))
+
+#define DDR_REG_SET(type, val) \
+ clrsetbits_le32(JH7110_SYS_CRG + DDR_##type##_OFFSET, \
+ DDR_##type##_MASK, \
+ ((val) << __ffs(DDR_##type##_MASK)) & DDR_##type##_MASK)
+
+#endif /*__STARFIVE_DDR_H__*/
if (next_step < 0)
return false;
- if (step < 0 || step > ARRAY_SIZE(step_str)) {
+ if (step < 0 || step >= ARRAY_SIZE(step_str)) {
printf("** step %d ** INVALID\n", step);
return false;
}
different hw blocks like DDR, gemgxl. With this driver we leverage
U-Boot's reset framework to reset these hardware blocks.
+config RESET_JH7110
+ bool "Reset driver for StarFive JH7110 SoC"
+ depends on DM_RESET && STARFIVE_JH7110
+ default y
+ help
+ Support for reset controller on StarFive
+ JH7110 SoCs.
+
+config SPL_RESET_JH7110
+ bool "SPL Reset driver for StarFive JH7110 SoC"
+ depends on SPL && STARFIVE_JH7110
+ default y
+ help
+ Support for reset controller on StarFive
+ JH7110 SoCs in SPL.
+
config RESET_SYSCON
bool "Enable generic syscon reset driver support"
depends on DM_RESET
obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
obj-$(CONFIG_RESET_AT91) += reset-at91.o
+obj-$(CONFIG_$(SPL_TPL_)RESET_JH7110) += reset-jh7110.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/ofnode.h>
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+#include <errno.h>
+#include <linux/iopoll.h>
+#include <reset-uclass.h>
+
+struct jh7110_reset_priv {
+ void __iomem *reg;
+ u32 assert;
+ u32 status;
+ u32 resets;
+};
+
+struct reset_info {
+ const char *compat;
+ const u32 nr_resets;
+ const u32 assert_offset;
+ const u32 status_offset;
+};
+
+static const struct reset_info jh7110_rst_info[] = {
+ {
+ .compat = "starfive,jh7110-syscrg",
+ .nr_resets = JH7110_SYSRST_END,
+ .assert_offset = 0x2F8,
+ .status_offset = 0x308,
+ },
+ {
+ .compat = "starfive,jh7110-aoncrg",
+ .nr_resets = JH7110_AONRST_END,
+ .assert_offset = 0x38,
+ .status_offset = 0x3C,
+ },
+ {
+ .compat = "starfive,jh7110-stgcrg",
+ .nr_resets = JH7110_STGRST_END,
+ .assert_offset = 0x74,
+ .status_offset = 0x78,
+ }
+};
+
+static const struct reset_info *jh7110_reset_get_cfg(const char *compat)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(jh7110_rst_info); i++)
+ if (!strcmp(compat, jh7110_rst_info[i].compat))
+ return &jh7110_rst_info[i];
+
+ return NULL;
+}
+
+static int jh7110_reset_trigger(struct jh7110_reset_priv *priv,
+ unsigned long id, bool assert)
+{
+ ulong group;
+ u32 mask, value, done = 0;
+ ulong addr;
+
+ group = id / 32;
+ mask = BIT(id % 32);
+
+ if (!assert)
+ done ^= mask;
+
+ addr = (ulong)priv->reg + priv->assert + group * sizeof(u32);
+ value = readl((ulong *)addr);
+
+ if (assert)
+ value |= mask;
+ else
+ value &= ~mask;
+
+ writel(value, (ulong *)addr);
+ addr = (ulong)priv->reg + priv->status + group * sizeof(u32);
+
+ return readl_poll_timeout((ulong *)addr, value,
+ (value & mask) == done, 1000);
+}
+
+static int jh7110_reset_assert(struct reset_ctl *rst)
+{
+ struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+ jh7110_reset_trigger(priv, rst->id, true);
+
+ return 0;
+}
+
+static int jh7110_reset_deassert(struct reset_ctl *rst)
+{
+ struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+ jh7110_reset_trigger(priv, rst->id, false);
+
+ return 0;
+}
+
+static int jh7110_reset_free(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int jh7110_reset_request(struct reset_ctl *rst)
+{
+ struct jh7110_reset_priv *priv = dev_get_priv(rst->dev);
+
+ if (rst->id >= priv->resets)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int jh7110_reset_probe(struct udevice *dev)
+{
+ struct jh7110_reset_priv *priv = dev_get_priv(dev);
+ const struct reset_info *cfg;
+ const char *compat;
+
+ compat = ofnode_get_property(dev_ofnode(dev), "compatible", NULL);
+ if (!compat)
+ return -EINVAL;
+
+ cfg = jh7110_reset_get_cfg(compat);
+ if (!cfg)
+ return -EINVAL;
+
+ priv->assert = cfg->assert_offset;
+ priv->status = cfg->status_offset;
+ priv->resets = cfg->nr_resets;
+ priv->reg = (void __iomem *)dev_read_addr_index(dev, 0);
+
+ return 0;
+}
+
+const struct reset_ops jh7110_reset_reset_ops = {
+ .rfree = jh7110_reset_free,
+ .request = jh7110_reset_request,
+ .rst_assert = jh7110_reset_assert,
+ .rst_deassert = jh7110_reset_deassert,
+};
+
+U_BOOT_DRIVER(jh7110_reset) = {
+ .name = "jh7110_reset",
+ .id = UCLASS_RESET,
+ .ops = &jh7110_reset_reset_ops,
+ .probe = jh7110_reset_probe,
+ .priv_auto = sizeof(struct jh7110_reset_priv),
+};
#define STM32_BUSY_TIMEOUT_US 100000
#define STM32_ABT_TIMEOUT_US 100000
-struct stm32_qspi_flash {
- u32 cr;
- u32 dcr;
- bool initialized;
-};
-
struct stm32_qspi_priv {
struct stm32_qspi_regs *regs;
- struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
void __iomem *mm_base;
resource_size_t mm_size;
ulong clock_rate;
return -ENODEV;
if (priv->cs_used != slave_cs) {
- struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
-
priv->cs_used = slave_cs;
- if (flash->initialized) {
- /* Set the configuration: speed + cs */
- writel(flash->cr, &priv->regs->cr);
- writel(flash->dcr, &priv->regs->dcr);
- } else {
- /* Set chip select */
- clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
- priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
-
- /* Save the configuration: speed + cs */
- flash->cr = readl(&priv->regs->cr);
- flash->dcr = readl(&priv->regs->dcr);
-
- flash->initialized = true;
- }
+ /* Set chip select */
+ clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
+ priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
}
setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
default 30000 if ARCH_SOCFPGA
default 16000 if ARCH_SUNXI
default 5376 if ULP_WATCHDOG
+ default 15000 if ARCH_BCM283X
default 60000
help
Watchdog timeout in msec
help
Enable support for the watchdog timer in Allwinner sunxi SoCs.
+config WDT_BCM2835
+ bool "Broadcom 2835 watchdog timer support"
+ depends on WDT && ARCH_BCM283X
+ default y
+ help
+ Enable support for the watchdog timer in Broadcom 283X SoCs such
+ as Raspberry Pi boards.
+
config XILINX_TB_WATCHDOG
bool "Xilinx Axi watchdog timer support"
depends on WDT
Intel Tangier SoC. If you're using a board with Intel Tangier
SoC, say Y here.
+config WDT_ARM_SMC
+ bool "ARM SMC watchdog timer support"
+ depends on WDT && ARM_SMCCC
+ imply WATCHDOG
+ help
+ Select this to enable Arm SMC watchdog timer. This watchdog will manage
+ a watchdog based on ARM SMCCC communication.
+
config SPL_WDT
bool "Enable driver model for watchdog timer drivers in SPL"
depends on SPL_DM
Enable driver model for watchdog timer in SPL.
This is similar to CONFIG_WDT in U-Boot.
+config WDT_FTWDT010
+ bool "Faraday Technology ftwdt010 watchdog timer support"
+ depends on WDT
+ imply WATCHDOG
+ help
+ Faraday Technology ftwdt010 watchdog is an architecture independent
+ watchdog. It is usually used in SoC chip design.
endmenu
obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
obj-$(CONFIG_WDT_ALARM_SANDBOX) += sandbox_alarm-wdt.o
obj-$(CONFIG_WDT_APPLE) += apple_wdt.o
+obj-$(CONFIG_WDT_ARM_SMC) += arm_smc_wdt.o
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
+obj-$(CONFIG_WDT_BCM2835) += bcm2835_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
+obj-$(CONFIG_WDT_FTWDT010) += ftwdt010_wdt.o
obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o
obj-$(CONFIG_WDT_MAX6370) += max6370_wdt.o
obj-$(CONFIG_WDT_MESON_GXBB) += meson_gxbb_wdt.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * ARM Secure Monitor Call watchdog driver
+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * This file is based on Linux driver drivers/watchdog/arm_smc_wdt.c
+ */
+
+#define LOG_CATEGORY UCLASS_WDT
+
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/arm-smccc.h>
+#include <linux/psci.h>
+#include <wdt.h>
+
+#define DRV_NAME "arm_smc_wdt"
+
+#define WDT_TIMEOUT_SECS(TIMEOUT) ((TIMEOUT) / 1000)
+
+enum smcwd_call {
+ SMCWD_INIT = 0,
+ SMCWD_SET_TIMEOUT = 1,
+ SMCWD_ENABLE = 2,
+ SMCWD_PET = 3,
+ SMCWD_GET_TIMELEFT = 4,
+};
+
+struct smcwd_priv_data {
+ u32 smc_id;
+ unsigned int min_timeout;
+ unsigned int max_timeout;
+};
+
+static int smcwd_call(struct udevice *dev, enum smcwd_call call,
+ unsigned long arg, struct arm_smccc_res *res)
+{
+ struct smcwd_priv_data *priv = dev_get_priv(dev);
+ struct arm_smccc_res local_res;
+
+ if (!res)
+ res = &local_res;
+
+ arm_smccc_smc(priv->smc_id, call, arg, 0, 0, 0, 0, 0, res);
+
+ if (res->a0 == PSCI_RET_NOT_SUPPORTED)
+ return -ENODEV;
+ if (res->a0 == PSCI_RET_INVALID_PARAMS)
+ return -EINVAL;
+ if (res->a0 != PSCI_RET_SUCCESS)
+ return -EIO;
+
+ return 0;
+}
+
+static int smcwd_reset(struct udevice *dev)
+{
+ return smcwd_call(dev, SMCWD_PET, 0, NULL);
+}
+
+static int smcwd_stop(struct udevice *dev)
+{
+ return smcwd_call(dev, SMCWD_ENABLE, 0, NULL);
+}
+
+static int smcwd_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ struct smcwd_priv_data *priv = dev_get_priv(dev);
+ u64 timeout_sec = WDT_TIMEOUT_SECS(timeout_ms);
+ int err;
+
+ if (timeout_sec < priv->min_timeout || timeout_sec > priv->max_timeout) {
+ dev_err(dev, "Timeout value not supported\n");
+ return -EINVAL;
+ }
+
+ err = smcwd_call(dev, SMCWD_SET_TIMEOUT, timeout_sec, NULL);
+ if (err) {
+ dev_err(dev, "Timeout out configuration failed\n");
+ return err;
+ }
+
+ return smcwd_call(dev, SMCWD_ENABLE, 1, NULL);
+}
+
+static int smcwd_probe(struct udevice *dev)
+{
+ struct smcwd_priv_data *priv = dev_get_priv(dev);
+ struct arm_smccc_res res;
+ int err;
+
+ priv->smc_id = dev_read_u32_default(dev, "arm,smc-id", 0x82003D06);
+
+ err = smcwd_call(dev, SMCWD_INIT, 0, &res);
+ if (err < 0) {
+ dev_err(dev, "Init failed %i\n", err);
+ return err;
+ }
+
+ priv->min_timeout = res.a1;
+ priv->max_timeout = res.a2;
+
+ return 0;
+}
+
+static const struct wdt_ops smcwd_ops = {
+ .start = smcwd_start,
+ .stop = smcwd_stop,
+ .reset = smcwd_reset,
+};
+
+static const struct udevice_id smcwd_dt_ids[] = {
+ { .compatible = "arm,smc-wdt" },
+ {}
+};
+
+U_BOOT_DRIVER(wdt_sandbox) = {
+ .name = "smcwd",
+ .id = UCLASS_WDT,
+ .of_match = smcwd_dt_ids,
+ .priv_auto = sizeof(struct smcwd_priv_data),
+ .probe = smcwd_probe,
+ .ops = &smcwd_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 Lubomir Rintel <lkundrak@v3.sk>
+ * Copyright (C) 2023 Etienne Dublé (CNRS) <etienne.duble@imag.fr>
+ *
+ * This code is mostly derived from the linux driver.
+ */
+
+#include <dm.h>
+#include <wdt.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+#define PM_RSTC 0x1c
+#define PM_WDOG 0x24
+
+#define PM_PASSWORD 0x5a000000
+
+/* The hardware supports a maximum timeout value of 0xfffff ticks
+ * (just below 16 seconds).
+ */
+#define PM_WDOG_MAX_TICKS 0x000fffff
+#define PM_RSTC_WRCFG_CLR 0xffffffcf
+#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
+#define PM_RSTC_RESET 0x00000102
+
+#define MS_TO_WDOG_TICKS(x) (((x) << 16) / 1000)
+
+struct bcm2835_wdt_priv {
+ void __iomem *base;
+ u64 timeout_ticks;
+};
+
+static int bcm2835_wdt_start_ticks(struct udevice *dev,
+ u64 timeout_ticks, ulong flags)
+{
+ struct bcm2835_wdt_priv *priv = dev_get_priv(dev);
+ void __iomem *base = priv->base;
+ u32 cur;
+
+ writel(PM_PASSWORD | timeout_ticks, base + PM_WDOG);
+ cur = readl(base + PM_RSTC);
+ writel(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET,
+ base + PM_RSTC);
+
+ return 0;
+}
+
+static int bcm2835_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ struct bcm2835_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->timeout_ticks = MS_TO_WDOG_TICKS(timeout_ms);
+
+ if (priv->timeout_ticks > PM_WDOG_MAX_TICKS) {
+ printf("bcm2835_wdt: the timeout value is too high, using ~16s instead.\n");
+ priv->timeout_ticks = PM_WDOG_MAX_TICKS;
+ }
+
+ return bcm2835_wdt_start_ticks(dev, priv->timeout_ticks, flags);
+}
+
+static int bcm2835_wdt_reset(struct udevice *dev)
+{
+ struct bcm2835_wdt_priv *priv = dev_get_priv(dev);
+
+ /* restart the timer with the value of priv->timeout_ticks
+ * saved from the last bcm2835_wdt_start() call.
+ */
+ return bcm2835_wdt_start_ticks(dev, priv->timeout_ticks, 0);
+}
+
+static int bcm2835_wdt_stop(struct udevice *dev)
+{
+ struct bcm2835_wdt_priv *priv = dev_get_priv(dev);
+ void __iomem *base = priv->base;
+
+ writel(PM_PASSWORD | PM_RSTC_RESET, base + PM_RSTC);
+
+ return 0;
+}
+
+static int bcm2835_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ int ret;
+
+ /* use a timeout of 10 ticks (~150us) */
+ ret = bcm2835_wdt_start_ticks(dev, 10, flags);
+ if (ret)
+ return ret;
+
+ mdelay(500);
+
+ return 0;
+}
+
+static const struct wdt_ops bcm2835_wdt_ops = {
+ .reset = bcm2835_wdt_reset,
+ .start = bcm2835_wdt_start,
+ .stop = bcm2835_wdt_stop,
+ .expire_now = bcm2835_wdt_expire_now,
+};
+
+static const struct udevice_id bcm2835_wdt_ids[] = {
+ { .compatible = "brcm,bcm2835-pm" },
+ { .compatible = "brcm,bcm2835-pm-wdt" },
+ { /* sentinel */ }
+};
+
+static int bcm2835_wdt_probe(struct udevice *dev)
+{
+ struct bcm2835_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_remap_addr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ priv->timeout_ticks = PM_WDOG_MAX_TICKS;
+
+ bcm2835_wdt_stop(dev);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(bcm2835_wdt) = {
+ .name = "bcm2835_wdt",
+ .id = UCLASS_WDT,
+ .of_match = bcm2835_wdt_ids,
+ .probe = bcm2835_wdt_probe,
+ .priv_auto = sizeof(struct bcm2835_wdt_priv),
+ .ops = &bcm2835_wdt_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Watchdog driver for the FTWDT010 Watch Dog Driver
+ *
+ * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com)
+ * Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu>
+ * Based on SoftDog driver by Alan Cox <alan@redhat.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * 27/11/2004 Initial release, Faraday.
+ * 12/01/2011 Port to u-boot, Macpaul Lin.
+ * 22/08/2022 Port to DM
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <wdt.h>
+#include <log.h>
+#include <asm/io.h>
+#include <faraday/ftwdt010_wdt.h>
+
+struct ftwdt010_wdt_priv {
+ struct ftwdt010_wdt __iomem *regs;
+};
+
+/*
+ * Set the watchdog time interval.
+ * Counter is 32 bit.
+ */
+static int ftwdt010_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
+ struct ftwdt010_wdt *wd = priv->regs;
+ unsigned int reg;
+
+ debug("Activating WDT %llu ms\n", timeout_ms);
+
+ /* Check if disabled */
+ if (readl(&wd->wdcr) & ~FTWDT010_WDCR_ENABLE) {
+ printf("sorry, watchdog is disabled\n");
+ return -1;
+ }
+
+ /*
+ * In a 66MHz system,
+ * if you set WDLOAD as 0x03EF1480 (66000000)
+ * the reset timer is 1 second.
+ */
+ reg = FTWDT010_WDLOAD(timeout_ms * FTWDT010_TIMEOUT_FACTOR);
+
+ writel(reg, &wd->wdload);
+
+ return 0;
+}
+
+static int ftwdt010_wdt_reset(struct udevice *dev)
+{
+ struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
+ struct ftwdt010_wdt *wd = priv->regs;
+
+ /* clear control register */
+ writel(0, &wd->wdcr);
+
+ /* Write Magic number */
+ writel(FTWDT010_WDRESTART_MAGIC, &wd->wdrestart);
+
+ /* Enable WDT */
+ writel((FTWDT010_WDCR_RST | FTWDT010_WDCR_ENABLE), &wd->wdcr);
+
+ return 0;
+}
+
+static int ftwdt010_wdt_stop(struct udevice *dev)
+{
+ struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
+ struct ftwdt010_wdt *wd = priv->regs;
+
+ debug("Deactivating WDT..\n");
+
+ /*
+ * It was defined with CONFIG_WATCHDOG_NOWAYOUT in Linux
+ *
+ * Shut off the timer.
+ * Lock it in if it's a module and we defined ...NOWAYOUT
+ */
+ writel(0, &wd->wdcr);
+ return 0;
+}
+
+static int ftwdt010_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
+ struct ftwdt010_wdt *wd = priv->regs;
+
+ debug("Expiring WDT..\n");
+ writel(FTWDT010_WDLOAD(0), &wd->wdload);
+ return ftwdt010_wdt_reset(dev);
+}
+
+static int ftwdt010_wdt_probe(struct udevice *dev)
+{
+ struct ftwdt010_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->regs = dev_read_addr_ptr(dev);
+ if (!priv->regs)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct wdt_ops ftwdt010_wdt_ops = {
+ .start = ftwdt010_wdt_start,
+ .reset = ftwdt010_wdt_reset,
+ .stop = ftwdt010_wdt_stop,
+ .expire_now = ftwdt010_wdt_expire_now,
+};
+
+static const struct udevice_id ftwdt010_wdt_ids[] = {
+ { .compatible = "faraday,ftwdt010" },
+ {}
+};
+
+U_BOOT_DRIVER(ftwdt010_wdt) = {
+ .name = "ftwdt010_wdt",
+ .id = UCLASS_WDT,
+ .of_match = ftwdt010_wdt_ids,
+ .ops = &ftwdt010_wdt_ops,
+ .probe = ftwdt010_wdt_probe,
+ .priv_auto = sizeof(struct ftwdt010_wdt_priv),
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ *
+ */
+
+#ifndef _STARFIVE_VISIONFIVE2_H
+#define _STARFIVE_VISIONFIVE2_H
+
+#define RISCV_MMODE_TIMERBASE 0x2000000
+#define RISCV_MMODE_TIMER_FREQ 4000000
+#define RISCV_SMODE_TIMER_FREQ 4000000
+
+#define __io
+
+/* Environment options */
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define TYPE_GUID_SPL "2E54B353-1271-4842-806F-E436D6AF6985"
+#define TYPE_GUID_UBOOT "BC13C2FF-59E6-4262-A352-B275FD6F7172"
+#define TYPE_GUID_SYSTEM "EBD0A0A2-B9E5-4433-87C0-68B6B72699C7"
+
+#define PARTS_DEFAULT \
+ "name=spl,start=2M,size=2M,type=${type_guid_gpt_loader1};" \
+ "name=uboot,size=4MB,type=${type_guid_gpt_loader2};" \
+ "name=system,size=-,bootable,type=${type_guid_gpt_system};"
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x40200000\0" \
+ "kernel_comp_addr_r=0x88000000\0" \
+ "kernel_comp_size=0x4000000\0" \
+ "fdt_addr_r=0x46000000\0" \
+ "scriptaddr=0x43900000\0" \
+ "pxefile_addr_r=0x45900000\0" \
+ "ramdisk_addr_r=0x46100000\0" \
+ "type_guid_gpt_loader1=" TYPE_GUID_SPL "\0" \
+ "type_guid_gpt_loader2=" TYPE_GUID_UBOOT "\0" \
+ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
+ "partitions=" PARTS_DEFAULT "\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ BOOTENV
+
+#endif /* _STARFIVE_VISIONFIVE2_H */
#define __CONFIG_STM32MP13_ST_COMMON_H__
#define STM32MP_BOARD_EXTRA_ENV \
- "usb_pgood_delay=1000\0" \
+ "usb_pgood_delay=2000\0" \
"console=ttySTM0\0"
#include <configs/stm32mp13_common.h>
#define __CONFIG_STM32MP15_ST_COMMON_H__
#define STM32MP_BOARD_EXTRA_ENV \
+ "usb_pgood_delay=2000\0" \
"console=ttySTM0\0"
#include <configs/stm32mp15_common.h>
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
+
+#define JH7110_SYSCLK_CPU_ROOT 0
+#define JH7110_SYSCLK_CPU_CORE 1
+#define JH7110_SYSCLK_CPU_BUS 2
+#define JH7110_SYSCLK_GPU_ROOT 3
+#define JH7110_SYSCLK_PERH_ROOT 4
+#define JH7110_SYSCLK_BUS_ROOT 5
+#define JH7110_SYSCLK_NOCSTG_BUS 6
+#define JH7110_SYSCLK_AXI_CFG0 7
+#define JH7110_SYSCLK_STG_AXIAHB 8
+#define JH7110_SYSCLK_AHB0 9
+#define JH7110_SYSCLK_AHB1 10
+#define JH7110_SYSCLK_APB_BUS 11
+#define JH7110_SYSCLK_APB0 12
+#define JH7110_SYSCLK_PLL0_DIV2 13
+#define JH7110_SYSCLK_PLL1_DIV2 14
+#define JH7110_SYSCLK_PLL2_DIV2 15
+#define JH7110_SYSCLK_AUDIO_ROOT 16
+#define JH7110_SYSCLK_MCLK_INNER 17
+#define JH7110_SYSCLK_MCLK 18
+#define JH7110_SYSCLK_MCLK_OUT 19
+#define JH7110_SYSCLK_ISP_2X 20
+#define JH7110_SYSCLK_ISP_AXI 21
+#define JH7110_SYSCLK_GCLK0 22
+#define JH7110_SYSCLK_GCLK1 23
+#define JH7110_SYSCLK_GCLK2 24
+#define JH7110_SYSCLK_CORE 25
+#define JH7110_SYSCLK_CORE1 26
+#define JH7110_SYSCLK_CORE2 27
+#define JH7110_SYSCLK_CORE3 28
+#define JH7110_SYSCLK_CORE4 29
+#define JH7110_SYSCLK_DEBUG 30
+#define JH7110_SYSCLK_RTC_TOGGLE 31
+#define JH7110_SYSCLK_TRACE0 32
+#define JH7110_SYSCLK_TRACE1 33
+#define JH7110_SYSCLK_TRACE2 34
+#define JH7110_SYSCLK_TRACE3 35
+#define JH7110_SYSCLK_TRACE4 36
+#define JH7110_SYSCLK_TRACE_COM 37
+#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38
+#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39
+#define JH7110_SYSCLK_OSC_DIV2 40
+#define JH7110_SYSCLK_PLL1_DIV4 41
+#define JH7110_SYSCLK_PLL1_DIV8 42
+#define JH7110_SYSCLK_DDR_BUS 43
+#define JH7110_SYSCLK_DDR_AXI 44
+#define JH7110_SYSCLK_GPU_CORE 45
+#define JH7110_SYSCLK_GPU_CORE_CLK 46
+#define JH7110_SYSCLK_GPU_SYS_CLK 47
+#define JH7110_SYSCLK_GPU_APB 48
+#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49
+#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50
+#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51
+#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52
+#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53
+#define JH7110_SYSCLK_HIFI4_CORE 54
+#define JH7110_SYSCLK_HIFI4_AXI 55
+#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56
+#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57
+#define JH7110_SYSCLK_VOUT_SRC 58
+#define JH7110_SYSCLK_VOUT_AXI 59
+#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60
+#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61
+#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62
+#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63
+#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64
+#define JH7110_SYSCLK_JPEGC_AXI 65
+#define JH7110_SYSCLK_CODAJ12_AXI 66
+#define JH7110_SYSCLK_CODAJ12_CORE 67
+#define JH7110_SYSCLK_CODAJ12_APB 68
+#define JH7110_SYSCLK_VDEC_AXI 69
+#define JH7110_SYSCLK_WAVE511_AXI 70
+#define JH7110_SYSCLK_WAVE511_BPU 71
+#define JH7110_SYSCLK_WAVE511_VCE 72
+#define JH7110_SYSCLK_WAVE511_APB 73
+#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74
+#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75
+#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76
+#define JH7110_SYSCLK_VENC_AXI 77
+#define JH7110_SYSCLK_WAVE420L_AXI 78
+#define JH7110_SYSCLK_WAVE420L_BPU 79
+#define JH7110_SYSCLK_WAVE420L_VCE 80
+#define JH7110_SYSCLK_WAVE420L_APB 81
+#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82
+#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83
+#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84
+#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85
+#define JH7110_SYSCLK_AXIMEM2_AXI 86
+#define JH7110_SYSCLK_QSPI_AHB 87
+#define JH7110_SYSCLK_QSPI_APB 88
+#define JH7110_SYSCLK_QSPI_REF_SRC 89
+#define JH7110_SYSCLK_QSPI_REF 90
+#define JH7110_SYSCLK_SDIO0_AHB 91
+#define JH7110_SYSCLK_SDIO1_AHB 92
+#define JH7110_SYSCLK_SDIO0_SDCARD 93
+#define JH7110_SYSCLK_SDIO1_SDCARD 94
+#define JH7110_SYSCLK_USB_125M 95
+#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96
+#define JH7110_SYSCLK_GMAC1_AHB 97
+#define JH7110_SYSCLK_GMAC1_AXI 98
+#define JH7110_SYSCLK_GMAC_SRC 99
+#define JH7110_SYSCLK_GMAC1_GTXCLK 100
+#define JH7110_SYSCLK_GMAC1_RMII_RTX 101
+#define JH7110_SYSCLK_GMAC1_PTP 102
+#define JH7110_SYSCLK_GMAC1_RX 103
+#define JH7110_SYSCLK_GMAC1_RX_INV 104
+#define JH7110_SYSCLK_GMAC1_TX 105
+#define JH7110_SYSCLK_GMAC1_TX_INV 106
+#define JH7110_SYSCLK_GMAC1_GTXC 107
+#define JH7110_SYSCLK_GMAC0_GTXCLK 108
+#define JH7110_SYSCLK_GMAC0_PTP 109
+#define JH7110_SYSCLK_GMAC_PHY 110
+#define JH7110_SYSCLK_GMAC0_GTXC 111
+#define JH7110_SYSCLK_IOMUX_APB 112
+#define JH7110_SYSCLK_MAILBOX 113
+#define JH7110_SYSCLK_INT_CTRL_APB 114
+#define JH7110_SYSCLK_CAN0_APB 115
+#define JH7110_SYSCLK_CAN0_TIMER 116
+#define JH7110_SYSCLK_CAN0_CAN 117
+#define JH7110_SYSCLK_CAN1_APB 118
+#define JH7110_SYSCLK_CAN1_TIMER 119
+#define JH7110_SYSCLK_CAN1_CAN 120
+#define JH7110_SYSCLK_PWM_APB 121
+#define JH7110_SYSCLK_WDT_APB 122
+#define JH7110_SYSCLK_WDT_CORE 123
+#define JH7110_SYSCLK_TIMER_APB 124
+#define JH7110_SYSCLK_TIMER0 125
+#define JH7110_SYSCLK_TIMER1 126
+#define JH7110_SYSCLK_TIMER2 127
+#define JH7110_SYSCLK_TIMER3 128
+#define JH7110_SYSCLK_TEMP_APB 129
+#define JH7110_SYSCLK_TEMP_CORE 130
+#define JH7110_SYSCLK_SPI0_APB 131
+#define JH7110_SYSCLK_SPI1_APB 132
+#define JH7110_SYSCLK_SPI2_APB 133
+#define JH7110_SYSCLK_SPI3_APB 134
+#define JH7110_SYSCLK_SPI4_APB 135
+#define JH7110_SYSCLK_SPI5_APB 136
+#define JH7110_SYSCLK_SPI6_APB 137
+#define JH7110_SYSCLK_I2C0_APB 138
+#define JH7110_SYSCLK_I2C1_APB 139
+#define JH7110_SYSCLK_I2C2_APB 140
+#define JH7110_SYSCLK_I2C3_APB 141
+#define JH7110_SYSCLK_I2C4_APB 142
+#define JH7110_SYSCLK_I2C5_APB 143
+#define JH7110_SYSCLK_I2C6_APB 144
+#define JH7110_SYSCLK_UART0_APB 145
+#define JH7110_SYSCLK_UART0_CORE 146
+#define JH7110_SYSCLK_UART1_APB 147
+#define JH7110_SYSCLK_UART1_CORE 148
+#define JH7110_SYSCLK_UART2_APB 149
+#define JH7110_SYSCLK_UART2_CORE 150
+#define JH7110_SYSCLK_UART3_APB 151
+#define JH7110_SYSCLK_UART3_CORE 152
+#define JH7110_SYSCLK_UART4_APB 153
+#define JH7110_SYSCLK_UART4_CORE 154
+#define JH7110_SYSCLK_UART5_APB 155
+#define JH7110_SYSCLK_UART5_CORE 156
+#define JH7110_SYSCLK_PWMDAC_APB 157
+#define JH7110_SYSCLK_PWMDAC_CORE 158
+#define JH7110_SYSCLK_SPDIF_APB 159
+#define JH7110_SYSCLK_SPDIF_CORE 160
+#define JH7110_SYSCLK_I2STX0_APB 161
+#define JH7110_SYSCLK_I2STX0_BCLK_MST 162
+#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163
+#define JH7110_SYSCLK_I2STX0_LRCK_MST 164
+#define JH7110_SYSCLK_I2STX0_BCLK 165
+#define JH7110_SYSCLK_I2STX0_BCLK_INV 166
+#define JH7110_SYSCLK_I2STX0_LRCK 167
+#define JH7110_SYSCLK_I2STX1_APB 168
+#define JH7110_SYSCLK_I2STX1_BCLK_MST 169
+#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170
+#define JH7110_SYSCLK_I2STX1_LRCK_MST 171
+#define JH7110_SYSCLK_I2STX1_BCLK 172
+#define JH7110_SYSCLK_I2STX1_BCLK_INV 173
+#define JH7110_SYSCLK_I2STX1_LRCK 174
+#define JH7110_SYSCLK_I2SRX_APB 175
+#define JH7110_SYSCLK_I2SRX_BCLK_MST 176
+#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177
+#define JH7110_SYSCLK_I2SRX_LRCK_MST 178
+#define JH7110_SYSCLK_I2SRX_BCLK 179
+#define JH7110_SYSCLK_I2SRX_BCLK_INV 180
+#define JH7110_SYSCLK_I2SRX_LRCK 181
+#define JH7110_SYSCLK_PDM_DMIC 182
+#define JH7110_SYSCLK_PDM_APB 183
+#define JH7110_SYSCLK_TDM_AHB 184
+#define JH7110_SYSCLK_TDM_APB 185
+#define JH7110_SYSCLK_TDM_INTERNAL 186
+#define JH7110_SYSCLK_TDM_CLK_TDM 187
+#define JH7110_SYSCLK_TDM_CLK_TDM_N 188
+#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
+
+#define JH7110_SYSCLK_PLL0_OUT 190
+#define JH7110_SYSCLK_PLL1_OUT 191
+#define JH7110_SYSCLK_PLL2_OUT 192
+
+#define JH7110_SYSCLK_END 193
+
+#define JH7110_AONCLK_OSC_DIV4 (JH7110_SYSCLK_END + 0)
+#define JH7110_AONCLK_APB_FUNC (JH7110_SYSCLK_END + 1)
+#define JH7110_AONCLK_GMAC0_AHB (JH7110_SYSCLK_END + 2)
+#define JH7110_AONCLK_GMAC0_AXI (JH7110_SYSCLK_END + 3)
+#define JH7110_AONCLK_GMAC0_RMII_RTX (JH7110_SYSCLK_END + 4)
+#define JH7110_AONCLK_GMAC0_TX (JH7110_SYSCLK_END + 5)
+#define JH7110_AONCLK_GMAC0_TX_INV (JH7110_SYSCLK_END + 6)
+#define JH7110_AONCLK_GMAC0_RX (JH7110_SYSCLK_END + 7)
+#define JH7110_AONCLK_GMAC0_RX_INV (JH7110_SYSCLK_END + 8)
+#define JH7110_AONCLK_OTPC_APB (JH7110_SYSCLK_END + 9)
+#define JH7110_AONCLK_RTC_APB (JH7110_SYSCLK_END + 10)
+#define JH7110_AONCLK_RTC_INTERNAL (JH7110_SYSCLK_END + 11)
+#define JH7110_AONCLK_RTC_32K (JH7110_SYSCLK_END + 12)
+#define JH7110_AONCLK_RTC_CAL (JH7110_SYSCLK_END + 13)
+
+#define JH7110_AONCLK_END (JH7110_SYSCLK_END + 14)
+
+#define JH7110_STGCLK_HIFI4_CORE (JH7110_AONCLK_END + 0)
+#define JH7110_STGCLK_USB_APB (JH7110_AONCLK_END + 1)
+#define JH7110_STGCLK_USB_UTMI_APB (JH7110_AONCLK_END + 2)
+#define JH7110_STGCLK_USB_AXI (JH7110_AONCLK_END + 3)
+#define JH7110_STGCLK_USB_LPM (JH7110_AONCLK_END + 4)
+#define JH7110_STGCLK_USB_STB (JH7110_AONCLK_END + 5)
+#define JH7110_STGCLK_USB_APP_125 (JH7110_AONCLK_END + 6)
+#define JH7110_STGCLK_USB_REFCLK (JH7110_AONCLK_END + 7)
+#define JH7110_STGCLK_PCIE0_AXI (JH7110_AONCLK_END + 8)
+#define JH7110_STGCLK_PCIE0_APB (JH7110_AONCLK_END + 9)
+#define JH7110_STGCLK_PCIE0_TL (JH7110_AONCLK_END + 10)
+#define JH7110_STGCLK_PCIE1_AXI (JH7110_AONCLK_END + 11)
+#define JH7110_STGCLK_PCIE1_APB (JH7110_AONCLK_END + 12)
+#define JH7110_STGCLK_PCIE1_TL (JH7110_AONCLK_END + 13)
+#define JH7110_STGCLK_PCIE01_MAIN (JH7110_AONCLK_END + 14)
+#define JH7110_STGCLK_SEC_HCLK (JH7110_AONCLK_END + 15)
+#define JH7110_STGCLK_SEC_MISCAHB (JH7110_AONCLK_END + 16)
+#define JH7110_STGCLK_MTRX_GRP0_MAIN (JH7110_AONCLK_END + 17)
+#define JH7110_STGCLK_MTRX_GRP0_BUS (JH7110_AONCLK_END + 18)
+#define JH7110_STGCLK_MTRX_GRP0_STG (JH7110_AONCLK_END + 19)
+#define JH7110_STGCLK_MTRX_GRP1_MAIN (JH7110_AONCLK_END + 20)
+#define JH7110_STGCLK_MTRX_GRP1_BUS (JH7110_AONCLK_END + 21)
+#define JH7110_STGCLK_MTRX_GRP1_STG (JH7110_AONCLK_END + 22)
+#define JH7110_STGCLK_MTRX_GRP1_HIFI (JH7110_AONCLK_END + 23)
+#define JH7110_STGCLK_E2_RTC (JH7110_AONCLK_END + 24)
+#define JH7110_STGCLK_E2_CORE (JH7110_AONCLK_END + 25)
+#define JH7110_STGCLK_E2_DBG (JH7110_AONCLK_END + 26)
+#define JH7110_STGCLK_DMA1P_AXI (JH7110_AONCLK_END + 27)
+#define JH7110_STGCLK_DMA1P_AHB (JH7110_AONCLK_END + 28)
+
+#define JH7110_STGCLK_END (JH7110_AONCLK_END + 29)
+
+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+
+/*
+ * mux bits:
+ * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
+ * | din | dout | doen | function | gpio nr |
+ *
+ * dout: output signal
+ * doen: output enable signal
+ * din: optional input signal, 0xff = none
+ * function:
+ * gpio nr: gpio number, 0 - 63
+ */
+#define GPIOMUX(n, dout, doen, din) ( \
+ (((din) & 0xff) << 24) | \
+ (((dout) & 0xff) << 16) | \
+ (((doen) & 0x3f) << 10) | \
+ ((n) & 0x3f))
+
+#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff))
+
+/* sys_iomux pin */
+#define PAD_GPIO0 0
+#define PAD_GPIO1 1
+#define PAD_GPIO2 2
+#define PAD_GPIO3 3
+#define PAD_GPIO4 4
+#define PAD_GPIO5 5
+#define PAD_GPIO6 6
+#define PAD_GPIO7 7
+#define PAD_GPIO8 8
+#define PAD_GPIO9 9
+#define PAD_GPIO10 10
+#define PAD_GPIO11 11
+#define PAD_GPIO12 12
+#define PAD_GPIO13 13
+#define PAD_GPIO14 14
+#define PAD_GPIO15 15
+#define PAD_GPIO16 16
+#define PAD_GPIO17 17
+#define PAD_GPIO18 18
+#define PAD_GPIO19 19
+#define PAD_GPIO20 20
+#define PAD_GPIO21 21
+#define PAD_GPIO22 22
+#define PAD_GPIO23 23
+#define PAD_GPIO24 24
+#define PAD_GPIO25 25
+#define PAD_GPIO26 26
+#define PAD_GPIO27 27
+#define PAD_GPIO28 28
+#define PAD_GPIO29 29
+#define PAD_GPIO30 30
+#define PAD_GPIO31 31
+#define PAD_GPIO32 32
+#define PAD_GPIO33 33
+#define PAD_GPIO34 34
+#define PAD_GPIO35 35
+#define PAD_GPIO36 36
+#define PAD_GPIO37 37
+#define PAD_GPIO38 38
+#define PAD_GPIO39 39
+#define PAD_GPIO40 40
+#define PAD_GPIO41 41
+#define PAD_GPIO42 42
+#define PAD_GPIO43 43
+#define PAD_GPIO44 44
+#define PAD_GPIO45 45
+#define PAD_GPIO46 46
+#define PAD_GPIO47 47
+#define PAD_GPIO48 48
+#define PAD_GPIO49 49
+#define PAD_GPIO50 50
+#define PAD_GPIO51 51
+#define PAD_GPIO52 52
+#define PAD_GPIO53 53
+#define PAD_GPIO54 54
+#define PAD_GPIO55 55
+#define PAD_GPIO56 56
+#define PAD_GPIO57 57
+#define PAD_GPIO58 58
+#define PAD_GPIO59 59
+#define PAD_GPIO60 60
+#define PAD_GPIO61 61
+#define PAD_GPIO62 62
+#define PAD_GPIO63 63
+#define PAD_SD0_CLK 64
+#define PAD_SD0_CMD 65
+#define PAD_SD0_DATA0 66
+#define PAD_SD0_DATA1 67
+#define PAD_SD0_DATA2 68
+#define PAD_SD0_DATA3 69
+#define PAD_SD0_DATA4 70
+#define PAD_SD0_DATA5 71
+#define PAD_SD0_DATA6 72
+#define PAD_SD0_DATA7 73
+#define PAD_SD0_STRB 74
+#define PAD_GMAC1_MDC 75
+#define PAD_GMAC1_MDIO 76
+#define PAD_GMAC1_RXD0 77
+#define PAD_GMAC1_RXD1 78
+#define PAD_GMAC1_RXD2 79
+#define PAD_GMAC1_RXD3 80
+#define PAD_GMAC1_RXDV 81
+#define PAD_GMAC1_RXC 82
+#define PAD_GMAC1_TXD0 83
+#define PAD_GMAC1_TXD1 84
+#define PAD_GMAC1_TXD2 85
+#define PAD_GMAC1_TXD3 86
+#define PAD_GMAC1_TXEN 87
+#define PAD_GMAC1_TXC 88
+#define PAD_QSPI_SCLK 89
+#define PAD_QSPI_CS0 90
+#define PAD_QSPI_DATA0 91
+#define PAD_QSPI_DATA1 92
+#define PAD_QSPI_DATA2 93
+#define PAD_QSPI_DATA3 94
+
+/* aon_iomux pin */
+#define PAD_TESTEN 0
+#define PAD_RGPIO0 1
+#define PAD_RGPIO1 2
+#define PAD_RGPIO2 3
+#define PAD_RGPIO3 4
+#define PAD_RSTN 5
+#define PAD_GMAC0_MDC 6
+#define PAD_GMAC0_MDIO 7
+#define PAD_GMAC0_RXD0 8
+#define PAD_GMAC0_RXD1 9
+#define PAD_GMAC0_RXD2 10
+#define PAD_GMAC0_RXD3 11
+#define PAD_GMAC0_RXDV 12
+#define PAD_GMAC0_RXC 13
+#define PAD_GMAC0_TXD0 14
+#define PAD_GMAC0_TXD1 15
+#define PAD_GMAC0_TXD2 16
+#define PAD_GMAC0_TXD3 17
+#define PAD_GMAC0_TXEN 18
+#define PAD_GMAC0_TXC 19
+
+/* sys_iomux dout */
+#define GPOUT_LOW 0
+#define GPOUT_HIGH 1
+#define GPOUT_SYS_WAVE511_UART_TX 2
+#define GPOUT_SYS_CAN0_STBY 3
+#define GPOUT_SYS_CAN0_TST_NEXT_BIT 4
+#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 5
+#define GPOUT_SYS_CAN0_TXD 6
+#define GPOUT_SYS_USB_DRIVE_VBUS 7
+#define GPOUT_SYS_QSPI_CS1 8
+#define GPOUT_SYS_SPDIF 9
+#define GPOUT_SYS_HDMI_CEC_SDA 10
+#define GPOUT_SYS_HDMI_DDC_SCL 11
+#define GPOUT_SYS_HDMI_DDC_SDA 12
+#define GPOUT_SYS_WATCHDOG 13
+#define GPOUT_SYS_I2C0_CLK 14
+#define GPOUT_SYS_I2C0_DATA 15
+#define GPOUT_SYS_SDIO0_BACK_END_POWER 16
+#define GPOUT_SYS_SDIO0_CARD_POWER_EN 17
+#define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN 18
+#define GPOUT_SYS_SDIO0_RST 19
+#define GPOUT_SYS_UART0_TX 20
+#define GPOUT_SYS_HIFI4_JTAG_TDO 21
+#define GPOUT_SYS_JTAG_TDO 22
+#define GPOUT_SYS_PDM_MCLK 23
+#define GPOUT_SYS_PWM_CHANNEL0 24
+#define GPOUT_SYS_PWM_CHANNEL1 25
+#define GPOUT_SYS_PWM_CHANNEL2 26
+#define GPOUT_SYS_PWM_CHANNEL3 27
+#define GPOUT_SYS_PWMDAC_LEFT 28
+#define GPOUT_SYS_PWMDAC_RIGHT 29
+#define GPOUT_SYS_SPI0_CLK 30
+#define GPOUT_SYS_SPI0_FSS 31
+#define GPOUT_SYS_SPI0_TXD 32
+#define GPOUT_SYS_GMAC_PHYCLK 33
+#define GPOUT_SYS_I2SRX_BCLK 34
+#define GPOUT_SYS_I2SRX_LRCK 35
+#define GPOUT_SYS_I2STX0_BCLK 36
+#define GPOUT_SYS_I2STX0_LRCK 37
+#define GPOUT_SYS_MCLK 38
+#define GPOUT_SYS_TDM_CLK 39
+#define GPOUT_SYS_TDM_SYNC 40
+#define GPOUT_SYS_TDM_TXD 41
+#define GPOUT_SYS_TRACE_DATA0 42
+#define GPOUT_SYS_TRACE_DATA1 43
+#define GPOUT_SYS_TRACE_DATA2 44
+#define GPOUT_SYS_TRACE_DATA3 45
+#define GPOUT_SYS_TRACE_REF 46
+#define GPOUT_SYS_CAN1_STBY 47
+#define GPOUT_SYS_CAN1_TST_NEXT_BIT 48
+#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 49
+#define GPOUT_SYS_CAN1_TXD 50
+#define GPOUT_SYS_I2C1_CLK 51
+#define GPOUT_SYS_I2C1_DATA 52
+#define GPOUT_SYS_SDIO1_BACK_END_POWER 53
+#define GPOUT_SYS_SDIO1_CARD_POWER_EN 54
+#define GPOUT_SYS_SDIO1_CLK 55
+#define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN 56
+#define GPOUT_SYS_SDIO1_CMD 57
+#define GPOUT_SYS_SDIO1_DATA0 58
+#define GPOUT_SYS_SDIO1_DATA1 59
+#define GPOUT_SYS_SDIO1_DATA2 60
+#define GPOUT_SYS_SDIO1_DATA3 61
+#define GPOUT_SYS_SDIO1_DATA4 63
+#define GPOUT_SYS_SDIO1_DATA5 63
+#define GPOUT_SYS_SDIO1_DATA6 64
+#define GPOUT_SYS_SDIO1_DATA7 65
+#define GPOUT_SYS_SDIO1_RST 66
+#define GPOUT_SYS_UART1_RTS 67
+#define GPOUT_SYS_UART1_TX 68
+#define GPOUT_SYS_I2STX1_SDO0 69
+#define GPOUT_SYS_I2STX1_SDO1 70
+#define GPOUT_SYS_I2STX1_SDO2 71
+#define GPOUT_SYS_I2STX1_SDO3 72
+#define GPOUT_SYS_SPI1_CLK 73
+#define GPOUT_SYS_SPI1_FSS 74
+#define GPOUT_SYS_SPI1_TXD 75
+#define GPOUT_SYS_I2C2_CLK 76
+#define GPOUT_SYS_I2C2_DATA 77
+#define GPOUT_SYS_UART2_RTS 78
+#define GPOUT_SYS_UART2_TX 79
+#define GPOUT_SYS_SPI2_CLK 80
+#define GPOUT_SYS_SPI2_FSS 81
+#define GPOUT_SYS_SPI2_TXD 82
+#define GPOUT_SYS_I2C3_CLK 83
+#define GPOUT_SYS_I2C3_DATA 84
+#define GPOUT_SYS_UART3_TX 85
+#define GPOUT_SYS_SPI3_CLK 86
+#define GPOUT_SYS_SPI3_FSS 87
+#define GPOUT_SYS_SPI3_TXD 88
+#define GPOUT_SYS_I2C4_CLK 89
+#define GPOUT_SYS_I2C4_DATA 90
+#define GPOUT_SYS_UART4_RTS 91
+#define GPOUT_SYS_UART4_TX 92
+#define GPOUT_SYS_SPI4_CLK 93
+#define GPOUT_SYS_SPI4_FSS 94
+#define GPOUT_SYS_SPI4_TXD 95
+#define GPOUT_SYS_I2C5_CLK 96
+#define GPOUT_SYS_I2C5_DATA 97
+#define GPOUT_SYS_UART5_RTS 98
+#define GPOUT_SYS_UART5_TX 99
+#define GPOUT_SYS_SPI5_CLK 100
+#define GPOUT_SYS_SPI5_FSS 101
+#define GPOUT_SYS_SPI5_TXD 102
+#define GPOUT_SYS_I2C6_CLK 103
+#define GPOUT_SYS_I2C6_DATA 104
+#define GPOUT_SYS_SPI6_CLK 105
+#define GPOUT_SYS_SPI6_FSS 106
+#define GPOUT_SYS_SPI6_TXD 107
+
+/* aon_iomux dout */
+#define GPOUT_AON_CLK_32K_OUT 2
+#define GPOUT_AON_PTC0_PWM4 3
+#define GPOUT_AON_PTC0_PWM5 4
+#define GPOUT_AON_PTC0_PWM6 5
+#define GPOUT_AON_PTC0_PWM7 6
+#define GPOUT_AON_CLK_GCLK0 7
+#define GPOUT_AON_CLK_GCLK1 8
+#define GPOUT_AON_CLK_GCLK2 9
+
+/* sys_iomux doen */
+#define GPOEN_ENABLE 0
+#define GPOEN_DISABLE 1
+#define GPOEN_SYS_HDMI_CEC_SDA 2
+#define GPOEN_SYS_HDMI_DDC_SCL 3
+#define GPOEN_SYS_HDMI_DDC_SDA 4
+#define GPOEN_SYS_I2C0_CLK 5
+#define GPOEN_SYS_I2C0_DATA 6
+#define GPOEN_SYS_HIFI4_JTAG_TDO 7
+#define GPOEN_SYS_JTAG_TDO 8
+#define GPOEN_SYS_PWM0_CHANNEL0 9
+#define GPOEN_SYS_PWM0_CHANNEL1 10
+#define GPOEN_SYS_PWM0_CHANNEL2 11
+#define GPOEN_SYS_PWM0_CHANNEL3 12
+#define GPOEN_SYS_SPI0_NSSPCTL 13
+#define GPOEN_SYS_SPI0_NSSP 14
+#define GPOEN_SYS_TDM_SYNC 15
+#define GPOEN_SYS_TDM_TXD 16
+#define GPOEN_SYS_I2C1_CLK 17
+#define GPOEN_SYS_I2C1_DATA 18
+#define GPOEN_SYS_SDIO1_CMD 19
+#define GPOEN_SYS_SDIO1_DATA0 20
+#define GPOEN_SYS_SDIO1_DATA1 21
+#define GPOEN_SYS_SDIO1_DATA2 22
+#define GPOEN_SYS_SDIO1_DATA3 23
+#define GPOEN_SYS_SDIO1_DATA4 24
+#define GPOEN_SYS_SDIO1_DATA5 25
+#define GPOEN_SYS_SDIO1_DATA6 26
+#define GPOEN_SYS_SDIO1_DATA7 27
+#define GPOEN_SYS_SPI1_NSSPCTL 28
+#define GPOEN_SYS_SPI1_NSSP 29
+#define GPOEN_SYS_I2C2_CLK 30
+#define GPOEN_SYS_I2C2_DATA 31
+#define GPOEN_SYS_SPI2_NSSPCTL 32
+#define GPOEN_SYS_SPI2_NSSP 33
+#define GPOEN_SYS_I2C3_CLK 34
+#define GPOEN_SYS_I2C3_DATA 35
+#define GPOEN_SYS_SPI3_NSSPCTL 36
+#define GPOEN_SYS_SPI3_NSSP 37
+#define GPOEN_SYS_I2C4_CLK 38
+#define GPOEN_SYS_I2C4_DATA 39
+#define GPOEN_SYS_SPI4_NSSPCTL 40
+#define GPOEN_SYS_SPI4_NSSP 41
+#define GPOEN_SYS_I2C5_CLK 42
+#define GPOEN_SYS_I2C5_DATA 43
+#define GPOEN_SYS_SPI5_NSSPCTL 44
+#define GPOEN_SYS_SPI5_NSSP 45
+#define GPOEN_SYS_I2C6_CLK 46
+#define GPOEN_SYS_I2C6_DATA 47
+#define GPOEN_SYS_SPI6_NSSPCTL 48
+#define GPOEN_SYS_SPI6_NSSP 49
+
+/* aon_iomux doen */
+#define GPOEN_AON_PTC0_OE_N_4 2
+#define GPOEN_AON_PTC0_OE_N_5 3
+#define GPOEN_AON_PTC0_OE_N_6 4
+#define GPOEN_AON_PTC0_OE_N_7 5
+
+/* sys_iomux gin */
+#define GPI_NONE 255
+
+#define GPI_SYS_WAVE511_UART_RX 0
+#define GPI_SYS_CAN0_RXD 1
+#define GPI_SYS_USB_OVERCURRENT 2
+#define GPI_SYS_SPDIF 3
+#define GPI_SYS_JTAG_RST 4
+#define GPI_SYS_HDMI_CEC_SDA 5
+#define GPI_SYS_HDMI_DDC_SCL 6
+#define GPI_SYS_HDMI_DDC_SDA 7
+#define GPI_SYS_HDMI_HPD 8
+#define GPI_SYS_I2C0_CLK 9
+#define GPI_SYS_I2C0_DATA 10
+#define GPI_SYS_SDIO0_CD 11
+#define GPI_SYS_SDIO0_INT 12
+#define GPI_SYS_SDIO0_WP 13
+#define GPI_SYS_UART0_RX 14
+#define GPI_SYS_HIFI4_JTAG_TCK 15
+#define GPI_SYS_HIFI4_JTAG_TDI 16
+#define GPI_SYS_HIFI4_JTAG_TMS 17
+#define GPI_SYS_HIFI4_JTAG_RST 18
+#define GPI_SYS_JTAG_TDI 19
+#define GPI_SYS_JTAG_TMS 20
+#define GPI_SYS_PDM_DMIC0 21
+#define GPI_SYS_PDM_DMIC1 22
+#define GPI_SYS_I2SRX_SDIN0 23
+#define GPI_SYS_I2SRX_SDIN1 24
+#define GPI_SYS_I2SRX_SDIN2 25
+#define GPI_SYS_SPI0_CLK 26
+#define GPI_SYS_SPI0_FSS 27
+#define GPI_SYS_SPI0_RXD 28
+#define GPI_SYS_JTAG_TCK 29
+#define GPI_SYS_MCLK_EXT 30
+#define GPI_SYS_I2SRX_BCLK 31
+#define GPI_SYS_I2SRX_LRCK 32
+#define GPI_SYS_I2STX0_BCLK 33
+#define GPI_SYS_I2STX0_LRCK 34
+#define GPI_SYS_TDM_CLK 35
+#define GPI_SYS_TDM_RXD 36
+#define GPI_SYS_TDM_SYNC 37
+#define GPI_SYS_CAN1_RXD 38
+#define GPI_SYS_I2C1_CLK 39
+#define GPI_SYS_I2C1_DATA 40
+#define GPI_SYS_SDIO1_CD 41
+#define GPI_SYS_SDIO1_INT 42
+#define GPI_SYS_SDIO1_WP 43
+#define GPI_SYS_SDIO1_CMD 44
+#define GPI_SYS_SDIO1_DATA0 45
+#define GPI_SYS_SDIO1_DATA1 46
+#define GPI_SYS_SDIO1_DATA2 47
+#define GPI_SYS_SDIO1_DATA3 48
+#define GPI_SYS_SDIO1_DATA4 49
+#define GPI_SYS_SDIO1_DATA5 50
+#define GPI_SYS_SDIO1_DATA6 51
+#define GPI_SYS_SDIO1_DATA7 52
+#define GPI_SYS_SDIO1_STRB 53
+#define GPI_SYS_UART1_CTS 54
+#define GPI_SYS_UART1_RX 55
+#define GPI_SYS_SPI1_CLK 56
+#define GPI_SYS_SPI1_FSS 57
+#define GPI_SYS_SPI1_RXD 58
+#define GPI_SYS_I2C2_CLK 59
+#define GPI_SYS_I2C2_DATA 60
+#define GPI_SYS_UART2_CTS 61
+#define GPI_SYS_UART2_RX 62
+#define GPI_SYS_SPI2_CLK 63
+#define GPI_SYS_SPI2_FSS 64
+#define GPI_SYS_SPI2_RXD 65
+#define GPI_SYS_I2C3_CLK 66
+#define GPI_SYS_I2C3_DATA 67
+#define GPI_SYS_UART3_RX 68
+#define GPI_SYS_SPI3_CLK 69
+#define GPI_SYS_SPI3_FSS 70
+#define GPI_SYS_SPI3_RXD 71
+#define GPI_SYS_I2C4_CLK 72
+#define GPI_SYS_I2C4_DATA 73
+#define GPI_SYS_UART4_CTS 74
+#define GPI_SYS_UART4_RX 75
+#define GPI_SYS_SPI4_CLK 76
+#define GPI_SYS_SPI4_FSS 77
+#define GPI_SYS_SPI4_RXD 78
+#define GPI_SYS_I2C5_CLK 79
+#define GPI_SYS_I2C5_DATA 80
+#define GPI_SYS_UART5_CTS 81
+#define GPI_SYS_UART5_RX 82
+#define GPI_SYS_SPI5_CLK 83
+#define GPI_SYS_SPI5_FSS 84
+#define GPI_SYS_SPI5_RXD 85
+#define GPI_SYS_I2C6_CLK 86
+#define GPI_SYS_I2C6_DATA 87
+#define GPI_SYS_SPI6_CLK 88
+#define GPI_SYS_SPI6_FSS 89
+#define GPI_SYS_SPI6_RXD 90
+
+/* aon_iomux gin */
+#define GPI_AON_PMU_GPIO_WAKEUP_0 0
+#define GPI_AON_PMU_GPIO_WAKEUP_1 1
+#define GPI_AON_PMU_GPIO_WAKEUP_2 2
+#define GPI_AON_PMU_GPIO_WAKEUP_3 3
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
+
+/* SYSCRG resets */
+#define JH7110_SYSRST_JTAG2APB 0
+#define JH7110_SYSRST_SYSCON 1
+#define JH7110_SYSRST_IOMUX_APB 2
+#define JH7110_SYSRST_BUS 3
+#define JH7110_SYSRST_DEBUG 4
+#define JH7110_SYSRST_CORE0 5
+#define JH7110_SYSRST_CORE1 6
+#define JH7110_SYSRST_CORE2 7
+#define JH7110_SYSRST_CORE3 8
+#define JH7110_SYSRST_CORE4 9
+#define JH7110_SYSRST_CORE0_ST 10
+#define JH7110_SYSRST_CORE1_ST 11
+#define JH7110_SYSRST_CORE2_ST 12
+#define JH7110_SYSRST_CORE3_ST 13
+#define JH7110_SYSRST_CORE4_ST 14
+#define JH7110_SYSRST_TRACE0 15
+#define JH7110_SYSRST_TRACE1 16
+#define JH7110_SYSRST_TRACE2 17
+#define JH7110_SYSRST_TRACE3 18
+#define JH7110_SYSRST_TRACE4 19
+#define JH7110_SYSRST_TRACE_COM 20
+#define JH7110_SYSRST_GPU_APB 21
+#define JH7110_SYSRST_GPU_DOMA 22
+#define JH7110_SYSRST_NOC_BUS_APB_BUS 23
+#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24
+#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25
+#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26
+#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27
+#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28
+#define JH7110_SYSRST_NOC_BUS_DDRC 29
+#define JH7110_SYSRST_NOC_BUS_STG_AXI 30
+#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31
+
+#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32
+#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33
+#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34
+#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35
+#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36
+#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37
+#define JH7110_SYSRST_DDR_AXI 38
+#define JH7110_SYSRST_DDR_OSC 39
+#define JH7110_SYSRST_DDR_APB 40
+#define JH7110_SYSRST_DOM_ISP_TOP_N 41
+#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42
+#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43
+#define JH7110_SYSRST_CODAJ12_AXI 44
+#define JH7110_SYSRST_CODAJ12_CORE 45
+#define JH7110_SYSRST_CODAJ12_APB 46
+#define JH7110_SYSRST_WAVE511_AXI 47
+#define JH7110_SYSRST_WAVE511_BPU 48
+#define JH7110_SYSRST_WAVE511_VCE 49
+#define JH7110_SYSRST_WAVE511_APB 50
+#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51
+#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52
+#define JH7110_SYSRST_AXIMEM0_AXI 53
+#define JH7110_SYSRST_WAVE420L_AXI 54
+#define JH7110_SYSRST_WAVE420L_BPU 55
+#define JH7110_SYSRST_WAVE420L_VCE 56
+#define JH7110_SYSRST_WAVE420L_APB 57
+#define JH7110_SYSRST_AXIMEM1_AXI 58
+#define JH7110_SYSRST_AXIMEM2_AXI 59
+#define JH7110_SYSRST_INTMEM 60
+#define JH7110_SYSRST_QSPI_AHB 61
+#define JH7110_SYSRST_QSPI_APB 62
+#define JH7110_SYSRST_QSPI_REF 63
+
+#define JH7110_SYSRST_SDIO0_AHB 64
+#define JH7110_SYSRST_SDIO1_AHB 65
+#define JH7110_SYSRST_GMAC1_AXI 66
+#define JH7110_SYSRST_GMAC1_AHB 67
+#define JH7110_SYSRST_MAILBOX 68
+#define JH7110_SYSRST_SPI0_APB 69
+#define JH7110_SYSRST_SPI1_APB 70
+#define JH7110_SYSRST_SPI2_APB 71
+#define JH7110_SYSRST_SPI3_APB 72
+#define JH7110_SYSRST_SPI4_APB 73
+#define JH7110_SYSRST_SPI5_APB 74
+#define JH7110_SYSRST_SPI6_APB 75
+#define JH7110_SYSRST_I2C0_APB 76
+#define JH7110_SYSRST_I2C1_APB 77
+#define JH7110_SYSRST_I2C2_APB 78
+#define JH7110_SYSRST_I2C3_APB 79
+#define JH7110_SYSRST_I2C4_APB 80
+#define JH7110_SYSRST_I2C5_APB 81
+#define JH7110_SYSRST_I2C6_APB 82
+#define JH7110_SYSRST_UART0_APB 83
+#define JH7110_SYSRST_UART0_CORE 84
+#define JH7110_SYSRST_UART1_APB 85
+#define JH7110_SYSRST_UART1_CORE 86
+#define JH7110_SYSRST_UART2_APB 87
+#define JH7110_SYSRST_UART2_CORE 88
+#define JH7110_SYSRST_UART3_APB 89
+#define JH7110_SYSRST_UART3_CORE 90
+#define JH7110_SYSRST_UART4_APB 91
+#define JH7110_SYSRST_UART4_CORE 92
+#define JH7110_SYSRST_UART5_APB 93
+#define JH7110_SYSRST_UART5_CORE 94
+#define JH7110_SYSRST_SPDIF_APB 95
+
+#define JH7110_SYSRST_PWMDAC_APB 96
+#define JH7110_SYSRST_PDM_DMIC 97
+#define JH7110_SYSRST_PDM_APB 98
+#define JH7110_SYSRST_I2SRX_APB 99
+#define JH7110_SYSRST_I2SRX_BCLK 100
+#define JH7110_SYSRST_I2STX0_APB 101
+#define JH7110_SYSRST_I2STX0_BCLK 102
+#define JH7110_SYSRST_I2STX1_APB 103
+#define JH7110_SYSRST_I2STX1_BCLK 104
+#define JH7110_SYSRST_TDM_AHB 105
+#define JH7110_SYSRST_TDM_CORE 106
+#define JH7110_SYSRST_TDM_APB 107
+#define JH7110_SYSRST_PWM_APB 108
+#define JH7110_SYSRST_WDT_APB 109
+#define JH7110_SYSRST_WDT_CORE 110
+#define JH7110_SYSRST_CAN0_APB 111
+#define JH7110_SYSRST_CAN0_CORE 112
+#define JH7110_SYSRST_CAN0_TIMER 113
+#define JH7110_SYSRST_CAN1_APB 114
+#define JH7110_SYSRST_CAN1_CORE 115
+#define JH7110_SYSRST_CAN1_TIMER 116
+#define JH7110_SYSRST_TIMER_APB 117
+#define JH7110_SYSRST_TIMER0 118
+#define JH7110_SYSRST_TIMER1 119
+#define JH7110_SYSRST_TIMER2 120
+#define JH7110_SYSRST_TIMER3 121
+#define JH7110_SYSRST_INT_CTRL_APB 122
+#define JH7110_SYSRST_TEMP_APB 123
+#define JH7110_SYSRST_TEMP_CORE 124
+#define JH7110_SYSRST_JTAG_CERTIFICATION 125
+
+#define JH7110_SYSRST_END 126
+
+/* AONCRG resets */
+#define JH7110_AONRST_GMAC0_AXI 0
+#define JH7110_AONRST_GMAC0_AHB 1
+#define JH7110_AONRST_IOMUX 2
+#define JH7110_AONRST_PMU_APB 3
+#define JH7110_AONRST_PMU_WKUP 4
+#define JH7110_AONRST_RTC_APB 5
+#define JH7110_AONRST_RTC_CAL 6
+#define JH7110_AONRST_RTC_32K 7
+
+#define JH7110_AONRST_END 8
+
+/* STGCRG resets */
+#define JH7110_STGRST_SYSCON_PRESETN 0
+#define JH7110_STGRST_HIFI4_CORE 1
+#define JH7110_STGRST_HIFI4_AXI 2
+#define JH7110_STGRST_SEC_TOP_HRESETN 3
+#define JH7110_STGRST_E24_CORE 4
+#define JH7110_STGRST_DMA1P_AXI 5
+#define JH7110_STGRST_DMA1P_AHB 6
+#define JH7110_STGRST_USB_AXI 7
+#define JH7110_STGRST_USB_APB 8
+#define JH7110_STGRST_USB_UTMI_APB 9
+#define JH7110_STGRST_USB_PWRUP 10
+#define JH7110_STGRST_PCIE0_MST0 11
+#define JH7110_STGRST_PCIE0_SLV0 12
+#define JH7110_STGRST_PCIE0_SLV 13
+#define JH7110_STGRST_PCIE0_BRG 14
+#define JH7110_STGRST_PCIE0_CORE 15
+#define JH7110_STGRST_PCIE0_APB 16
+#define JH7110_STGRST_PCIE1_MST0 17
+#define JH7110_STGRST_PCIE1_SLV0 18
+#define JH7110_STGRST_PCIE1_SLV 19
+#define JH7110_STGRST_PCIE1_BRG 20
+#define JH7110_STGRST_PCIE1_CORE 21
+#define JH7110_STGRST_PCIE1_APB 22
+
+#define JH7110_STGRST_END 23
+
+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */
*/
#define FTWDT010_TIMEOUT_FACTOR (get_board_sys_clk() / 1000) /* 1 ms */
-void ftwdt010_wdt_reset(void);
-void ftwdt010_wdt_disable(void);
-
#endif /* __FTWDT010_H */
prelink_le32(data);
}
+ munmap(data, st.st_size);
+
return 0;
}
#define cpu_to_target32 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 32)
#define cpu_to_target64 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 64)
-static void* get_offset_bonn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
+static void *get_offset_bonn(void *data, Elf_Phdr *phdrs, size_t phnum, Elf_Addr addr)
{
Elf_Phdr *p;
Elf_Rela *rela_dyn = NULL;
size_t rela_count = 0;
Elf_Sym *dynsym = NULL;
- for (dyn = dyns;; ++dyn) {
+ for (dyn = dyns; ; ++dyn) {
if (targetnn_to_cpu(dyn->d_tag) == DT_NULL)
break;
else if (targetnn_to_cpu(dyn->d_tag) == DT_RELA)
rela_dyn = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
else if (targetnn_to_cpu(dyn->d_tag) == DT_RELASZ)
- rela_count = targetnn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
+ rela_count = targetnn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
else if (targetnn_to_cpu(dyn->d_tag) == DT_SYMTAB)
dynsym = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
continue;
if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
- *((uintnn_t*) buf) = r->r_addend;
+ *((uintnn_t *)buf) = r->r_addend;
else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_32)
- *((uint32_t*) buf) = cpu_to_target32(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
+ *((uint32_t *)buf) = cpu_to_target32(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_64)
- *((uint64_t*) buf) = cpu_to_target64(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
+ *((uint64_t *)buf) = cpu_to_target64(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
}
}
projects / thirdparty / u-boot.git / commitdiff
