x86/cpufeatures: Shorten X86_FEATURE_AMD_HETEROGENEOUS_CORES

Shorten X86_FEATURE_AMD_HETEROGENEOUS_CORES to X86_FEATURE_AMD_HTR_CORES
to make the last column aligned consistently in the whole file.

No functional changes.

Suggested-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Xin Li (Intel) <xin@zytor.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/20250415175410.2944032-4-xin@zytor.com

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index bd27a1d701771d1af688d3874e94a0bab9789677..bc81b9d1aeca5c0cbe62ea3c48147238bacce74c 100644 (file)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -478,7 +478,7 @@
 #define X86_FEATURE_CLEAR_BHB_HW       (21*32+ 3) /* BHI_DIS_S HW control enabled */
 #define X86_FEATURE_CLEAR_BHB_VMEXIT   (21*32+ 4) /* Clear branch history at vmexit using SW loop */
 #define X86_FEATURE_AMD_FAST_CPPC      (21*32+ 5) /* Fast CPPC */
-#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32+ 6) /* Heterogeneous Core Topology */
+#define X86_FEATURE_AMD_HTR_CORES      (21*32+ 6) /* Heterogeneous Core Topology */
 #define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32+ 7) /* Workload Classification */
 #define X86_FEATURE_PREFER_YMM         (21*32+ 8) /* Avoid ZMM registers due to downclocking */
 

diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c
index 77bfb846490c07bb2bee9ac789423b486fbe5176..62ca714aae77d57e537e18cddc5c8087ad92476e 100644 (file)
--- a/arch/x86/kernel/acpi/cppc.c
+++ b/arch/x86/kernel/acpi/cppc.c
@@ -272,7 +272,7 @@ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator)
        }
 
        /* detect if running on heterogeneous design */
-       if (cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES)) {
+       if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES)) {
                switch (core_type) {
                case TOPO_CPU_TYPE_UNKNOWN:
                        pr_warn("Undefined core type found for cpu %d\n", cpu);

diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 16f3ca30626ab29eb192e8c59f82c5a5834b0fab..c75c57b32b742d30f725d61694a81a1d3737396a 100644 (file)
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -53,7 +53,7 @@ static const struct cpuid_bit cpuid_bits[] = {
        { X86_FEATURE_PERFMON_V2,               CPUID_EAX,  0, 0x80000022, 0 },
        { X86_FEATURE_AMD_LBR_V2,               CPUID_EAX,  1, 0x80000022, 0 },
        { X86_FEATURE_AMD_LBR_PMC_FREEZE,       CPUID_EAX,  2, 0x80000022, 0 },
-       { X86_FEATURE_AMD_HETEROGENEOUS_CORES,  CPUID_EAX, 30, 0x80000026, 0 },
+       { X86_FEATURE_AMD_HTR_CORES,            CPUID_EAX, 30, 0x80000026, 0 },
        { 0, 0, 0, 0, 0 }
 };
 

diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topology_amd.c
index 03b3c9c3a45e2ef16449c666793a2c91378f5542..eb799e2405f9f23dbaa86ced76890aba74e1122d 100644 (file)
--- a/arch/x86/kernel/cpu/topology_amd.c
+++ b/arch/x86/kernel/cpu/topology_amd.c
@@ -182,7 +182,7 @@ static void parse_topology_amd(struct topo_scan *tscan)
        if (cpu_feature_enabled(X86_FEATURE_TOPOEXT))
                has_topoext = cpu_parse_topology_ext(tscan);
 
-       if (cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES))
+       if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES))
                tscan->c->topo.cpu_type = cpuid_ebx(0x80000026);
 
        if (!has_topoext && !parse_8000_0008(tscan))

diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index e10c3f4ab328d15fc0de1d1f876a19ef8e2cea58..fdbc92aca812a45a497ebbc17dccade8b0950c42 100644 (file)
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -468,7 +468,7 @@
 #define X86_FEATURE_CLEAR_BHB_HW       (21*32+ 3) /* BHI_DIS_S HW control enabled */
 #define X86_FEATURE_CLEAR_BHB_VMEXIT   (21*32+ 4) /* Clear branch history at vmexit using SW loop */
 #define X86_FEATURE_AMD_FAST_CPPC      (21*32+ 5) /* Fast CPPC */
-#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32+ 6) /* Heterogeneous Core Topology */
+#define X86_FEATURE_AMD_HTR_CORES      (21*32+ 6) /* Heterogeneous Core Topology */
 #define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32+ 7) /* Workload Classification */
 #define X86_FEATURE_PREFER_YMM         (21*32+ 8) /* Avoid ZMM registers due to downclocking */