#include <linux/types.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct adi_caps {
__u64 blksz;
return adi_state.caps.nbits;
}
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* !(__ASM_SPARC64_ADI_H) */
#ifndef ___ASM_SPARC_AUXIO_H
#define ___ASM_SPARC_AUXIO_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
extern void __iomem *auxio_register;
-#endif /* ifndef __ASSEMBLY__ */
+#endif /* ifndef __ASSEMBLER__ */
#if defined(__sparc__) && defined(__arch64__)
#include <asm/auxio_64.h>
#define AUXIO_FLPY_EJCT 0x02 /* Eject floppy disk. Write only. */
#define AUXIO_LED 0x01 /* On if set, off if unset. Read/Write */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/*
* NOTE: these routines are implementation dependent--
} \
} while (0)
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
/* AUXIO2 (Power Off Control) */
#define AUXIO_PCIO_CPWR_OFF 0x02 /* Courtesy Power Off */
#define AUXIO_PCIO_SPWR_OFF 0x01 /* System Power Off */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#define AUXIO_LTE_ON 1
#define AUXIO_LTE_OFF 0
*/
void auxio_set_led(int on);
-#endif /* ifndef __ASSEMBLY__ */
+#endif /* ifndef __ASSEMBLER__ */
#endif /* !(_SPARC64_AUXIO_H) */
#include <asm/page.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <linux/mm.h>
#define flush_cache_vmap_early(start, end) do { } while (0)
#define flush_cache_vunmap(start, end) do { } while (0)
-#endif /* !__ASSEMBLY__ */
+#endif /* !__ASSEMBLER__ */
#endif /* _SPARC64_CACHEFLUSH_H */
#ifndef ___ASM_SPARC_CPUDATA_H
#define ___ASM_SPARC_CPUDATA_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <linux/threads.h>
#include <linux/percpu.h>
extern const struct seq_operations cpuinfo_op;
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#if defined(__sparc__) && defined(__arch64__)
#include <asm/cpudata_64.h>
#ifndef _SPARC64_CPUDATA_H
#define _SPARC64_CPUDATA_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
typedef struct {
/* Dcache line 1 */
#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
#define local_cpu_data() (*this_cpu_ptr(&__cpu_data))
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#include <asm/trap_block.h>
#ifndef _SPARC64_DELAY_H
#define _SPARC64_DELAY_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
void __delay(unsigned long loops);
void udelay(unsigned long usecs);
#define mdelay(n) udelay((n) * 1000)
-#endif /* !__ASSEMBLY__ */
+#endif /* !__ASSEMBLER__ */
#endif /* _SPARC64_DELAY_H */
#define MCOUNT_ADDR ((unsigned long)(_mcount))
#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
void _mcount(void);
#endif
#ifndef _SPARC64_HVTRAP_H
#define _SPARC64_HVTRAP_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <linux/types.h>
*/
#define HV_FAST_MACH_EXIT 0x00
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
void sun4v_mach_exit(unsigned long exit_code);
#endif
*/
#define HV_FAST_MACH_DESC 0x01
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_mach_desc(unsigned long buffer_pa,
unsigned long buf_len,
unsigned long *real_buf_len);
*/
#define HV_FAST_MACH_SIR 0x02
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
void sun4v_mach_sir(void);
#endif
*/
#define HV_FAST_MACH_SET_WATCHDOG 0x05
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
unsigned long *orig_timeout);
#endif
*/
#define HV_FAST_CPU_START 0x10
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_cpu_start(unsigned long cpuid,
unsigned long pc,
unsigned long rtba,
*/
#define HV_FAST_CPU_STOP 0x11
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_cpu_stop(unsigned long cpuid);
#endif
*/
#define HV_FAST_CPU_YIELD 0x12
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_cpu_yield(void);
#endif
*/
#define HV_FAST_CPU_POKE 0x13
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_cpu_poke(unsigned long cpuid);
#endif
#define HV_CPU_QUEUE_RES_ERROR 0x3e
#define HV_CPU_QUEUE_NONRES_ERROR 0x3f
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_cpu_qconf(unsigned long type,
unsigned long queue_paddr,
unsigned long num_queue_entries);
*/
#define HV_FAST_CPU_MONDO_SEND 0x42
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count,
unsigned long cpu_list_pa,
unsigned long mondo_block_pa);
#define HV_CPU_STATE_RUNNING 0x02
#define HV_CPU_STATE_ERROR 0x03
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
long sun4v_cpu_state(unsigned long cpuid);
#endif
*
* Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
*/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct hv_tsb_descr {
unsigned short pgsz_idx;
unsigned short assoc;
* The fault status block is a multiple of 64-bytes and must be aligned
* on a 64-byte boundary.
*/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct hv_fault_status {
unsigned long i_fault_type;
unsigned long i_fault_addr;
*/
#define HV_FAST_MMU_TSB_CTX0 0x20
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
unsigned long tsb_desc_ra);
#endif
*/
#define HV_FAST_MMU_DEMAP_ALL 0x24
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
void sun4v_mmu_demap_all(void);
#endif
*/
#define HV_FAST_MMU_MAP_PERM_ADDR 0x25
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
unsigned long set_to_zero,
unsigned long tte,
*/
#define HV_CCB_SUBMIT 0x34
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_ccb_submit(unsigned long ccb_buf,
unsigned long len,
unsigned long flags,
*/
#define HV_CCB_INFO 0x35
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_ccb_info(unsigned long ca,
void *info_arr);
#endif
*/
#define HV_CCB_KILL 0x36
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_ccb_kill(unsigned long ca,
void *kill_status);
#endif
*/
#define HV_FAST_TOD_GET 0x50
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_tod_get(unsigned long *time);
#endif
*/
#define HV_FAST_TOD_SET 0x51
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_tod_set(unsigned long time);
#endif
*/
#define HV_FAST_CONS_WRITE 0x63
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
long sun4v_con_getchar(long *status);
long sun4v_con_putchar(long c);
long sun4v_con_read(unsigned long buffer,
#define HV_SOFT_STATE_NORMAL 0x01
#define HV_SOFT_STATE_TRANSITION 0x02
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
unsigned long msg_string_ra);
#endif
*/
#define HV_FAST_SVC_CLRSTATUS 0x84
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_svc_send(unsigned long svc_id,
unsigned long buffer,
unsigned long buffer_size,
* start (offset 0) of the trap trace buffer, and is described as
* follows:
*/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct hv_trap_trace_control {
unsigned long head_offset;
unsigned long tail_offset;
*
* Each trap trace buffer entry is laid out as follows:
*/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct hv_trap_trace_entry {
unsigned char type; /* Hypervisor or guest entry? */
unsigned char hpstate; /* Hyper-privileged state */
*/
#define HV_FAST_INTR_DEVINO2SYSINO 0xa0
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
unsigned long devino);
#endif
*/
#define HV_FAST_INTR_GETENABLED 0xa1
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_intr_getenabled(unsigned long sysino);
#endif
*/
#define HV_FAST_INTR_SETENABLED 0xa2
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_intr_setenabled(unsigned long sysino,
unsigned long intr_enabled);
#endif
*/
#define HV_FAST_INTR_GETSTATE 0xa3
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_intr_getstate(unsigned long sysino);
#endif
*/
#define HV_FAST_INTR_SETSTATE 0xa4
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
#endif
*/
#define HV_FAST_INTR_GETTARGET 0xa5
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_intr_gettarget(unsigned long sysino);
#endif
*/
#define HV_FAST_INTR_SETTARGET 0xa6
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
#endif
*/
#define HV_FAST_VINTR_SET_TARGET 0xae
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
unsigned long dev_ino,
unsigned long *cookie);
#define LDC_MTE_SZ64K 0x0000000000000001 /* 64K page */
#define LDC_MTE_SZ8K 0x0000000000000000 /* 8K page */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct ldc_mtable_entry {
unsigned long mte;
unsigned long cookie;
*/
#define HV_FAST_LDC_REVOKE 0xef
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
unsigned long ra,
unsigned long num_entries);
#define HV_FAST_N2_GET_PERFREG 0x104
#define HV_FAST_N2_SET_PERFREG 0x105
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_niagara_getperf(unsigned long reg,
unsigned long *val);
unsigned long sun4v_niagara_setperf(unsigned long reg,
* a buffer where these statistics can be collected. It is continually
* updated once configured. The layout is as follows:
*/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct hv_mmu_statistics {
unsigned long immu_tsb_hits_ctx0_8k_tte;
unsigned long immu_tsb_ticks_ctx0_8k_tte;
*/
#define HV_FAST_MMUSTAT_INFO 0x103
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_mmustat_conf(unsigned long ra, unsigned long *orig_ra);
unsigned long sun4v_mmustat_info(unsigned long *ra);
#endif
#define HV_NCS_QCONF 0x01
#define HV_NCS_QTAIL_UPDATE 0x02
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct hv_ncs_queue_entry {
/* MAU Control Register */
unsigned long mau_control;
*/
#define HV_FAST_NCS_REQUEST 0x110
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_ncs_request(unsigned long request,
unsigned long arg_ra,
unsigned long arg_size);
#define HV_FAST_REBOOT_DATA_SET 0x172
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_reboot_data_set(unsigned long ra,
unsigned long len);
#endif
#define HV_FAST_VT_GET_PERFREG 0x184
#define HV_FAST_VT_SET_PERFREG 0x185
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_vt_get_perfreg(unsigned long reg_num,
unsigned long *reg_val);
unsigned long sun4v_vt_set_perfreg(unsigned long reg_num,
#define HV_FAST_T5_GET_PERFREG 0x1a8
#define HV_FAST_T5_SET_PERFREG 0x1a9
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_t5_get_perfreg(unsigned long reg_num,
unsigned long *reg_val);
unsigned long sun4v_t5_set_perfreg(unsigned long reg_num,
#define HV_FAST_M7_GET_PERFREG 0x43
#define HV_FAST_M7_SET_PERFREG 0x44
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_m7_get_perfreg(unsigned long reg_num,
unsigned long *reg_val);
unsigned long sun4v_m7_set_perfreg(unsigned long reg_num,
#define HV_GRP_T5_CPU 0x0211
#define HV_GRP_DIAG 0x0300
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
unsigned long sun4v_get_version(unsigned long group,
unsigned long *major,
unsigned long *minor);
#ifndef _ASM_IRQFLAGS_H
#define _ASM_IRQFLAGS_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <linux/types.h>
#include <asm/psr.h>
return arch_irqs_disabled_flags(arch_local_save_flags());
}
-#endif /* (__ASSEMBLY__) */
+#endif /* (__ASSEMBLER__) */
#endif /* !(_ASM_IRQFLAGS_H) */
#include <asm/pil.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
static inline notrace unsigned long arch_local_save_flags(void)
{
return flags;
}
-#endif /* (__ASSEMBLY__) */
+#endif /* (__ASSEMBLER__) */
#endif /* !(_ASM_IRQFLAGS_H) */
#ifndef _ASM_SPARC_JUMP_LABEL_H
#define _ASM_SPARC_JUMP_LABEL_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <linux/types.h>
jump_label_t key;
};
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif
#define DEBUG_BP_TRAP 126
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* The debug vector is passed in %o1 at boot time. It is a pointer to
* a structure in the debuggers address space. Here is its format.
*/
DIE_OOPS,
};
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
/* Some nice offset defines for assembler code. */
#define KDEBUG_ENTRY_OFF 0x0
#define ASI_LEON3_SYSCTRL_CFG_SNOOPING (1 << 27)
#define ASI_LEON3_SYSCTRL_CFG_SSIZE(c) (1 << ((c >> 20) & 0xf))
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* do a physical address bypass write, i.e. for 0x80000000 */
static inline void leon_store_reg(unsigned long paddr, unsigned long value)
return sparc_leon3_asr17() >> 28;
}
-#endif /*!__ASSEMBLY__*/
+#endif /*!__ASSEMBLER__*/
#ifdef CONFIG_SMP
# define LEON3_IRQ_IPI_DEFAULT 13
#define LEON2_CCR_DSETS_MASK 0x03000000UL
#define LEON2_CFG_SSIZE_MASK 0x00007000UL
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct vm_area_struct;
unsigned long leon_swprobe(unsigned long vaddr, unsigned long *paddr);
#endif /* CONFIG_SMP */
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
/* macros used in leon_mm.c */
#define PFN(x) ((x) >> PAGE_SHIFT)
#ifndef LEON_AMBA_H_INCLUDE
#define LEON_AMBA_H_INCLUDE
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct amba_prom_registers {
unsigned int phys_addr; /* The physical address of this register */
#define LEON3_GPTIMER_CONFIG_NRTIMERS(c) ((c)->config & 0x7)
#define LEON3_GPTIMER_CTRL_ISPENDING(r) (((r)&LEON3_GPTIMER_CTRL_PENDING) ? 1 : 0)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct leon3_irqctrl_regs_map {
u32 ilevel;
extern unsigned long leon3_gptimer_irq;
extern unsigned int sparc_leon_eirq;
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#define LEON3_IO_AREA 0xfff00000
#define LEON3_CONF_AREA 0xff000
#include <uapi/asm/mman.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#define arch_mmap_check(addr,len,flags) sparc_mmap_check(addr,len)
int sparc_mmap_check(unsigned long addr, unsigned long len);
}
#endif /* CONFIG_SPARC64 */
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#endif /* __SPARC_MMAN_H__ */
#define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
#define CTX_NRBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_NR_MASK)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#define TSB_ENTRY_ALIGNMENT 16
spinlock_t tag_lock;
} mm_context_t;
-#endif /* !__ASSEMBLY__ */
+#endif /* !__ASSEMBLER__ */
#define TSB_CONFIG_TSB 0x00
#define TSB_CONFIG_RSS_LIMIT 0x08
#ifndef __SPARC_MMU_CONTEXT_H
#define __SPARC_MMU_CONTEXT_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <asm-generic/mm_hooks.h>
#include <asm-generic/mmu_context.h>
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* !(__SPARC_MMU_CONTEXT_H) */
/* Derived heavily from Linus's Alpha/AXP ASN code... */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <linux/spinlock.h>
#include <linux/mm_types.h>
#include <asm-generic/mmu_context.h>
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* !(__SPARC64_MMU_CONTEXT_H) */
* MID: The moduleID of the cpu your read this from.
*/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
static inline void mxcc_set_stream_src(unsigned long *paddr)
{
"i" (ASI_M_MXCC));
}
-#endif /* !__ASSEMBLY__ */
+#endif /* !__ASSEMBLER__ */
#endif /* !(_SPARC_MXCC_H) */
#define CC_EREG 0x1F00E00 /* Error code register */
#define CC_CID 0x1F00F04 /* Component ID */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
static inline int bw_get_intr_mask(int sbus_level)
{
"i" (ASI_M_MXCC));
}
-#endif /* !__ASSEMBLY__ */
+#endif /* !__ASSEMBLER__ */
#endif /* !(_SPARC_OBIO_H) */
/* Empirical constants... */
#define LINUX_OPPROM_MAGIC 0x10010407
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <linux/of.h>
/* V0 prom device operations. */
unsigned int interrupt;
};
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* !(__SPARC_OPENPROM_H) */
#include <vdso/page.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE)
#define TASK_UNMAPPED_BASE 0x50000000
-#else /* !(__ASSEMBLY__) */
+#else /* !(__ASSEMBLER__) */
#define __pgprot(x) (x)
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#define PAGE_OFFSET 0xf0000000
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
extern unsigned long phys_base;
extern unsigned long pfn_base;
#endif
#define HUGE_MAX_HSTATE 5
#endif
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
struct pt_regs;
extern unsigned long PAGE_OFFSET;
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
/* The maximum number of physical memory address bits we support. The
* largest value we can support is whatever "KPGD_SHIFT + KPTE_BITS"
#define ILOG2_4MB 22
#define ILOG2_256MB 28
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
#define virt_to_phys __pa
#define phys_to_virt __va
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#include <asm-generic/getorder.h>
#ifndef __SPARC_PCIC_H
#define __SPARC_PCIC_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <linux/types.h>
#include <linux/smp.h>
#define PGDIR_MASK (~(PGDIR_SIZE-1))
#define PGDIR_ALIGN(__addr) (((__addr) + ~PGDIR_MASK) & PGDIR_MASK)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <asm-generic/pgtable-nopud.h>
#include <linux/spinlock.h>
__changed; \
})
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#define VMALLOC_START _AC(0xfe600000,UL)
#define VMALLOC_END _AC(0xffc00000,UL)
#error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages.
#endif
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
extern unsigned long VMALLOC_END;
pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \
__FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0))
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
/* PTE bits which are the same in SUN4U and SUN4V format. */
#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
/* We borrow bit 20 to store the exclusive marker in swap PTEs. */
#define _PAGE_SWP_EXCLUSIVE _AC(0x0000000000100000, UL)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
#endif /* CONFIG_HUGETLB_PAGE */
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* !(_SPARC64_PGTABLE_H) */
#include <asm/page.h>
-#ifdef __ASSEMBLY__
+#ifdef __ASSEMBLER__
#include <asm/thread_info.h> /* TI_UWINMASK for WINDOW_FLUSH */
#endif
bne 99b; \
restore %g0, %g0, %g0;
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
extern unsigned long last_valid_pfn;
/* This makes sense. Honest it does - Anton */
return entry;
}
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* !(_SPARC_PGTSRMMU_H) */
* XXX No longer using virtual page tables, kill this upper limit...
*/
#define VA_BITS 44
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
#else
#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
#endif
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* The Sparc processor specific thread struct. */
/* XXX This should die, everything can go into thread_info now. */
#endif
};
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#ifndef CONFIG_DEBUG_SPINLOCK
#define INIT_THREAD { \
}
#endif /* !(CONFIG_DEBUG_SPINLOCK) */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <linux/types.h>
#include <asm/fpumacro.h>
int do_mathemu(struct pt_regs *regs, struct fpustate *f, bool illegal_insn_trap);
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
#include <uapi/asm/psr.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* Get the %psr register. */
static inline unsigned int get_psr(void)
{
return fsr;
}
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* !(__LINUX_SPARC_PSR_H) */
#include <uapi/asm/ptrace.h>
#if defined(__sparc__) && defined(__arch64__)
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <linux/compiler.h>
#include <linux/threads.h>
{
return regs->u_regs[UREG_I6];
}
-#else /* __ASSEMBLY__ */
-#endif /* __ASSEMBLY__ */
+#else /* __ASSEMBLER__ */
+#endif /* __ASSEMBLER__ */
#else /* (defined(__sparc__) && defined(__arch64__)) */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <asm/switch_to.h>
static inline bool pt_regs_is_syscall(struct pt_regs *regs)
#define instruction_pointer(regs) ((regs)->pc)
#define user_stack_pointer(regs) ((regs)->u_regs[UREG_FP])
unsigned long profile_pc(struct pt_regs *);
-#else /* (!__ASSEMBLY__) */
-#endif /* (!__ASSEMBLY__) */
+#else /* (!__ASSEMBLER__) */
+#endif /* (!__ASSEMBLER__) */
#endif /* (defined(__sparc__) && defined(__arch64__)) */
#define STACK_BIAS 2047
#define HYPERSPARC_ICCR_FTD 0x00000002
#define HYPERSPARC_ICCR_ICE 0x00000001
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
static inline unsigned int get_ross_icr(void)
{
}
}
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* !(_SPARC_ROSS_H) */
*/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
static inline int acquire_sbi(int devid, int mask)
{
"i" (ASI_M_CTL));
}
-#endif /* !__ASSEMBLY__ */
+#endif /* !__ASSEMBLER__ */
#endif /* !(_SPARC_SBI_H) */
#include <asm/ptrace.h>
#include <uapi/asm/sigcontext.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#define __SUNOS_MAXWIN 31
#endif /* (CONFIG_SPARC64) */
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* !(__SPARC_SIGCONTEXT_H) */
#ifndef __SPARC_SIGNAL_H
#define __SPARC_SIGNAL_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <linux/personality.h>
#include <linux/types.h>
#endif
#include <uapi/asm/signal.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#define __ARCH_HAS_KA_RESTORER
#define __ARCH_HAS_SA_RESTORER
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* !(__SPARC_SIGNAL_H) */
#include <linux/threads.h>
#include <asm/head.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <linux/cpumask.h>
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
#ifdef CONFIG_SMP
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <asm/ptrace.h>
#include <asm/asi.h>
void smp_setup_cpu_possible_map(void);
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
/* Sparc specific messages. */
#define MSG_CROSS_CALL 0x0005 /* run func on cpus */
#include <asm/starfire.h>
#include <asm/spitfire.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <linux/cpumask.h>
#include <linux/cache.h>
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#ifdef CONFIG_SMP
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/*
* Private routines/data
void __cpu_die(unsigned int cpu);
#endif
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#else
#ifndef __SPARC_SPINLOCK_H
#define __SPARC_SPINLOCK_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <asm/psr.h>
#include <asm/barrier.h>
res; \
})
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* __SPARC_SPINLOCK_H */
#ifndef __SPARC64_SPINLOCK_H
#define __SPARC64_SPINLOCK_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <asm/processor.h>
#include <asm/barrier.h>
#include <asm/qspinlock.h>
#include <asm/qrwlock.h>
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* !(__SPARC64_SPINLOCK_H) */
#define CPU_ID_M8 ('8')
#define CPU_ID_SONOMA1 ('N')
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
enum ultra_tlb_layout {
spitfire = 0,
"i" (ASI_ITLB_DATA_ACCESS));
}
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* CONFIG_SPARC64 */
#endif /* !(_SPARC64_SPITFIRE_H) */
#ifndef _SPARC64_STARFIRE_H
#define _SPARC64_STARFIRE_H
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
extern int this_is_starfire;
#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <asm/ptrace.h>
#include <asm/page.h>
*/
#define THREAD_SIZE_ORDER 1
-#endif /* __ASSEMBLY__ */
+#endif /* __ASSEMBLER__ */
/* Size of kernel stack for each process */
#define THREAD_SIZE (2 * PAGE_SIZE)
#include <asm/page.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <asm/ptrace.h>
#include <asm/types.h>
__attribute__ ((aligned(64)));
};
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
/* offsets into the thread_info struct for assembly code access */
#define TI_TASK 0x00000000
/*
* macros/functions for gaining access to the thread information structure
*/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#define INIT_THREAD_INFO(tsk) \
{ \
#define set_thread_fpdepth(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_FPDEPTH] = (val))
#define get_thread_wsaved() (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSAVED])
#define set_thread_wsaved(val) (__cur_thread_flag_byte_ptr[TI_FLAG_BYTE_WSAVED] = (val))
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
/*
* Thread information flags, only 16 bits are available as we encode
* Note that there are only 8 bits available.
*/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#define thread32_stack_is_64bit(__SP) (((__SP) & 0x1) != 0)
#define test_thread_64bit_stack(__SP) \
((test_thread_flag(TIF_32BIT) && !thread32_stack_is_64bit(__SP)) ? \
false : true)
-#endif /* !__ASSEMBLY__ */
+#endif /* !__ASSEMBLER__ */
#endif /* __KERNEL__ */
#include <asm/hypervisor.h>
#include <asm/asi.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* Trap handling code needs to get at a few critical values upon
* trap entry and to process TSB misses. These cannot be in the
__sun_m7_2insn_patch_end;
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#define TRAP_PER_CPU_THREAD 0x00
#define TRAP_PER_CPU_PGD_PADDR 0x08
#include <uapi/asm/traps.h>
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* This is for V8 compliant Sparc CPUS */
struct tt_entry {
unsigned long inst_one;
/* We set this to _start in system setup. */
extern struct tt_entry *sparc_ttable;
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* !(_SPARC_TRAPS_H) */
* The kernel TSB is locked into the TLB by virtue of being in the
* kernel image, so we don't play these games for swapper_tsb access.
*/
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
struct tsb_ldquad_phys_patch_entry {
unsigned int addr;
unsigned int sun4u_insn;
#include <asm/utrap.h>
#include <asm/pil.h>
-#ifdef __ASSEMBLY__
+#ifdef __ASSEMBLER__
#include <asm/thread_info.h>
#endif
#define TURBOSPARC_WTENABLE 0x00000020 /* Write thru for dcache */
#define TURBOSPARC_SNENABLE 0x40000000 /* DVMA snoop enable */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
/* Bits [13:5] select one of 512 instruction cache tags */
static inline void turbosparc_inv_insn_tag(unsigned long addr)
return regval;
}
-#endif /* !__ASSEMBLY__ */
+#endif /* !__ASSEMBLER__ */
#endif /* !(_SPARC_TURBOSPARC_H) */
#define UPA_PORTID_ID 0x000000000000ffff /* Module Identification bits */
/* UPA I/O space accessors */
-#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+#if defined(__KERNEL__) && !defined(__ASSEMBLER__)
static inline unsigned char _upa_readb(unsigned long addr)
{
unsigned char ret;
#define upa_writew(__w, __addr) (_upa_writew((__w), (unsigned long)(__addr)))
#define upa_writel(__l, __addr) (_upa_writel((__l), (unsigned long)(__addr)))
#define upa_writeq(__q, __addr) (_upa_writeq((__q), (unsigned long)(__addr)))
-#endif /* __KERNEL__ && !__ASSEMBLY__ */
+#endif /* __KERNEL__ && !__ASSEMBLER__ */
#endif /* !(_SPARC64_UPA_H) */
*/
#define SRMMU_NOCACHE_ALCRATIO 64 /* 256 pages per 64MB of system RAM */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
#include <asm/kmap_size.h>
enum fixed_addresses {
#define VIKING_PTAG_DIRTY 0x00010000 /* Block has been modified */
#define VIKING_PTAG_SHARED 0x00000100 /* Shared with some other cache */
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
static inline void viking_flush_icache(void)
{
return val;
}
-#endif /* !__ASSEMBLY__ */
+#endif /* !__ASSEMBLER__ */
#endif /* !(_SPARC_VIKING_H) */
#define VISExitHalfFast \
wr %o5, 0, %fprs;
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
static inline void save_and_clear_fpu(void) {
__asm__ __volatile__ (
" rd %%fprs, %%o5\n"
#define HV_RNG_NUM_CONTROL 4
-#ifndef __ASSEMBLY__
+#ifndef __ASSEMBLER__
extern unsigned long sun4v_rng_get_diag_ctl(void);
extern unsigned long sun4v_rng_ctl_read_v1(unsigned long ctl_regs_ra,
unsigned long *state,
#define N2RNG_BUSY_LIMIT 100
#define N2RNG_HCHECK_LIMIT 100
-#endif /* !(__ASSEMBLY__) */
+#endif /* !(__ASSEMBLER__) */
#endif /* _N2RNG_H */