drm/amdgpu: add se registers to ip dump for gfx10

add the registers of SE block of gfx for ip dump
for gfx10 IP.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 61c1e997f794878ba3a5e412ff8b7273597004e7..953df202953a8b65a4fcd77761f72686d334b14d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -373,7 +373,12 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
        SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
        SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
        SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
-       SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP)
+       SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),
+       /* SE status registers */
+       SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
+       SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
+       SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
+       SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
 };
 
 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {