drm/xe/xe2: Extend performance tuning to media GT

With exception of "Tuning: L3 cache - media", we are currently applying
recommended performance tuning settings only for the primary GT. Let's
also implement them for the media GT when applicable.

According to our spec, media GT registers CCCHKNREG1 and L3SQCREG* exist
only in Xe2_LPM and their offsets do not match their primary GT
counterparts. Furthermore, the range where CCCHKNREG1 belongs is not
listed as a multicast range on the media GT. As such, we need to have
Xe2_LPM-specific definitions for those registers and apply the setting
only for that specific IP.

Both Xe2_HPM and Xe2_LPM contain STATELESS_COMPRESSION_CTRL and the
offset on the media GT matches the one on the primary one. So we can
simply have a copy of "Tuning: Stateless compression control" for the
media GT.

v2:
  - Fix implementation with respect to multicast vs non-multicast
    registers. (Matt)
  - Add missing XE2LPM_CCCHKNREG1 on second action of "Tuning:
    Compression Overfetch - media".
v3:
  - STATELESS_COMPRESSION_CTRL on Xe2_HPM is also a multicast register,
    do not define a XE2HPM_STATELESS_COMPRESSION_CTRL register. (Tejas)

Bspec: 72161
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240920211459.255181-3-gustavo.sousa@intel.com
(cherry picked from commit e1f813947ccf2326cfda4558b7d31430d7860c4b)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 660ff42e45a6f44097419d3c769d5f156583fb8b..5a1d4639e916d47351548d209b71e020cc09f2f8 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -169,6 +169,8 @@
 #define XEHP_SLICE_COMMON_ECO_CHICKEN1         XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED)
 #define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE   REG_BIT(14)
 
+#define XE2LPM_CCCHKNREG1                      XE_REG(0x82a8)
+
 #define VF_PREEMPTION                          XE_REG(0x83a4, XE_REG_OPTION_MASKED)
 #define   PREEMPTION_VERTEX_COUNT              REG_GENMASK(15, 0)
 
@@ -391,6 +393,10 @@
 #define SCRATCH1LPFC                           XE_REG(0xb474)
 #define   EN_L3_RW_CCS_CACHE_FLUSH             REG_BIT(0)
 
+#define XE2LPM_L3SQCREG2                       XE_REG_MCR(0xb604)
+
+#define XE2LPM_L3SQCREG3                       XE_REG_MCR(0xb608)
+
 #define XE2LPM_L3SQCREG5                       XE_REG_MCR(0xb658)
 
 #define XE2_TDF_CTRL                           XE_REG(0xb418)

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index faa1bf42e50edf7011060ae21a3d827ed02cd6b3..c798ae1b3f750f84cd59357638c660cbd45c3194 100644 (file)
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -42,20 +42,40 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
          XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
                         SET(CCCHKNREG1, L3CMPCTRL))
        },
+       { XE_RTP_NAME("Tuning: Compression Overfetch - media"),
+         XE_RTP_RULES(MEDIA_VERSION(2000)),
+         XE_RTP_ACTIONS(CLR(XE2LPM_CCCHKNREG1, ENCOMPPERFFIX),
+                        SET(XE2LPM_CCCHKNREG1, L3CMPCTRL))
+       },
        { XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
          XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
        },
+       { XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3 - media"),
+         XE_RTP_RULES(MEDIA_VERSION(2000)),
+         XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
+       },
        { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
          XE_RTP_ACTIONS(SET(L3SQCREG2,
                             COMPMEMRD256BOVRFETCHEN))
        },
+       { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
+         XE_RTP_RULES(MEDIA_VERSION(2000)),
+         XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
+                            COMPMEMRD256BOVRFETCHEN))
+       },
        { XE_RTP_NAME("Tuning: Stateless compression control"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
          XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
                                   REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
        },
+       { XE_RTP_NAME("Tuning: Stateless compression control - media"),
+         XE_RTP_RULES(MEDIA_VERSION_RANGE(1301, 2000)),
+         XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
+                                  REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
+       },
+
        {}
 };