The kernel does this along the return path to user mode.
Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
{
- regs->iaoq[0] = infop->entry;
- regs->iaoq[1] = infop->entry + 4;
+ regs->iaoq[0] = infop->entry | PRIV_USER;
+ regs->iaoq[1] = regs->iaoq[0] + 4;
regs->gr[23] = 0;
regs->gr[24] = infop->argv;
regs->gr[25] = infop->argc;
default:
env->gr[28] = ret;
/* We arrived here by faking the gateway page. Return. */
- env->iaoq_f = env->gr[31];
- env->iaoq_b = env->gr[31] + 4;
+ env->iaoq_f = env->gr[31] | PRIV_USER;
+ env->iaoq_b = env->iaoq_f + 4;
break;
case -QEMU_ERESTARTSYS:
case -QEMU_ESIGRETURN:
case EXCP_SYSCALL_LWS:
env->gr[21] = hppa_lws(env);
/* We arrived here by faking the gateway page. Return. */
- env->iaoq_f = env->gr[31];
- env->iaoq_b = env->gr[31] + 4;
+ env->iaoq_f = env->gr[31] | PRIV_USER;
+ env->iaoq_b = env->iaoq_f + 4;
break;
case EXCP_IMP:
force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, env->iaoq_f);
case EXCP_PRIV_OPR:
/* check for glibc ABORT_INSTRUCTION "iitlbp %r0,(%sr0, %r0)" */
if (env->cr[CR_IIR] == 0x04000000) {
- force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f);
+ force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f);
} else {
- force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->iaoq_f);
+ force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->iaoq_f);
}
break;
case EXCP_PRIV_REG:
force_sig_fault(TARGET_SIGFPE, 0, env->iaoq_f);
break;
case EXCP_BREAK:
- force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f & ~3);
+ force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f);
break;
case EXCP_DEBUG:
force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f);
cpu_hppa_loaded_fr0(env);
__get_user(env->iaoq_f, &sc->sc_iaoq[0]);
+ env->iaoq_f |= PRIV_USER;
__get_user(env->iaoq_b, &sc->sc_iaoq[1]);
+ env->iaoq_b |= PRIV_USER;
__get_user(env->cr[CR_SAR], &sc->sc_sar);
}
unlock_user(fdesc, haddr, 0);
haddr = dest;
}
- env->iaoq_f = haddr;
- env->iaoq_b = haddr + 4;
+ env->iaoq_f = haddr | PRIV_USER;
+ env->iaoq_b = env->iaoq_f + 4;
env->psw_n = 0;
return;
/* Indicate child in return value. */
env->gr[28] = 0;
/* Return from the syscall. */
- env->iaoq_f = env->gr[31];
- env->iaoq_b = env->gr[31] + 4;
+ env->iaoq_f = env->gr[31] | PRIV_USER;
+ env->iaoq_b = env->iaoq_f + 4;
}
static inline void cpu_clone_regs_parent(CPUHPPAState *env, unsigned flags)
{
HPPACPU *cpu = HPPA_CPU(cs);
+#ifdef CONFIG_USER_ONLY
+ value |= PRIV_USER;
+#endif
cpu->env.iaoq_f = value;
cpu->env.iaoq_b = value + 4;
}
tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
#ifdef CONFIG_USER_ONLY
- cpu->env.iaoq_f = tb->pc;
- cpu->env.iaoq_b = tb->cs_base;
+ cpu->env.iaoq_f = tb->pc | PRIV_USER;
+ cpu->env.iaoq_b = tb->cs_base | PRIV_USER;
#else
/* Recover the IAOQ values from the GVA + PRIV. */
uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3;
#define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1)
#define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)
+#define PRIV_KERNEL 0
+#define PRIV_USER 3
+
#define TARGET_INSN_START_EXTRA_WORDS 2
/* No need to flush MMU_ABS*_IDX */
env->cr[CR_SAR] = val & (hppa_is_pa20(env) ? 63 : 31);
break;
case 33:
+#ifdef CONFIG_USER_ONLY
+ val |= PRIV_USER;
+#endif
env->iaoq_f = val;
break;
case 34:
env->iasq_f = (uint64_t)val << 32;
break;
case 35:
+#ifdef CONFIG_USER_ONLY
+ val |= PRIV_USER;
+#endif
env->iaoq_b = val;
break;
case 36:
tcg_gen_st_i64(cpu_gr[26], tcg_env,
offsetof(CPUHPPAState, cr[27]));
- tcg_gen_ori_i64(next.base, cpu_gr[31], 3);
+ tcg_gen_ori_i64(next.base, cpu_gr[31], PRIV_USER);
install_iaq_entries(ctx, &next, NULL);
ctx->base.is_jmp = DISAS_IAQ_N_UPDATED;
}
ctx->is_pa20 = hppa_is_pa20(cpu_env(cs));
#ifdef CONFIG_USER_ONLY
- ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX);
+ ctx->privilege = PRIV_USER;
ctx->mmu_idx = MMU_USER_IDX;
ctx->iaoq_first = ctx->base.pc_first | ctx->privilege;
ctx->iaq_b.disp = ctx->base.tb->cs_base - ctx->base.pc_first;