perf/x86/intel/uncore: Guard against invalid box control address

Theoretically, intel_uncore_find_discovery_unit() could return NULL,
e.g., when a CPU die is offline during uncore enumeration and its PMU
units are not added to the discovery RB-tree.

Guard against a NULL return value and the resulting invalid box control
address (0) before accessing hardware.

Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Link: https://patch.msgid.link/20260602144908.263680-3-zide.chen@intel.com

diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/intel/uncore_discovery.c
index 60e1200c4691d7886f740fbaaedc19e562da2310..af7e80fee81fb1e35a852dff06d119e997c1d3f0 100644 (file)
--- a/arch/x86/events/intel/uncore_discovery.c
+++ b/arch/x86/events/intel/uncore_discovery.c
@@ -490,17 +490,28 @@ static u64 intel_generic_uncore_box_ctl(struct intel_uncore_box *box)
 
 void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box)
 {
-       wrmsrq(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_INT);
+       u64 box_ctl = intel_generic_uncore_box_ctl(box);
+
+       if (!box_ctl)
+               return;
+
+       wrmsrq(box_ctl, GENERIC_PMON_BOX_CTL_INT);
 }
 
 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box)
 {
-       wrmsrq(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ);
+       u64 box_ctl = intel_generic_uncore_box_ctl(box);
+
+       if (box_ctl)
+               wrmsrq(box_ctl, GENERIC_PMON_BOX_CTL_FRZ);
 }
 
 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box)
 {
-       wrmsrq(intel_generic_uncore_box_ctl(box), 0);
+       u64 box_ctl = intel_generic_uncore_box_ctl(box);
+
+       if (box_ctl)
+               wrmsrq(box_ctl, 0);
 }
 
 static void intel_generic_uncore_msr_enable_event(struct intel_uncore_box *box,
@@ -549,6 +560,7 @@ bool intel_generic_uncore_assign_hw_event(struct perf_event *event,
 
        if (box->pci_dev) {
                box_ctl = UNCORE_DISCOVERY_PCI_BOX_CTRL(box_ctl);
+
                hwc->config_base = box_ctl + uncore_pci_event_ctl(box, hwc->idx);
                hwc->event_base  = box_ctl + uncore_pci_perf_ctr(box, hwc->idx);
                return true;
@@ -567,27 +579,30 @@ static inline int intel_pci_uncore_box_ctl(struct intel_uncore_box *box)
 
 void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box)
 {
-       struct pci_dev *pdev = box->pci_dev;
        int box_ctl = intel_pci_uncore_box_ctl(box);
 
+       if (!box_ctl)
+               return;
+
        __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags);
-       pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_INT);
+       pci_write_config_dword(box->pci_dev, box_ctl, GENERIC_PMON_BOX_CTL_INT);
 }
 
 void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box)
 {
-       struct pci_dev *pdev = box->pci_dev;
        int box_ctl = intel_pci_uncore_box_ctl(box);
 
-       pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_FRZ);
+       if (box_ctl)
+               pci_write_config_dword(box->pci_dev, box_ctl,
+                                      GENERIC_PMON_BOX_CTL_FRZ);
 }
 
 void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box)
 {
-       struct pci_dev *pdev = box->pci_dev;
        int box_ctl = intel_pci_uncore_box_ctl(box);
 
-       pci_write_config_dword(pdev, box_ctl, 0);
+       if (box_ctl)
+               pci_write_config_dword(box->pci_dev, box_ctl, 0);
 }
 
 static void intel_generic_uncore_pci_enable_event(struct intel_uncore_box *box,