drm/msm/dpu: drop validity checks for clear_pending_flush() ctl op

clear_pending_flush() ctl op is always assigned irrespective of the DPU
hardware revision. Hence there is no needed to check whether the op has
been assigned before calling it.

Drop the checks across the driver for clear_pending_flush() and also
update its documentation that it is always expected to be assigned.

changes in v2:
	- instead of adding more validity checks just drop the one for clear_pending_flush
	- update the documentation for clear_pending_flush() ctl op
	- update the commit text reflecting these changes

changes in v3:
	- simplify the documentation of clear_pending_flush

Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback")
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Closes: https://lore.kernel.org/all/464fbd84-0d1c-43c3-a40b-31656ac06456@moroto.mountain/T/
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/600241/
Link: https://lore.kernel.org/r/20240620201731.3694593-1-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index dba4f7009a9167531645002224a5e4c20ebd8a7c..dd9c476ee678575646a647bccdccd962feb1e15c 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1743,8 +1743,7 @@ void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
                phys = dpu_enc->phys_encs[i];
 
                ctl = phys->hw_ctl;
-               if (ctl->ops.clear_pending_flush)
-                       ctl->ops.clear_pending_flush(ctl);
+               ctl->ops.clear_pending_flush(ctl);
 
                /* update only for command mode primary ctl */
                if ((phys == dpu_enc->cur_master) &&

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 356dca5e5ea947d5b6e47fd5d94113777feb9009..882c717859cec6dfc4b646200e68a748a5294ac9 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -538,8 +538,7 @@ static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
        }
 
        /* reset h/w before final flush */
-       if (phys_enc->hw_ctl->ops.clear_pending_flush)
-               phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
+       phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
 
        /*
         * New CTL reset sequence from 5.0 MDP onwards.

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index ef56280bea932fe15717f172cd4acb936458eb06..4401fdc0f3e4fe525531f018272613d38f57fd73 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -83,7 +83,8 @@ struct dpu_hw_ctl_ops {
 
        /**
         * Clear the value of the cached pending_flush_mask
-        * No effect on hardware
+        * No effect on hardware.
+        * Required to be implemented.
         * @ctx       : ctl path ctx pointer
         */
        void (*clear_pending_flush)(struct dpu_hw_ctl *ctx);