riscv: lib: Split out support for T-Head cache management operations

Designed before a standard set of cache management operations defined in
RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the
customized extension XTheadCMO, which has been used in the CV1800B port
of U-Boot.

This patch splits XTheadCMO-related code into a generic module, allowing
SoCs shipping T-Head cores to share the code.

Link: https://github.com/XUANTIE-RV/thead-extension-spec
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b24623590f2b43f2cf1fa5834579c05c043c1fcf..dc36d9b856651230b4e41feaa2ad40e092757b8c 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -77,6 +77,14 @@ config SYS_DCACHE_OFF
        help
          Do not enable data cache in U-Boot.
 
+config SYS_CACHE_THEAD_CMO
+       bool "THEAD non-standard cache operations"
+       depends on !SYS_DCACHE_OFF
+       default n
+       help
+         Support for non-standard cache management operations on SoCs based on
+         T-Head C906/C910 cores.
+
 config SPL_SYS_DCACHE_OFF
        bool "Do not enable dcache in SPL"
        depends on SPL

diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig
index 7225b1210c508cee438f12411a631bbee5756bcb..57f724ae043e17423a97360eda0961a7e55cd679 100644 (file)
--- a/arch/riscv/cpu/cv1800b/Kconfig
+++ b/arch/riscv/cpu/cv1800b/Kconfig
@@ -6,6 +6,7 @@ config SOPHGO_CV1800B
        bool
        select ARCH_EARLY_INIT_R
        select SYS_CACHE_SHIFT_6
+       select SYS_CACHE_THEAD_CMO
        imply CPU
        imply CPU_RISCV
        imply RISCV_TIMER

diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile
index 95beb34b51af76b41c53ef513f5b3a984fdc1a42..da12e0f64e1b8b6c13abafc89633f626c5ff739d 100644 (file)
--- a/arch/riscv/cpu/cv1800b/Makefile
+++ b/arch/riscv/cpu/cv1800b/Makefile
@@ -4,4 +4,3 @@
 
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 189b35c24d39b5aecc09ec0d68cde5a00cd5e818..db8d235c6993a8fd78b09acf50f14776615d5269 100644 (file)
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y  += cache.o
 obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
+obj-$(CONFIG_SYS_CACHE_THEAD_CMO) += thead_cmo.o
 ifeq ($(CONFIG_$(PHASE_)RISCV_MMODE),y)
 obj-$(CONFIG_$(PHASE_)RISCV_ACLINT) += aclint_ipi.o
 obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o

diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/lib/thead_cmo.c
similarity index 100%
rename from arch/riscv/cpu/cv1800b/cache.c
rename to arch/riscv/lib/thead_cmo.c