ARM: dts: imx6ull-seeed-npi: fix fsl,pins property in tscgrp pinctrl

The property is "fsl,pins", not "fsl,pin".  Wrong property means the pin
configuration was not applied.  Fixes dtbs_check warnings:

  imx6ull-seeed-npi-dev-board-emmc.dtb: pinctrl@20e0000: uart1grp: 'fsl,pins' is a required property
  imx6ull-seeed-npi-dev-board-emmc.dtb: pinctrl@20e0000: uart1grp: 'fsl,pin' does not match any of the regexes: 'pinctrl-[0-9]+'

Cc: stable@vger.kernel.org
Fixes: e3b5697195c8 ("ARM: dts: imx6ull: add seeed studio NPi dev board")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Parthiban Nallathambi <parthiban@linumiz.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
index 6bb12e0bbc7ec625920265e57140d360bd80cc4d..50654dbf62e02ce1ba80f1a9ac32887e08b16b13 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
@@ -339,14 +339,14 @@
        };
 
        pinctrl_uart1: uart1grp {
-               fsl,pin = <
+               fsl,pins = <
                        MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
                        MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
                >;
        };
 
        pinctrl_uart2: uart2grp {
-               fsl,pin = <
+               fsl,pins = <
                        MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
                        MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
                        MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS    0x1b0b1
@@ -355,7 +355,7 @@
        };
 
        pinctrl_uart3: uart3grp {
-               fsl,pin = <
+               fsl,pins = <
                        MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x1b0b1
                        MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX   0x1b0b1
                        MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS    0x1b0b1
@@ -364,21 +364,21 @@
        };
 
        pinctrl_uart4: uart4grp {
-               fsl,pin = <
+               fsl,pins = <
                        MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX   0x1b0b1
                        MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX   0x1b0b1
                >;
        };
 
        pinctrl_uart5: uart5grp {
-               fsl,pin = <
+               fsl,pins = <
                        MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX   0x1b0b1
                        MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX   0x1b0b1
                >;
        };
 
        pinctrl_usb_otg1_id: usbotg1idgrp {
-               fsl,pin = <
+               fsl,pins = <
                        MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
                >;
        };