combine cmps with shifts

2009-08-24  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

       * gcc.target/arm/combine-cmp-shift.c: New test.

2009-08-24  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

       * config/arm/arm.c (arm_select_cc_mode): Handle subreg.

From-SVN: r151050

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f4155754d6a0ef403f0bcd0f0f9b69e491ae64bd..fc6fa1ece8f438761d5d5fd464f47305a488fdbd 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2009-08-24  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+       * config/arm/arm.c (arm_select_cc_mode): Handle subreg.
+
 2009-08-24  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 
         * config/arm/vfp.md (*arm_movdi_vfp): Mark as predicable.

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3c7e67ed94c43cc94b3d64323e27f187a65ef3c5..0d53896aee0837effa2c376b2ed7b160ac98e99a 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -9504,7 +9504,8 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
 
   /* A compare with a shifted operand.  Because of canonicalization, the
      comparison will have to be swapped when we emit the assembler.  */
-  if (GET_MODE (y) == SImode && GET_CODE (y) == REG
+  if (GET_MODE (y) == SImode 
+      && (REG_P (y) || (GET_CODE (y) == SUBREG))
       && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
          || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
          || GET_CODE (x) == ROTATERT))
@@ -9512,7 +9513,8 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
 
   /* This operation is performed swapped, but since we only rely on the Z
      flag we don't need an additional mode.  */
-  if (GET_MODE (y) == SImode && REG_P (y)
+  if (GET_MODE (y) == SImode 
+      && (REG_P (y) || (GET_CODE (y) == SUBREG))
       && GET_CODE (x) == NEG
       && (op ==        EQ || op == NE))
     return CC_Zmode;

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 896c6819e579fdd30d13fc4b4b5ae2c31682d2b7..3716a9058ba9eb5ba915dee56c9d88552aa8c281 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2009-08-11  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+       * gcc.target/arm/combine-cmp-shift.c: New test.
+
 2009-08-24  Kai Tietz  <kai.tietz@onevision.com>
 
        *gcc.dg/format/ms-format1.c: Add new cases for I32

diff --git a/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c b/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c
new file mode 100644 (file)
index 0000000..1cacc29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c
@@ -0,0 +1,15 @@
+/* { dg-options "-O2 -mcpu=cortex-a8" }  */
+/* { dg-final { scan-assembler "cmp\tr\[0-9\]*, r\[0-9\]*, asr #31" } } */
+
+typedef int SItype __attribute__ ((mode (SI)));
+typedef int DItype __attribute__ ((mode (DI)));
+void abort (void);
+
+SItype
+__mulvsi3 (SItype a, SItype b)
+{
+  const DItype w = (DItype) a * (DItype) b;
+  if ((SItype) (w >> (4 * 8)) != (SItype) w >> ((4 * 8) - 1))
+    abort ();
+  return w;
+}