drm/i915/dp: Clear VSC SDP during post ddi disable routine

Clear VSC SDP if intel_dp_set_infoframes is called from post ddi disable
routine i.e with the variable of enable as false. This is to avoid
an infoframes.enable mismatch issue which is caused when pipe is
connected to eDp which has psr then connected to DPMST. In this case
eDp's post ddi disable routine does not clear infoframes.enable VSC
for the given pipe and DPMST does not recompute VSC SDP and write
infoframes.enable which causes a mismatch.

--v2
-Make the comment match the code [Jani]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240724163743.3668407-1-suraj.kandpal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 116041f3886af49a1f2d61797bb7f79db81ca741..5d6568c8e186c603cbb5fc536f479359c796eabe 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4369,8 +4369,11 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
        if (!enable && HAS_DSC(dev_priv))
                val &= ~VDIP_ENABLE_PPS;
 
-       /* When PSR is enabled, this routine doesn't disable VSC DIP */
-       if (!crtc_state->has_psr)
+       /*
+        * This routine disables VSC DIP if the function is called
+        * to disable SDP or if it does not have PSR
+        */
+       if (!enable || !crtc_state->has_psr)
                val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
 
        intel_de_write(dev_priv, reg, val);