iommu/arm-smmu: Add ACTLR data and support for qcom_smmu_500

Add ACTLR data table for qcom_smmu_500 including corresponding data
entry and set prefetch value by way of a list of compatible strings.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Link: https://lore.kernel.org/r/20241212151402.159102-6-quic_bibekkum@quicinc.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index b524d19e52f7f3a9ba8a719e92e6bae0edc74cde..59d02687280e8d37b5e944619fcfe4ebd1bd6926 100644 (file)
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -16,8 +16,40 @@
 
 #define QCOM_DUMMY_VAL -1
 
+/*
+ * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
+ * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch
+ * buffer). The remaining bits are implementation defined and vary across
+ * SoCs.
+ */
+
+#define CPRE                   (1 << 1)
+#define CMTLB                  (1 << 0)
+#define PREFETCH_SHIFT         8
+#define PREFETCH_DEFAULT       0
+#define PREFETCH_SHALLOW       (1 << PREFETCH_SHIFT)
+#define PREFETCH_MODERATE      (2 << PREFETCH_SHIFT)
+#define PREFETCH_DEEP          (3 << PREFETCH_SHIFT)
 #define GFX_ACTLR_PRR          (1 << 5)
 
+static const struct of_device_id qcom_smmu_actlr_client_of_match[] = {
+       { .compatible = "qcom,adreno",
+                       .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
+       { .compatible = "qcom,adreno-gmu",
+                       .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
+       { .compatible = "qcom,adreno-smmu",
+                       .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
+       { .compatible = "qcom,fastrpc",
+                       .data = (const void *) (PREFETCH_DEEP | CPRE | CMTLB) },
+       { .compatible = "qcom,sc7280-mdss",
+                       .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
+       { .compatible = "qcom,sc7280-venus",
+                       .data = (const void *) (PREFETCH_SHALLOW | CPRE | CMTLB) },
+       { .compatible = "qcom,sm8550-mdss",
+                       .data = (const void *) (PREFETCH_DEFAULT | CMTLB) },
+       { }
+};
+
 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
 {
        return container_of(smmu, struct qcom_smmu, smmu);
@@ -635,6 +667,7 @@ static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
        .impl = &qcom_smmu_500_impl,
        .adreno_impl = &qcom_adreno_smmu_500_impl,
        .cfg = &qcom_smmu_impl0_cfg,
+       .client_match = qcom_smmu_actlr_client_of_match,
 };
 
 /*