]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
drop net-mvpp2-set-dma-mask-and-coherent-dma-mask-on-ppv2.2.patch from 4.4 as well
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 21 Mar 2018 13:12:36 +0000 (14:12 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 21 Mar 2018 13:12:36 +0000 (14:12 +0100)
queue-4.4/net-mvpp2-set-dma-mask-and-coherent-dma-mask-on-ppv2.2.patch [deleted file]
queue-4.4/series

diff --git a/queue-4.4/net-mvpp2-set-dma-mask-and-coherent-dma-mask-on-ppv2.2.patch b/queue-4.4/net-mvpp2-set-dma-mask-and-coherent-dma-mask-on-ppv2.2.patch
deleted file mode 100644 (file)
index e42654e..0000000
+++ /dev/null
@@ -1,48 +0,0 @@
-From foo@baz Mon Mar 19 09:58:12 CET 2018
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Date: Tue, 7 Mar 2017 16:53:19 +0100
-Subject: net: mvpp2: set dma mask and coherent dma mask on PPv2.2
-
-From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-
-
-[ Upstream commit 2067e0a13cfe0b1bdca7b91bc5e4f2740b07d478 ]
-
-On PPv2.2, the streaming mappings can be anywhere in the first 40 bits
-of the physical address space. However, for the coherent mappings, we
-still need them to be in the first 32 bits of the address space,
-because all BM pools share a single register to store the high 32 bits
-of the BM pool address, which means all BM pools must be allocated in
-the same 4GB memory area.
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
-Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/net/ethernet/marvell/mvpp2.c |   14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/net/ethernet/marvell/mvpp2.c
-+++ b/drivers/net/ethernet/marvell/mvpp2.c
-@@ -6448,6 +6448,20 @@ static int mvpp2_probe(struct platform_d
-       /* Get system's tclk rate */
-       priv->tclk = clk_get_rate(priv->pp_clk);
-+      if (priv->hw_version == MVPP22) {
-+              err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));
-+              if (err)
-+                      goto err_mg_clk;
-+              /* Sadly, the BM pools all share the same register to
-+               * store the high 32 bits of their address. So they
-+               * must all have the same high 32 bits, which forces
-+               * us to restrict coherent memory to DMA_BIT_MASK(32).
-+               */
-+              err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
-+              if (err)
-+                      goto err_mg_clk;
-+      }
-+
-       /* Initialize network controller */
-       err = mvpp2_init(pdev, priv);
-       if (err < 0) {
index 194da3b8d74e591192fa8e1ffe8512a613ba1bf0..4eeb56cc1570b755fc9cb66b2aedad65543e5368 100644 (file)
@@ -5,7 +5,6 @@ staging-wilc1000-add-check-for-kmalloc-allocation-failure.patch
 hid-reject-input-outside-logical-range-only-if-null-state-is-set.patch
 drm-qxl-don-t-alloc-fbdev-if-emulation-is-not-supported.patch
 ath10k-fix-a-warning-during-channel-switch-with-multiple-vaps.patch
-net-mvpp2-set-dma-mask-and-coherent-dma-mask-on-ppv2.2.patch
 pci-msi-stop-disabling-msi-msi-x-in-pci_device_shutdown.patch
 selinux-check-for-address-length-in-selinux_socket_bind.patch
 perf-sort-fix-segfault-with-basic-block-cycles-sort-dimension.patch