]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amdgpu: Remove gfxoff usage
authorLijo Lazar <lijo.lazar@amd.com>
Wed, 27 Nov 2024 06:08:41 +0000 (11:38 +0530)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 10 Dec 2024 15:26:50 +0000 (10:26 -0500)
GFXOFF is not valid for these IP versions. Also, SDMA v4.4.2 is not in
GFX domain.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

index 58541b93580ab9036fcfd4170e3b0a02699242ea..8eccb080d56f6e95420845f90f4bfd5fe8d5ab86 100644 (file)
@@ -4657,7 +4657,6 @@ static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block)
 
        num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 
-       amdgpu_gfx_off_ctrl(adev, false);
        for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
                xcc_offset = xcc_id * reg_count;
                for (i = 0; i < reg_count; i++)
@@ -4665,7 +4664,6 @@ static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block)
                                RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i],
                                                                   GET_INST(GC, xcc_id)));
        }
-       amdgpu_gfx_off_ctrl(adev, true);
 
        /* dump compute queue registers for all instances */
        if (!adev->gfx.ip_dump_compute_queues)
@@ -4674,7 +4672,6 @@ static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block)
        num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
                adev->gfx.mec.num_queue_per_pipe;
        reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3);
-       amdgpu_gfx_off_ctrl(adev, false);
        mutex_lock(&adev->srbm_mutex);
        for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
                xcc_offset = xcc_id * reg_count * num_inst;
@@ -4701,7 +4698,6 @@ static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block)
        }
        soc15_grbm_select(adev, 0, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
-       amdgpu_gfx_off_ctrl(adev, true);
 }
 
 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
index e1674da07c232ea3bc235d0792b06de612ba8ce2..ef6f852d43dde9e1e5e6352a87c911c638d71c07 100644 (file)
@@ -1950,7 +1950,6 @@ static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block)
        if (!adev->sdma.ip_dump)
                return;
 
-       amdgpu_gfx_off_ctrl(adev, false);
        for (i = 0; i < adev->sdma.num_instances; i++) {
                instance_offset = i * reg_count;
                for (j = 0; j < reg_count; j++)
@@ -1958,7 +1957,6 @@ static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block)
                                RREG32(sdma_v4_4_2_get_reg_offset(adev, i,
                                       sdma_reg_list_4_4_2[j].reg_offset));
        }
-       amdgpu_gfx_off_ctrl(adev, true);
 }
 
 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {