riscv: dts: microchip: add an initial devicetree for the BeagleV Fire

Add an initial devicetree for the BeagleV Fire. This devicetree differs
from that in the BeagleBoard BSP as it has a different memory
configuration, however it will boot on the same FPGA images. PCI is
disabled for now, as the Linux PCI driver (and the binding) assume
which root port instance is in use. This will need to be fixed before
PCI can be enabled.

Link: https://www.beagleboard.org/boards/beaglev-fire
Co-developed-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index e177815bf1a2f56937141d696d90383558e89bf6..f51aeeb9fd3b34fbb32bb31c88e2847495599221 100644 (file)
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb

diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi
new file mode 100644 (file)
index 0000000..e153eaf
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+       fabric_clk3: fabric-clk3 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <50000000>;
+       };
+
+       fabric_clk1: fabric-clk1 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <125000000>;
+       };
+
+       fabric-bus@40000000 {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */
+                        <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
+                        <0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
+                        <0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */
+                        <0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */
+
+               cape_gpios_p8: gpio@41100000 {
+                       compatible = "microchip,coregpio-rtl-v3";
+                       reg = <0x0 0x41100000 0x0 0x1000>;
+                       clocks = <&fabric_clk3>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       ngpios = <16>;
+                       gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34",
+                                         "P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38",
+                                         "P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42",
+                                         "P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46";
+               };
+
+               cape_gpios_p9: gpio@41200000 {
+                       compatible = "microchip,coregpio-rtl-v3";
+                       reg = <0x0 0x41200000 0x0 0x1000>;
+                       clocks = <&fabric_clk3>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       ngpios = <20>;
+                       gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14",
+                                         "P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18",
+                                         "P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24",
+                                         "P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28",
+                                         "P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42";
+               };
+
+               hsi_gpios: gpio@44000000 {
+                       compatible = "microchip,coregpio-rtl-v3";
+                       reg = <0x0 0x44000000 0x0 0x1000>;
+                       clocks = <&fabric_clk3>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       ngpios = <20>;
+                       gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N",
+                                         "B0_HSIO73N_C2P_CLKN", "B0_HSIO70P", "B0_HSIO71P",
+                                         "B0_HSIO83P", "B0_HSIO73N_C2P_CLKP", "XCVR1_RX_VALID",
+                                         "XCVR1_LOCK", "XCVR1_ERROR", "XCVR2_RX_VALID",
+                                         "XCVR2_LOCK", "XCVR2_ERROR", "XCVR3_RX_VALID",
+                                         "XCVR3_LOCK", "XCVR3_ERROR", "XCVR_0B_REF_CLK_PLL_LOCK",
+                                         "XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N";
+               };
+       };
+
+       refclk_ccc: cccrefclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+       };
+};
+
+&ccc_nw {
+       clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
+                <&refclk_ccc>, <&refclk_ccc>;
+       clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
+                     "dll0_ref", "dll1_ref";
+       status = "okay";
+};

diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts
new file mode 100644 (file)
index 0000000..47cf693
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "mpfs.dtsi"
+#include "mpfs-beaglev-fire-fabric.dtsi"
+
+/* Clock frequency (in Hz) of MTIMER */
+#define MTIMER_FREQ            1000000
+
+/ {
+       #address-cells = <2>;
+       #size-cells = <2>;
+       model = "BeagleBoard BeagleV-Fire";
+       compatible = "beagle,beaglev-fire", "microchip,mpfs";
+
+       aliases {
+               serial0 = &mmuart0;
+               serial1 = &mmuart1;
+               serial2 = &mmuart2;
+               serial3 = &mmuart3;
+               serial4 = &mmuart4;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       cpus {
+               timebase-frequency = <MTIMER_FREQ>;
+       };
+
+       ddrc_cache_lo: memory@80000000 {
+               device_type = "memory";
+               reg = <0x0 0x80000000 0x0 0x40000000>;
+               status = "okay";
+       };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               hss: hss-buffer@103fc00000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x10 0x3fc00000 0x0 0x400000>;
+                       no-map;
+               };
+       };
+
+       imx219_clk: camera-clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <24000000>;
+       };
+
+       imx219_vana: fixedregulator-0 {
+               compatible = "regulator-fixed";
+               regulator-name = "imx219_vana";
+               regulator-min-microvolt = <2800000>;
+               regulator-max-microvolt = <2800000>;
+       };
+
+       imx219_vdig: fixedregulator-1 {
+               compatible = "regulator-fixed";
+               regulator-name = "imx219_vdig";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+       };
+
+       imx219_vddl: fixedregulator-2 {
+               compatible = "regulator-fixed";
+               regulator-name = "imx219_vddl";
+               regulator-min-microvolt = <1200000>;
+               regulator-max-microvolt = <1200000>;
+       };
+
+};
+
+&gpio2 {
+       interrupts = <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>;
+       ngpios=<32>;
+       gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2",
+                         "P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5",
+                         "P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8",
+                         "P8_PIN12_USER_LED_9", "P8_PIN13_USER_LED_10", "P8_PIN14_USER_LED_11",
+                         "P8_PIN15", "P8_PIN16", "P8_PIN17", "P8_PIN18", "P8_PIN19", "P8_PIN20",
+                         "P8_PIN21", "P8_PIN22", "P8_PIN23", "P8_PIN24", "P8_PIN25", "P8_PIN26",
+                         "P8_PIN27", "P8_PIN28", "P8_PIN29", "P8_PIN30", "M2_W_DISABLE1",
+                         "M2_W_DISABLE2", "VIO_ENABLE", "SD_DET";
+       status = "okay";
+
+       vio-enable-hog {
+               gpio-hog;
+               gpios = <30 30>;
+               output-high;
+               line-name = "VIO_ENABLE";
+       };
+
+       sd-det-hog {
+               gpio-hog;
+               gpios = <31 31>;
+               input;
+               line-name = "SD_DET";
+       };
+};
+
+&i2c0 {
+       status = "okay";
+};
+
+&i2c1 {
+       status = "okay";
+
+       eeprom: eeprom@50 {
+               compatible = "atmel,24c32";
+               reg = <0x50>;
+       };
+
+       imx219: sensor@10 {
+               compatible = "sony,imx219";
+               reg = <0x10>;
+               clocks = <&imx219_clk>;
+               VANA-supply = <&imx219_vana>;   /* 2.8v */
+               VDIG-supply = <&imx219_vdig>;   /* 1.8v */
+               VDDL-supply = <&imx219_vddl>;   /* 1.2v */
+
+               port {
+                       imx219_0: endpoint {
+                               data-lanes = <1 2>;
+                               clock-noncontinuous;
+                               link-frequencies = /bits/ 64 <456000000>;
+                       };
+               };
+       };
+};
+
+&mac0 {
+       status = "okay";
+       phy-mode = "sgmii";
+       phy-handle = <&phy0>;
+       phy0: ethernet-phy@0 {
+               reg = <0>;
+       };
+};
+
+&mbox {
+       status = "okay";
+};
+
+&mmc {
+       bus-width = <4>;
+       disable-wp;
+       cap-sd-highspeed;
+       cap-mmc-highspeed;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       sd-uhs-sdr12;
+       sd-uhs-sdr25;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+       status = "okay";
+};
+
+&mmuart0 {
+       status = "okay";
+};
+
+&mmuart1 {
+       status = "okay";
+};
+
+&refclk {
+       clock-frequency = <125000000>;
+};
+
+&refclk_ccc {
+       clock-frequency = <50000000>;
+};
+
+&rtc {
+       status = "okay";
+};
+
+&spi0 {
+       status = "okay";
+};
+
+&spi1 {
+       status = "okay";
+};
+
+&syscontroller {
+       microchip,bitstream-flash = <&sys_ctrl_flash>;
+       status = "okay";
+};
+
+&syscontroller_qspi {
+       status = "okay";
+
+       sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
+               compatible = "jedec,spi-nor";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               spi-max-frequency = <20000000>;
+               spi-rx-bus-width = <1>;
+               reg = <0>;
+       };
+};
+
+&usb {
+       status = "okay";
+       dr_mode = "otg";
+};