drm/amd/display: Add clear DCC and Tiling callback for DCE

Introduce the DCC and Tiling reset callback to all DCE versions that can
call it.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index 691b4a68d8ac3ad3134acf0fcfa095901de2a5b9..e6fcc21bb9bce264ddb2f109c25dd521650c6b1f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -290,21 +290,7 @@ void dc_plane_force_dcc_and_tiling_disable(struct dc_plane_state *plane_state,
                if (!pipe_ctx)
                        continue;
 
-               if (dc->ctx->dce_version >= DCE_VERSION_MAX) {
-                       if (dc->hwss.clear_surface_dcc_and_tiling)
-                               dc->hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling);
-               } else {
-                       struct mem_input *mi = pipe_ctx->plane_res.mi;
-                       if (!mi)
-                               continue;
-                       /* if framebuffer is tiled, disable tiling */
-                       if (clear_tiling && mi->funcs->mem_input_clear_tiling)
-                               mi->funcs->mem_input_clear_tiling(mi);
-
-                       /* force page flip to see the new content of the framebuffer */
-                       mi->funcs->mem_input_program_surface_flip_and_addr(mi,
-                                                                          &plane_state->address,
-                                                                          true);
-               }
+               if (dc->hwss.clear_surface_dcc_and_tiling)
+                       dc->hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling);
        }
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
index 1fdeef47e4dccfc0394c848b678d84378dfae3a9..44b56490e1524c0ee7962a8f99b10c91bcd40079 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c
@@ -428,5 +428,6 @@ void dce60_hw_sequencer_construct(struct dc *dc)
        dc->hwss.pipe_control_lock = dce60_pipe_control_lock;
        dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
        dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
+       dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
index b76350a9cf5f59bb4738c79c2119fb7c39b97fb1..0d7e28260db1fd47b16b102ed82c4fc976a351c9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce100/dce100_hwseq.c
@@ -138,6 +138,7 @@ void dce100_hw_sequencer_construct(struct dc *dc)
        dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
        dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
        dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
+       dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;
 }
 
 /**

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 935d08d3a670b41f6b89057658c8b47616983875..8280e3652171f44068a09af7ee3e9912ebe35063 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -33,6 +33,7 @@
 #include "dce110_hwseq.h"
 #include "dce110/dce110_timing_generator.h"
 #include "dce/dce_hwseq.h"
+#include "dce100/dce100_hwseq.h"
 #include "gpio_service_interface.h"
 
 #include "dce110/dce110_compressor.h"
@@ -3332,6 +3333,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
        .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
        .update_plane_addr = update_plane_addr,
        .update_pending_status = dce110_update_pending_status,
+       .clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling,
        .enable_accelerated_mode = dce110_enable_accelerated_mode,
        .enable_timing_synchronization = dce110_enable_timing_synchronization,
        .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
index 22ee304ef9cf7e296841ac7b864314dda8ddfe6e..2a62f63d03572240700ac2998f0a823a455e7b7a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
@@ -29,6 +29,7 @@
 #include "dce120_hwseq.h"
 #include "dce/dce_hwseq.h"
 
+#include "dce100/dce100_hwseq.h"
 #include "dce110/dce110_hwseq.h"
 
 #include "dce/dce_12_0_offset.h"
@@ -264,5 +265,6 @@ void dce120_hw_sequencer_construct(struct dc *dc)
        dce110_hw_sequencer_construct(dc);
        dc->hwseq->funcs.enable_display_power_gating = dce120_enable_display_power_gating;
        dc->hwss.update_dchub = dce120_update_dchub;
+       dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c
index 0a054e880801e7e1e51873221a96bf232767dab8..76fd45550c5e7b04b9d913bd51f7efed5ada568f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c
@@ -50,5 +50,6 @@ void dce80_hw_sequencer_construct(struct dc *dc)
        dc->hwss.pipe_control_lock = dce_pipe_control_lock;
        dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
        dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
+       dc->hwss.clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling;
 }