i386: Emulate MMX smulv4hi3_highpart with SSE

Emulate MMX mulv4hi3 with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow
	TARGET_MMX_WITH_SSE.
	(*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add
	SSE support.

From-SVN: r271219

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index db75ab45b62a65851d3a9ba0279e2b5bcd622f62..7b2a9bb2e5e15c7b7f84303a806435e042483b37 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/89021
+       * config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow
+       TARGET_MMX_WITH_SSE.
+       (*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add
+       SSE support.
+
 2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR target/89021

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index b51f3aceaf5c6c905a4a5103b08c3424c7492d10..d7c3bd45df6a871e6516cf2f788b150d7e1b7c7f 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -773,27 +773,32 @@
          (lshiftrt:V4SI
            (mult:V4SI
              (sign_extend:V4SI
-               (match_operand:V4HI 1 "nonimmediate_operand"))
+               (match_operand:V4HI 1 "register_mmxmem_operand"))
              (sign_extend:V4SI
-               (match_operand:V4HI 2 "nonimmediate_operand")))
+               (match_operand:V4HI 2 "register_mmxmem_operand")))
            (const_int 16))))]
-  "TARGET_MMX"
+  "TARGET_MMX || TARGET_MMX_WITH_SSE"
   "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
 
 (define_insn "*mmx_smulv4hi3_highpart"
-  [(set (match_operand:V4HI 0 "register_operand" "=y")
+  [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
        (truncate:V4HI
          (lshiftrt:V4SI
            (mult:V4SI
              (sign_extend:V4SI
-               (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
+               (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv"))
              (sign_extend:V4SI
-               (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
+               (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")))
            (const_int 16))))]
-  "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
-  "pmulhw\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxmul")
-   (set_attr "mode" "DI")])
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+   && ix86_binary_operator_ok (MULT, V4HImode, operands)"
+  "@
+   pmulhw\t{%2, %0|%0, %2}
+   pmulhw\t{%2, %0|%0, %2}
+   vpmulhw\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxmul,ssemul,ssemul")
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_expand "mmx_umulv4hi3_highpart"
   [(set (match_operand:V4HI 0 "register_operand")