arm64: dts: rockchip: use less broad pinctrl for pcie3x1 on Radxa E25

To avoid conflict with sdmmc_det, change pci3x1 pinctrl-0 name.
Only the reset-pin is actually needed.

Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://lore.kernel.org/r/20240918073236.648-1-naoki@radxa.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
index 1aa3b97e4fd591d4bab3230fce663e930dac1213..98cfa3abb80936610a4da22a0165310715e0ecc8 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
@@ -124,7 +124,7 @@
 &pcie3x1 {
        num-lanes = <1>;
        pinctrl-names = "default";
-       pinctrl-0 = <&pcie30x1m0_pins>;
+       pinctrl-0 = <&pcie30x1_reset_h>;
        reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
        vpcie3v3-supply = <&vcc3v3_minipcie>;
        status = "okay";
@@ -149,6 +149,10 @@
                        rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
                };
 
+               pcie30x1_reset_h: pcie30x1-reset-h {
+                       rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
                pcie30x2_reset_h: pcie30x2-reset-h {
                        rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
                };