]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
arm64: dts: freescale: Add GMAC Ethernet for S32G2 EVB and RDB2 and S32G3 RDB3
authorJan Petrous (OSS) <jan.petrous@oss.nxp.com>
Mon, 3 Nov 2025 09:24:01 +0000 (10:24 +0100)
committerShawn Guo <shawnguo@kernel.org>
Mon, 17 Nov 2025 00:56:56 +0000 (08:56 +0800)
Add support for the Ethernet connection over GMAC controller connected to
the Micrel KSZ9031 Ethernet RGMII PHY located on the boards.

The mentioned GMAC controller is one of two network controllers
embedded on the NXP Automotive SoCs S32G2 and S32G3.

The supported boards:
 * EVB:  S32G-VNP-EVB with S32G2 SoC
 * RDB2: S32G-VNP-RDB2
 * RDB3: S32G-VNP-RDB3

Tested-by: Enric Balletbo i Serra <eballetb@redhat.com>
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/s32g2.dtsi
arch/arm64/boot/dts/freescale/s32g274a-evb.dts
arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
arch/arm64/boot/dts/freescale/s32g3.dtsi
arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts

index d167624d1f0cb2feadb751136ed0d2b568440a5a..51d00dac12deb397a6af0ee98540c1740a405954 100644 (file)
@@ -3,7 +3,7 @@
  * NXP S32G2 SoC family
  *
  * Copyright (c) 2021 SUSE LLC
- * Copyright 2017-2021, 2024 NXP
+ * Copyright 2017-2021, 2024-2025 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
                        status = "disabled";
                };
 
+               gmac0: ethernet@4033c000 {
+                       compatible = "nxp,s32g2-dwmac";
+                       reg = <0x4033c000 0x2000>, /* gmac IP */
+                             <0x4007c004 0x4>;    /* GMAC_0_CTRL_STS */
+                       interrupt-parent = <&gic>;
+                       interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "macirq";
+                       snps,mtl-rx-config = <&mtl_rx_setup>;
+                       snps,mtl-tx-config = <&mtl_tx_setup>;
+                       status = "disabled";
+
+                       mtl_rx_setup: rx-queues-config {
+                               snps,rx-queues-to-use = <5>;
+
+                               queue0 {
+                               };
+
+                               queue1 {
+                               };
+
+                               queue2 {
+                               };
+
+                               queue3 {
+                               };
+
+                               queue4 {
+                               };
+                       };
+
+                       mtl_tx_setup: tx-queues-config {
+                               snps,tx-queues-to-use = <5>;
+
+                               queue0 {
+                               };
+
+                               queue1 {
+                               };
+
+                               queue2 {
+                               };
+
+                               queue3 {
+                               };
+
+                               queue4 {
+                               };
+                       };
+
+                       gmac0mdio: mdio {
+                               compatible = "snps,dwmac-mdio";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+               };
+
                gic: interrupt-controller@50800000 {
                        compatible = "arm,gic-v3";
                        reg = <0x50800000 0x10000>,
index c4a195dd67bf51c7fc2f100040ebe69dfe11b053..aa40a52f8e531ba201c86db647a6ae8e6db8ec2b 100644 (file)
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright (c) 2021 SUSE LLC
- * Copyright 2019-2021, 2024 NXP
+ * Copyright 2019-2021, 2024-2025 NXP
  */
 
 /dts-v1/;
@@ -14,6 +14,7 @@
        compatible = "nxp,s32g274a-evb", "nxp,s32g2";
 
        aliases {
+               ethernet0 = &gmac0;
                serial0 = &uart0;
        };
 
        no-1-8-v;
        status = "okay";
 };
+
+&gmac0 {
+       clocks = <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>;
+       clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
+       phy-mode = "rgmii-id";
+       phy-handle = <&rgmiiaphy4>;
+       status = "okay";
+};
+
+&gmac0mdio {
+       /* KSZ 9031 on RGMII */
+       rgmiiaphy4: ethernet-phy@4 {
+               reg = <4>;
+       };
+};
index 4f58be68c8182f3204d0cb79deffced6abb97206..ee3121b192e53ea4b287d29ed5fb0858565abe2f 100644 (file)
@@ -14,6 +14,7 @@
        compatible = "nxp,s32g274a-rdb2", "nxp,s32g2";
 
        aliases {
+               ethernet0 = &gmac0;
                serial0 = &uart0;
                serial1 = &uart1;
        };
        no-1-8-v;
        status = "okay";
 };
+
+&gmac0 {
+       clocks = <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>;
+       clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
+       phy-mode = "rgmii-id";
+       phy-handle = <&rgmiiaphy1>;
+       status = "okay";
+};
+
+&gmac0mdio {
+       /* KSZ 9031 on RGMII */
+       rgmiiaphy1: ethernet-phy@1 {
+               reg = <1>;
+       };
+};
index be3a582ebc1bf490705d03bf4eb2c300fca5e4a4..eff7673e7f3412ddabf5acec6ae7c98756140242 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 /*
- * Copyright 2021-2024 NXP
+ * Copyright 2021-2025 NXP
  *
  * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
  *          Ciprian Costea <ciprianmarian.costea@nxp.com>
                        status = "disabled";
                };
 
+               gmac0: ethernet@4033c000 {
+                       compatible = "nxp,s32g2-dwmac";
+                       reg = <0x4033c000 0x2000>, /* gmac IP */
+                             <0x4007c004 0x4>;    /* GMAC_0_CTRL_STS */
+                       interrupt-parent = <&gic>;
+                       interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "macirq";
+                       snps,mtl-rx-config = <&mtl_rx_setup>;
+                       snps,mtl-tx-config = <&mtl_tx_setup>;
+                       status = "disabled";
+
+                       mtl_rx_setup: rx-queues-config {
+                               snps,rx-queues-to-use = <5>;
+
+                               queue0 {
+                               };
+
+                               queue1 {
+                               };
+
+                               queue2 {
+                               };
+
+                               queue3 {
+                               };
+
+                               queue4 {
+                               };
+                       };
+
+                       mtl_tx_setup: tx-queues-config {
+                               snps,tx-queues-to-use = <5>;
+
+                               queue0 {
+                               };
+
+                               queue1 {
+                               };
+
+                               queue2 {
+                               };
+
+                               queue3 {
+                               };
+
+                               queue4 {
+                               };
+                       };
+
+                       gmac0mdio: mdio {
+                               compatible = "snps,dwmac-mdio";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+               };
+
                swt8: watchdog@40500000 {
                        compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
                        reg = <40500000 0x1000>;
index e94f70ad82d97866dafbd7bdfbbde7a4f39e9b38..326322b6219210c55496a580740589263530be6c 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 /*
- * Copyright 2021-2024 NXP
+ * Copyright 2021-2025 NXP
  *
  * NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)
  */
@@ -15,6 +15,7 @@
        compatible = "nxp,s32g399a-rdb3", "nxp,s32g3";
 
        aliases {
+               ethernet0 = &gmac0;
                mmc0 = &usdhc0;
                serial0 = &uart0;
                serial1 = &uart1;
        disable-wp;
        status = "okay";
 };
+
+&gmac0 {
+       clocks = <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>;
+       clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
+       phy-mode = "rgmii-id";
+       phy-handle = <&rgmiiaphy1>;
+       status = "okay";
+};
+
+&gmac0mdio {
+       /* KSZ 9031 on RGMII */
+       rgmiiaphy1: ethernet-phy@1 {
+               reg = <1>;
+       };
+};