target-mips: check CP0 enabled for CACHE instruction also in R6

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>

diff --git a/target-mips/translate.c b/target-mips/translate.c
index a5b8805f7772f2a69eeec6b717cfb92569e87697..65f2caff3efacdc08bdb2e73007d4552f52ec53b 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17194,6 +17194,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
         /* Treat as NOP. */
         break;
     case R6_OPC_CACHE:
+        check_cp0_enabled(ctx);
         /* Treat as NOP. */
         break;
     case R6_OPC_SC: