3.15-stable patches

added patches:
	input-elantech-deal-with-clickpads-reporting-right-button-events.patch
	input-elantech-don-t-set-bit-1-of-reg_10-when-the-no_hw_res-quirk-is-set.patch
	input-synaptics-fix-resolution-for-manually-provided-min-max.patch
	mips-msc-prevent-out-of-bounds-writes-to-mips-sc-ioremap-d-region.patch
	mtip32xx-fix-ero-and-nosnoop-values-in-pcie-upstream-on-amd-systems.patch
	mtip32xx-increase-timeout-for-standby-immediate-command.patch
	mtip32xx-remove-dfs_parent-after-pci-unregister.patch
	pci-add-new-id-for-intel-gpu-spurious-interrupt-quirk.patch
	pci-fix-incorrect-vgaarb-conditional-in-warn_on.patch
	recordmcount-mips-fix-possible-incorrect-mcount_loc-table-entries-in-modules.patch
	revert-mips-save-restore-msa-context-around-signals.patch

diff --git a/queue-3.15/input-elantech-deal-with-clickpads-reporting-right-button-events.patch b/queue-3.15/input-elantech-deal-with-clickpads-reporting-right-button-events.patch
new file mode 100644 (file)
index 0000000..8cdc9f1
--- /dev/null
+++ b/queue-3.15/input-elantech-deal-with-clickpads-reporting-right-button-events.patch
@@ -0,0 +1,79 @@
+From cd9e83e2754465856097f31c7ab933ce74c473f8 Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Sat, 7 Jun 2014 22:35:07 -0700
+Subject: Input: elantech - deal with clickpads reporting right button events
+
+From: Hans de Goede <hdegoede@redhat.com>
+
+commit cd9e83e2754465856097f31c7ab933ce74c473f8 upstream.
+
+At least the Dell Vostro 5470 elantech *clickpad* reports right button
+clicks when clicked in the right bottom area:
+
+https://bugzilla.redhat.com/show_bug.cgi?id=1103528
+
+This is different from how (elantech) clickpads normally operate, normally
+no matter where the user clicks on the pad the pad always reports a left
+button event, since there is only 1 hardware button beneath the path.
+
+It looks like Dell has put 2 buttons under the pad, one under each bottom
+corner, causing this.
+
+Since this however still clearly is a real clickpad hardware-wise, we still
+want to report it as such to userspace, so that things like finger movement
+in the bottom area can be properly ignored as it should be on clickpads.
+
+So deal with this weirdness by simply mapping a right click to a left click
+on elantech clickpads. As an added advantage this is something which we can
+simply do on all elantech clickpads, so no need to add special quirks for
+this weird model.
+
+Reported-and-tested-by: Elder Marco <eldermarco@gmail.com>
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/input/mouse/elantech.c |   22 ++++++++++++++++++----
+ 1 file changed, 18 insertions(+), 4 deletions(-)
+
+--- a/drivers/input/mouse/elantech.c
++++ b/drivers/input/mouse/elantech.c
+@@ -473,8 +473,15 @@ static void elantech_report_absolute_v3(
+       input_report_key(dev, BTN_TOOL_FINGER, fingers == 1);
+       input_report_key(dev, BTN_TOOL_DOUBLETAP, fingers == 2);
+       input_report_key(dev, BTN_TOOL_TRIPLETAP, fingers == 3);
+-      input_report_key(dev, BTN_LEFT, packet[0] & 0x01);
+-      input_report_key(dev, BTN_RIGHT, packet[0] & 0x02);
++
++      /* For clickpads map both buttons to BTN_LEFT */
++      if (etd->fw_version & 0x001000) {
++              input_report_key(dev, BTN_LEFT, packet[0] & 0x03);
++      } else {
++              input_report_key(dev, BTN_LEFT, packet[0] & 0x01);
++              input_report_key(dev, BTN_RIGHT, packet[0] & 0x02);
++      }
++
+       input_report_abs(dev, ABS_PRESSURE, pres);
+       input_report_abs(dev, ABS_TOOL_WIDTH, width);
+ 
+@@ -484,10 +491,17 @@ static void elantech_report_absolute_v3(
+ static void elantech_input_sync_v4(struct psmouse *psmouse)
+ {
+       struct input_dev *dev = psmouse->dev;
++      struct elantech_data *etd = psmouse->private;
+       unsigned char *packet = psmouse->packet;
+ 
+-      input_report_key(dev, BTN_LEFT, packet[0] & 0x01);
+-      input_report_key(dev, BTN_RIGHT, packet[0] & 0x02);
++      /* For clickpads map both buttons to BTN_LEFT */
++      if (etd->fw_version & 0x001000) {
++              input_report_key(dev, BTN_LEFT, packet[0] & 0x03);
++      } else {
++              input_report_key(dev, BTN_LEFT, packet[0] & 0x01);
++              input_report_key(dev, BTN_RIGHT, packet[0] & 0x02);
++      }
++
+       input_mt_report_pointer_emulation(dev, true);
+       input_sync(dev);
+ }

diff --git a/queue-3.15/input-elantech-don-t-set-bit-1-of-reg_10-when-the-no_hw_res-quirk-is-set.patch b/queue-3.15/input-elantech-don-t-set-bit-1-of-reg_10-when-the-no_hw_res-quirk-is-set.patch
new file mode 100644 (file)
index 0000000..64fe5da
--- /dev/null
+++ b/queue-3.15/input-elantech-don-t-set-bit-1-of-reg_10-when-the-no_hw_res-quirk-is-set.patch
@@ -0,0 +1,52 @@
+From fb4f8f568a9def02240ef9bf7aabd246dc63a081 Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Sat, 7 Jun 2014 23:07:13 -0700
+Subject: Input: elantech - don't set bit 1 of reg_10 when the no_hw_res quirk is set
+
+From: Hans de Goede <hdegoede@redhat.com>
+
+commit fb4f8f568a9def02240ef9bf7aabd246dc63a081 upstream.
+
+The touchpad on the GIGABYTE U2442 not only stops communicating when we try
+to set bit 3 (enable real hardware resolution) of reg_10, but on some BIOS
+versions also when we set bit 1 (enable two finger mode auto correct).
+
+I've asked the original reporter of:
+https://bugzilla.kernel.org/show_bug.cgi?id=61151
+
+To check that not setting bit 1 does not lead to any adverse effects on his
+model / BIOS revision, and it does not, so this commit fixes the touchpad
+not working on these versions by simply never setting bit 1 for laptop
+models with the no_hw_res quirk.
+
+Reported-and-tested-by: James Lademann <jwlademann@gmail.com>
+Tested-by: Philipp Wolfer <ph.wolfer@gmail.com>
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/input/mouse/elantech.c |    5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/input/mouse/elantech.c
++++ b/drivers/input/mouse/elantech.c
+@@ -849,7 +849,7 @@ static int elantech_set_absolute_mode(st
+               if (etd->set_hw_resolution)
+                       etd->reg_10 = 0x0b;
+               else
+-                      etd->reg_10 = 0x03;
++                      etd->reg_10 = 0x01;
+ 
+               if (elantech_write_reg(psmouse, 0x10, etd->reg_10))
+                       rc = -1;
+@@ -1350,7 +1350,8 @@ static int elantech_reconnect(struct psm
+ }
+ 
+ /*
+- * Some hw_version 3 models go into error state when we try to set bit 3 of r10
++ * Some hw_version 3 models go into error state when we try to set
++ * bit 3 and/or bit 1 of r10.
+  */
+ static const struct dmi_system_id no_hw_res_dmi_table[] = {
+ #if defined(CONFIG_DMI) && defined(CONFIG_X86)

diff --git a/queue-3.15/input-synaptics-fix-resolution-for-manually-provided-min-max.patch b/queue-3.15/input-synaptics-fix-resolution-for-manually-provided-min-max.patch
new file mode 100644 (file)
index 0000000..f4bbb2b
--- /dev/null
+++ b/queue-3.15/input-synaptics-fix-resolution-for-manually-provided-min-max.patch
@@ -0,0 +1,64 @@
+From d49cb7aeebb974713f9f7ab2991352d3050b095b Mon Sep 17 00:00:00 2001
+From: Benjamin Tissoires <benjamin.tissoires@redhat.com>
+Date: Sat, 7 Jun 2014 22:37:47 -0700
+Subject: Input: synaptics - fix resolution for manually provided min/max
+
+From: Benjamin Tissoires <benjamin.tissoires@redhat.com>
+
+commit d49cb7aeebb974713f9f7ab2991352d3050b095b upstream.
+
+commit 421e08c41fda fixed the reported min/max for the X and Y axis,
+but unfortunately, it broke the resolution of those same axis.
+
+On the t540p, the resolution is the same regarding X and Y. It is not
+a problem for xf86-input-synaptics because this driver is only interested
+in the ratio between X and Y.
+Unfortunately, xf86-input-cmt uses directly the resolution, and having a
+null resolution leads to some divide by 0 errors, which are translated by
+-infinity in the resulting coordinates.
+
+Reported-by: Peter Hutterer <peter.hutterer@who-t.net>
+Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/input/mouse/synaptics.c |   19 ++++++++++---------
+ 1 file changed, 10 insertions(+), 9 deletions(-)
+
+--- a/drivers/input/mouse/synaptics.c
++++ b/drivers/input/mouse/synaptics.c
+@@ -347,15 +347,6 @@ static int synaptics_resolution(struct p
+       unsigned char resp[3];
+       int i;
+ 
+-      for (i = 0; min_max_pnpid_table[i].pnp_ids; i++)
+-              if (matches_pnp_id(psmouse, min_max_pnpid_table[i].pnp_ids)) {
+-                      priv->x_min = min_max_pnpid_table[i].x_min;
+-                      priv->x_max = min_max_pnpid_table[i].x_max;
+-                      priv->y_min = min_max_pnpid_table[i].y_min;
+-                      priv->y_max = min_max_pnpid_table[i].y_max;
+-                      return 0;
+-              }
+-
+       if (SYN_ID_MAJOR(priv->identity) < 4)
+               return 0;
+ 
+@@ -366,6 +357,16 @@ static int synaptics_resolution(struct p
+               }
+       }
+ 
++      for (i = 0; min_max_pnpid_table[i].pnp_ids; i++) {
++              if (matches_pnp_id(psmouse, min_max_pnpid_table[i].pnp_ids)) {
++                      priv->x_min = min_max_pnpid_table[i].x_min;
++                      priv->x_max = min_max_pnpid_table[i].x_max;
++                      priv->y_min = min_max_pnpid_table[i].y_min;
++                      priv->y_max = min_max_pnpid_table[i].y_max;
++                      return 0;
++              }
++      }
++
+       if (SYN_EXT_CAP_REQUESTS(priv->capabilities) >= 5 &&
+           SYN_CAP_MAX_DIMENSIONS(priv->ext_cap_0c)) {
+               if (synaptics_send_cmd(psmouse, SYN_QUE_EXT_MAX_COORDS, resp)) {

diff --git a/queue-3.15/mips-msc-prevent-out-of-bounds-writes-to-mips-sc-ioremap-d-region.patch b/queue-3.15/mips-msc-prevent-out-of-bounds-writes-to-mips-sc-ioremap-d-region.patch
new file mode 100644 (file)
index 0000000..4312ce9
--- /dev/null
+++ b/queue-3.15/mips-msc-prevent-out-of-bounds-writes-to-mips-sc-ioremap-d-region.patch
@@ -0,0 +1,51 @@
+From ab6c15bc6620ebe220970cc040b29bcb2757f373 Mon Sep 17 00:00:00 2001
+From: Markos Chandras <markos.chandras@imgtec.com>
+Date: Mon, 23 Jun 2014 09:48:51 +0100
+Subject: MIPS: MSC: Prevent out-of-bounds writes to MIPS SC ioremap'd region
+
+From: Markos Chandras <markos.chandras@imgtec.com>
+
+commit ab6c15bc6620ebe220970cc040b29bcb2757f373 upstream.
+
+Previously, the lower limit for the MIPS SC initialization loop was
+set incorrectly allowing one extra loop leading to writes
+beyond the MSC ioremap'd space. More precisely, the value of the 'imp'
+in the last loop increased beyond the msc_irqmap_t boundaries and
+as a result of which, the 'n' variable was loaded with an incorrect
+value. This value was used later on to calculate the offset in the
+MSC01_IC_SUP which led to random crashes like the following one:
+
+CPU 0 Unable to handle kernel paging request at virtual address e75c0200,
+epc == 8058dba4, ra == 8058db90
+[...]
+Call Trace:
+[<8058dba4>] init_msc_irqs+0x104/0x154
+[<8058b5bc>] arch_init_irq+0xd8/0x154
+[<805897b0>] start_kernel+0x220/0x36c
+
+Kernel panic - not syncing: Attempted to kill the idle task!
+
+This patch fixes the problem
+
+Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
+Reviewed-by: James Hogan <james.hogan@imgtec.com>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/7118/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/mips/kernel/irq-msc01.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/kernel/irq-msc01.c
++++ b/arch/mips/kernel/irq-msc01.c
+@@ -131,7 +131,7 @@ void __init init_msc_irqs(unsigned long
+ 
+       board_bind_eic_interrupt = &msc_bind_eic_interrupt;
+ 
+-      for (; nirq >= 0; nirq--, imp++) {
++      for (; nirq > 0; nirq--, imp++) {
+               int n = imp->im_irq;
+ 
+               switch (imp->im_type) {

diff --git a/queue-3.15/mtip32xx-fix-ero-and-nosnoop-values-in-pcie-upstream-on-amd-systems.patch b/queue-3.15/mtip32xx-fix-ero-and-nosnoop-values-in-pcie-upstream-on-amd-systems.patch
new file mode 100644 (file)
index 0000000..7dc9feb
--- /dev/null
+++ b/queue-3.15/mtip32xx-fix-ero-and-nosnoop-values-in-pcie-upstream-on-amd-systems.patch
@@ -0,0 +1,95 @@
+From d1e714db8129a1d3670e449b87719c78e2c76f9f Mon Sep 17 00:00:00 2001
+From: Asai Thambi S P <asamymuthupa@micron.com>
+Date: Thu, 13 Mar 2014 18:45:15 -0700
+Subject: mtip32xx: Fix ERO and NoSnoop values in PCIe upstream on AMD systems
+
+From: Asai Thambi S P <asamymuthupa@micron.com>
+
+commit d1e714db8129a1d3670e449b87719c78e2c76f9f upstream.
+
+A hardware quirk in P320h/P420m interfere with PCIe transactions on some
+AMD chipsets, making P320h/P420m unusable. This workaround is to disable
+ERO and NoSnoop bits in the parent and root complex for normal
+functioning of these devices
+
+NOTE: This workaround is specific to AMD chipset with a PCIe upstream
+device with device id 0x5aXX
+
+Signed-off-by: Asai Thambi S P <asamymuthupa@micron.com>
+Signed-off-by: Sam Bradshaw <sbradshaw@micron.com>
+Signed-off-by: Jens Axboe <axboe@fb.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/block/mtip32xx/mtip32xx.c |   53 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 53 insertions(+)
+
+--- a/drivers/block/mtip32xx/mtip32xx.c
++++ b/drivers/block/mtip32xx/mtip32xx.c
+@@ -4479,6 +4479,57 @@ static DEFINE_HANDLER(5);
+ static DEFINE_HANDLER(6);
+ static DEFINE_HANDLER(7);
+ 
++static void mtip_disable_link_opts(struct driver_data *dd, struct pci_dev *pdev)
++{
++      int pos;
++      unsigned short pcie_dev_ctrl;
++
++      pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
++      if (pos) {
++              pci_read_config_word(pdev,
++                      pos + PCI_EXP_DEVCTL,
++                      &pcie_dev_ctrl);
++              if (pcie_dev_ctrl & (1 << 11) ||
++                  pcie_dev_ctrl & (1 << 4)) {
++                      dev_info(&dd->pdev->dev,
++                              "Disabling ERO/No-Snoop on bridge device %04x:%04x\n",
++                                      pdev->vendor, pdev->device);
++                      pcie_dev_ctrl &= ~(PCI_EXP_DEVCTL_NOSNOOP_EN |
++                                              PCI_EXP_DEVCTL_RELAX_EN);
++                      pci_write_config_word(pdev,
++                              pos + PCI_EXP_DEVCTL,
++                              pcie_dev_ctrl);
++              }
++      }
++}
++
++static void mtip_fix_ero_nosnoop(struct driver_data *dd, struct pci_dev *pdev)
++{
++      /*
++       * This workaround is specific to AMD/ATI chipset with a PCI upstream
++       * device with device id 0x5aXX
++       */
++      if (pdev->bus && pdev->bus->self) {
++              if (pdev->bus->self->vendor == PCI_VENDOR_ID_ATI &&
++                  ((pdev->bus->self->device & 0xff00) == 0x5a00)) {
++                      mtip_disable_link_opts(dd, pdev->bus->self);
++              } else {
++                      /* Check further up the topology */
++                      struct pci_dev *parent_dev = pdev->bus->self;
++                      if (parent_dev->bus &&
++                              parent_dev->bus->parent &&
++                              parent_dev->bus->parent->self &&
++                              parent_dev->bus->parent->self->vendor ==
++                                       PCI_VENDOR_ID_ATI &&
++                              (parent_dev->bus->parent->self->device &
++                                      0xff00) == 0x5a00) {
++                              mtip_disable_link_opts(dd,
++                                      parent_dev->bus->parent->self);
++                      }
++              }
++      }
++}
++
+ /*
+  * Called for each supported PCI device detected.
+  *
+@@ -4630,6 +4681,8 @@ static int mtip_pci_probe(struct pci_dev
+               goto msi_initialize_err;
+       }
+ 
++      mtip_fix_ero_nosnoop(dd, pdev);
++
+       /* Initialize the block layer. */
+       rv = mtip_block_initialize(dd);
+       if (rv < 0) {

diff --git a/queue-3.15/mtip32xx-increase-timeout-for-standby-immediate-command.patch b/queue-3.15/mtip32xx-increase-timeout-for-standby-immediate-command.patch
new file mode 100644 (file)
index 0000000..b900eb0
--- /dev/null
+++ b/queue-3.15/mtip32xx-increase-timeout-for-standby-immediate-command.patch
@@ -0,0 +1,123 @@
+From 670a641420a3d9586eebe7429dfeec4e7ed447aa Mon Sep 17 00:00:00 2001
+From: Asai Thambi S P <asamymuthupa@micron.com>
+Date: Wed, 16 Apr 2014 20:27:54 -0700
+Subject: mtip32xx: Increase timeout for STANDBY IMMEDIATE command
+
+From: Asai Thambi S P <asamymuthupa@micron.com>
+
+commit 670a641420a3d9586eebe7429dfeec4e7ed447aa upstream.
+
+Increased timeout for STANDBY IMMEDIATE command to 2 minutes.
+
+Signed-off-by: Selvan Mani <smani@micron.com>
+Signed-off-by: Asai Thambi S P <asamymuthupa@micron.com>
+Signed-off-by: Jens Axboe <axboe@fb.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/block/mtip32xx/mtip32xx.c |   66 ++++++++++++++++++++------------------
+ 1 file changed, 35 insertions(+), 31 deletions(-)
+
+--- a/drivers/block/mtip32xx/mtip32xx.c
++++ b/drivers/block/mtip32xx/mtip32xx.c
+@@ -1529,6 +1529,37 @@ static inline void ata_swap_string(u16 *
+               be16_to_cpus(&buf[i]);
+ }
+ 
++static void mtip_set_timeout(struct driver_data *dd,
++                                      struct host_to_dev_fis *fis,
++                                      unsigned int *timeout, u8 erasemode)
++{
++      switch (fis->command) {
++      case ATA_CMD_DOWNLOAD_MICRO:
++              *timeout = 120000; /* 2 minutes */
++              break;
++      case ATA_CMD_SEC_ERASE_UNIT:
++      case 0xFC:
++              if (erasemode)
++                      *timeout = ((*(dd->port->identify + 90) * 2) * 60000);
++              else
++                      *timeout = ((*(dd->port->identify + 89) * 2) * 60000);
++              break;
++      case ATA_CMD_STANDBYNOW1:
++              *timeout = 120000;  /* 2 minutes */
++              break;
++      case 0xF7:
++      case 0xFA:
++              *timeout = 60000;  /* 60 seconds */
++              break;
++      case ATA_CMD_SMART:
++              *timeout = 15000;  /* 15 seconds */
++              break;
++      default:
++              *timeout = MTIP_IOCTL_COMMAND_TIMEOUT_MS;
++              break;
++      }
++}
++
+ /*
+  * Request the device identity information.
+  *
+@@ -1644,6 +1675,7 @@ static int mtip_standby_immediate(struct
+       int rv;
+       struct host_to_dev_fis  fis;
+       unsigned long start;
++      unsigned int timeout;
+ 
+       /* Build the FIS. */
+       memset(&fis, 0, sizeof(struct host_to_dev_fis));
+@@ -1651,6 +1683,8 @@ static int mtip_standby_immediate(struct
+       fis.opts        = 1 << 7;
+       fis.command     = ATA_CMD_STANDBYNOW1;
+ 
++      mtip_set_timeout(port->dd, &fis, &timeout, 0);
++
+       start = jiffies;
+       rv = mtip_exec_internal_command(port,
+                                       &fis,
+@@ -1659,7 +1693,7 @@ static int mtip_standby_immediate(struct
+                                       0,
+                                       0,
+                                       GFP_ATOMIC,
+-                                      15000);
++                                      timeout);
+       dbg_printk(MTIP_DRV_NAME "Time taken to complete standby cmd: %d ms\n",
+                       jiffies_to_msecs(jiffies - start));
+       if (rv)
+@@ -2202,36 +2236,6 @@ static unsigned int implicit_sector(unsi
+       }
+       return rv;
+ }
+-static void mtip_set_timeout(struct driver_data *dd,
+-                                      struct host_to_dev_fis *fis,
+-                                      unsigned int *timeout, u8 erasemode)
+-{
+-      switch (fis->command) {
+-      case ATA_CMD_DOWNLOAD_MICRO:
+-              *timeout = 120000; /* 2 minutes */
+-              break;
+-      case ATA_CMD_SEC_ERASE_UNIT:
+-      case 0xFC:
+-              if (erasemode)
+-                      *timeout = ((*(dd->port->identify + 90) * 2) * 60000);
+-              else
+-                      *timeout = ((*(dd->port->identify + 89) * 2) * 60000);
+-              break;
+-      case ATA_CMD_STANDBYNOW1:
+-              *timeout = 120000;  /* 2 minutes */
+-              break;
+-      case 0xF7:
+-      case 0xFA:
+-              *timeout = 60000;  /* 60 seconds */
+-              break;
+-      case ATA_CMD_SMART:
+-              *timeout = 15000;  /* 15 seconds */
+-              break;
+-      default:
+-              *timeout = MTIP_IOCTL_COMMAND_TIMEOUT_MS;
+-              break;
+-      }
+-}
+ 
+ /*
+  * Executes a taskfile

diff --git a/queue-3.15/mtip32xx-remove-dfs_parent-after-pci-unregister.patch b/queue-3.15/mtip32xx-remove-dfs_parent-after-pci-unregister.patch
new file mode 100644 (file)
index 0000000..5e6787b
--- /dev/null
+++ b/queue-3.15/mtip32xx-remove-dfs_parent-after-pci-unregister.patch
@@ -0,0 +1,42 @@
+From af5ded8ccf21627f9614afc03b356712666ed225 Mon Sep 17 00:00:00 2001
+From: Asai Thambi S P <asamymuthupa@micron.com>
+Date: Wed, 16 Apr 2014 20:30:16 -0700
+Subject: mtip32xx: Remove dfs_parent after pci unregister
+
+From: Asai Thambi S P <asamymuthupa@micron.com>
+
+commit af5ded8ccf21627f9614afc03b356712666ed225 upstream.
+
+In module exit, dfs_parent and it's subtree were removed before
+unregistering with pci. When debugfs entry for each device is attempted
+to remove in pci_remove() context, they don't exist, as dfs_parent and
+its children were already ripped apart.
+
+Modified to first unregister with pci and then remove dfs_parent.
+
+Signed-off-by: Asai Thambi S P <asamymuthupa@micron.com>
+Signed-off-by: Jens Axboe <axboe@fb.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/block/mtip32xx/mtip32xx.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/block/mtip32xx/mtip32xx.c
++++ b/drivers/block/mtip32xx/mtip32xx.c
+@@ -4992,13 +4992,13 @@ static int __init mtip_init(void)
+  */
+ static void __exit mtip_exit(void)
+ {
+-      debugfs_remove_recursive(dfs_parent);
+-
+       /* Release the allocated major block device number. */
+       unregister_blkdev(mtip_major, MTIP_DRV_NAME);
+ 
+       /* Unregister the PCI driver. */
+       pci_unregister_driver(&mtip_pci_driver);
++
++      debugfs_remove_recursive(dfs_parent);
+ }
+ 
+ MODULE_AUTHOR("Micron Technology, Inc");

diff --git a/queue-3.15/pci-add-new-id-for-intel-gpu-spurious-interrupt-quirk.patch b/queue-3.15/pci-add-new-id-for-intel-gpu-spurious-interrupt-quirk.patch
new file mode 100644 (file)
index 0000000..9142170
--- /dev/null
+++ b/queue-3.15/pci-add-new-id-for-intel-gpu-spurious-interrupt-quirk.patch
@@ -0,0 +1,40 @@
+From 7c82126a94e69bbbac586f0249e7ef11e681246c Mon Sep 17 00:00:00 2001
+From: Thomas Jarosch <thomas.jarosch@intra2net.com>
+Date: Mon, 7 Apr 2014 15:10:32 +0200
+Subject: PCI: Add new ID for Intel GPU "spurious interrupt" quirk
+
+From: Thomas Jarosch <thomas.jarosch@intra2net.com>
+
+commit 7c82126a94e69bbbac586f0249e7ef11e681246c upstream.
+
+After a CPU upgrade while keeping the same mainboard, we faced "spurious
+interrupt" problems again.
+
+It turned out that the new CPU also featured a new GPU with a different PCI
+ID.
+
+Add this PCI ID to the quirk table.  Probably all other Intel GPU PCI IDs
+are affected, too, but I don't want to add them without a test system.
+
+See f67fd55fa96f ("PCI: Add quirk for still enabled interrupts on Intel
+Sandy Bridge GPUs") for some history.
+
+[bhelgaas: add f67fd55fa96f reference, stable tag]
+Signed-off-by: Thomas Jarosch <thomas.jarosch@intra2net.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/quirks.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -2954,6 +2954,7 @@ static void disable_igfx_irq(struct pci_
+ }
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
+ 
+ /*
+  * PCI devices which are on Intel chips can skip the 10ms delay

diff --git a/queue-3.15/pci-fix-incorrect-vgaarb-conditional-in-warn_on.patch b/queue-3.15/pci-fix-incorrect-vgaarb-conditional-in-warn_on.patch
new file mode 100644 (file)
index 0000000..2c79bfd
--- /dev/null
+++ b/queue-3.15/pci-fix-incorrect-vgaarb-conditional-in-warn_on.patch
@@ -0,0 +1,37 @@
+From 67ebd8140dc8923c65451fa0f6a8eee003c4dcd3 Mon Sep 17 00:00:00 2001
+From: Bjorn Helgaas <bhelgaas@google.com>
+Date: Sat, 5 Apr 2014 15:14:22 -0600
+Subject: PCI: Fix incorrect vgaarb conditional in WARN_ON()
+
+From: Bjorn Helgaas <bhelgaas@google.com>
+
+commit 67ebd8140dc8923c65451fa0f6a8eee003c4dcd3 upstream.
+
+3448a19da479 "vgaarb: use bridges to control VGA routing where possible"
+added the "flags & PCI_VGA_STATE_CHANGE_DECODES" condition to an existing
+WARN_ON(), but used bitwise AND (&) instead of logical AND (&&), so the
+condition is never true.  Replace with logical AND.
+
+Found by Coverity (CID 142811).
+
+Fixes: 3448a19da479 "vgaarb: use bridges to control VGA routing where possible"
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Yinghai Lu <yinghai@kernel.org>
+Acked-by: David Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/pci.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pci/pci.c
++++ b/drivers/pci/pci.c
+@@ -4126,7 +4126,7 @@ int pci_set_vga_state(struct pci_dev *de
+       u16 cmd;
+       int rc;
+ 
+-      WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
++      WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
+ 
+       /* ARCH specific VGA enables */
+       rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);

diff --git a/queue-3.15/recordmcount-mips-fix-possible-incorrect-mcount_loc-table-entries-in-modules.patch b/queue-3.15/recordmcount-mips-fix-possible-incorrect-mcount_loc-table-entries-in-modules.patch
new file mode 100644 (file)
index 0000000..44cea6d
--- /dev/null
+++ b/queue-3.15/recordmcount-mips-fix-possible-incorrect-mcount_loc-table-entries-in-modules.patch
@@ -0,0 +1,62 @@
+From 91ad11d7cc6f4472ebf177a6252fbf0fd100d798 Mon Sep 17 00:00:00 2001
+From: Alex Smith <alex.smith@imgtec.com>
+Date: Tue, 17 Jun 2014 10:39:53 +0100
+Subject: recordmcount/MIPS: Fix possible incorrect mcount_loc table entries in modules
+
+From: Alex Smith <alex.smith@imgtec.com>
+
+commit 91ad11d7cc6f4472ebf177a6252fbf0fd100d798 upstream.
+
+On MIPS calls to _mcount in modules generate 2 instructions to load
+the _mcount address (and therefore 2 relocations). The mcount_loc
+table should only reference the first of these, so the second is
+filtered out by checking the relocation offset and ignoring ones that
+immediately follow the previous one seen.
+
+However if a module has an _mcount call at offset 0, the second
+relocation would not be filtered out due to old_r_offset == 0
+being taken to mean that the current relocation is the first one
+seen, and both would end up in the mcount_loc table.
+
+This results in ftrace_make_nop() patching both (adjacent)
+instructions to branches over the _mcount call sequence like so:
+
+  0xffffffffc08a8000:  04 00 00 10     b       0xffffffffc08a8014
+  0xffffffffc08a8004:  04 00 00 10     b       0xffffffffc08a8018
+  0xffffffffc08a8008:  2d 08 e0 03     move    at,ra
+  ...
+
+The second branch is in the delay slot of the first, which is
+defined to be unpredictable - on the platform on which this bug was
+encountered, it triggers a reserved instruction exception.
+
+Fix by initializing old_r_offset to ~0 and using that instead of 0
+to determine whether the current relocation is the first seen.
+
+Signed-off-by: Alex Smith <alex.smith@imgtec.com>
+Cc: linux-kernel@vger.kernel.org
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/7098/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ scripts/recordmcount.h |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/scripts/recordmcount.h
++++ b/scripts/recordmcount.h
+@@ -163,11 +163,11 @@ static int mcount_adjust = 0;
+ 
+ static int MIPS_is_fake_mcount(Elf_Rel const *rp)
+ {
+-      static Elf_Addr old_r_offset;
++      static Elf_Addr old_r_offset = ~(Elf_Addr)0;
+       Elf_Addr current_r_offset = _w(rp->r_offset);
+       int is_fake;
+ 
+-      is_fake = old_r_offset &&
++      is_fake = (old_r_offset != ~(Elf_Addr)0) &&
+               (current_r_offset - old_r_offset == MIPS_FAKEMCOUNT_OFFSET);
+       old_r_offset = current_r_offset;
+ 

diff --git a/queue-3.15/revert-mips-save-restore-msa-context-around-signals.patch b/queue-3.15/revert-mips-save-restore-msa-context-around-signals.patch
new file mode 100644 (file)
index 0000000..867d3ae
--- /dev/null
+++ b/queue-3.15/revert-mips-save-restore-msa-context-around-signals.patch
@@ -0,0 +1,685 @@
+From 16f77de82f2d2f628306dab9bc4799df0d28a199 Mon Sep 17 00:00:00 2001
+From: Paul Burton <paul.burton@imgtec.com>
+Date: Wed, 18 Jun 2014 15:00:46 +0100
+Subject: Revert "MIPS: Save/restore MSA context around signals"
+
+From: Paul Burton <paul.burton@imgtec.com>
+
+commit 16f77de82f2d2f628306dab9bc4799df0d28a199 upstream.
+
+This reverts commit eec43a224cf1 "MIPS: Save/restore MSA context around
+signals" and the MSA parts of ca750649e08c "MIPS: kernel: signal:
+Prevent save/restore FPU context in user memory" (the restore path of
+which appears incorrect anyway...).
+
+The reverted patch took care not to break compatibility with userland
+users of struct sigcontext, but inadvertantly changed the offset of the
+uc_sigmask field of struct ucontext. Thus Linux v3.15 breaks the
+userland ABI. The MSA context will need to be saved via some other
+opt-in mechanism, but for now revert the change to reduce the fallout.
+
+This will have minimal impact upon use of MSA since the only supported
+CPU which includes it (the P5600) is 32-bit and therefore requires that
+the experimental CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option be selected
+before the kernel will set FR=1 for a task, a requirement for MSA use.
+Thus the users of MSA are limited to known small groups of people & this
+patch won't be breaking any previously working MSA-using userland
+outside of experimental settings.
+
+[ralf@linux-mips.org: Fixed rejects.]
+
+Reported-by: Joseph S. Myers <joseph@codesourcery.com>
+Signed-off-by: Paul Burton <paul.burton@imgtec.com>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/7107/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/mips/include/asm/sigcontext.h      |    2 
+ arch/mips/include/uapi/asm/sigcontext.h |    8 -
+ arch/mips/kernel/asm-offsets.c          |    3 
+ arch/mips/kernel/r4k_fpu.S              |  213 --------------------------------
+ arch/mips/kernel/signal.c               |   79 +----------
+ arch/mips/kernel/signal32.c             |   74 +----------
+ 6 files changed, 16 insertions(+), 363 deletions(-)
+
+--- a/arch/mips/include/asm/sigcontext.h
++++ b/arch/mips/include/asm/sigcontext.h
+@@ -32,8 +32,6 @@ struct sigcontext32 {
+       __u32           sc_lo2;
+       __u32           sc_hi3;
+       __u32           sc_lo3;
+-      __u64           sc_msaregs[32]; /* Most significant 64 bits */
+-      __u32           sc_msa_csr;
+ };
+ #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+ #endif /* _ASM_SIGCONTEXT_H */
+--- a/arch/mips/include/uapi/asm/sigcontext.h
++++ b/arch/mips/include/uapi/asm/sigcontext.h
+@@ -12,10 +12,6 @@
+ #include <linux/types.h>
+ #include <asm/sgidefs.h>
+ 
+-/* Bits which may be set in sc_used_math */
+-#define USEDMATH_FP   (1 << 0)
+-#define USEDMATH_MSA  (1 << 1)
+-
+ #if _MIPS_SIM == _MIPS_SIM_ABI32
+ 
+ /*
+@@ -41,8 +37,6 @@ struct sigcontext {
+       unsigned long           sc_lo2;
+       unsigned long           sc_hi3;
+       unsigned long           sc_lo3;
+-      unsigned long long      sc_msaregs[32]; /* Most significant 64 bits */
+-      unsigned long           sc_msa_csr;
+ };
+ 
+ #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+@@ -76,8 +70,6 @@ struct sigcontext {
+       __u32   sc_used_math;
+       __u32   sc_dsp;
+       __u32   sc_reserved;
+-      __u64   sc_msaregs[32];
+-      __u32   sc_msa_csr;
+ };
+ 
+ 
+--- a/arch/mips/kernel/asm-offsets.c
++++ b/arch/mips/kernel/asm-offsets.c
+@@ -295,7 +295,6 @@ void output_sc_defines(void)
+       OFFSET(SC_LO2, sigcontext, sc_lo2);
+       OFFSET(SC_HI3, sigcontext, sc_hi3);
+       OFFSET(SC_LO3, sigcontext, sc_lo3);
+-      OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
+       BLANK();
+ }
+ #endif
+@@ -310,7 +309,6 @@ void output_sc_defines(void)
+       OFFSET(SC_MDLO, sigcontext, sc_mdlo);
+       OFFSET(SC_PC, sigcontext, sc_pc);
+       OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
+-      OFFSET(SC_MSAREGS, sigcontext, sc_msaregs);
+       BLANK();
+ }
+ #endif
+@@ -322,7 +320,6 @@ void output_sc32_defines(void)
+       OFFSET(SC32_FPREGS, sigcontext32, sc_fpregs);
+       OFFSET(SC32_FPC_CSR, sigcontext32, sc_fpc_csr);
+       OFFSET(SC32_FPC_EIR, sigcontext32, sc_fpc_eir);
+-      OFFSET(SC32_MSAREGS, sigcontext32, sc_msaregs);
+       BLANK();
+ }
+ #endif
+--- a/arch/mips/kernel/r4k_fpu.S
++++ b/arch/mips/kernel/r4k_fpu.S
+@@ -13,7 +13,6 @@
+  * Copyright (C) 1999, 2001 Silicon Graphics, Inc.
+  */
+ #include <asm/asm.h>
+-#include <asm/asmmacro.h>
+ #include <asm/errno.h>
+ #include <asm/fpregdef.h>
+ #include <asm/mipsregs.h>
+@@ -246,218 +245,6 @@ LEAF(_restore_fp_context32)
+       END(_restore_fp_context32)
+ #endif
+ 
+-#ifdef CONFIG_CPU_HAS_MSA
+-
+-      .macro  save_sc_msareg  wr, off, sc, tmp
+-#ifdef CONFIG_64BIT
+-      copy_u_d \tmp, \wr, 1
+-      EX sd   \tmp, (\off+(\wr*8))(\sc)
+-#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
+-      copy_u_w \tmp, \wr, 2
+-      EX sw   \tmp, (\off+(\wr*8)+0)(\sc)
+-      copy_u_w \tmp, \wr, 3
+-      EX sw   \tmp, (\off+(\wr*8)+4)(\sc)
+-#else /* CONFIG_CPU_BIG_ENDIAN */
+-      copy_u_w \tmp, \wr, 2
+-      EX sw   \tmp, (\off+(\wr*8)+4)(\sc)
+-      copy_u_w \tmp, \wr, 3
+-      EX sw   \tmp, (\off+(\wr*8)+0)(\sc)
+-#endif
+-      .endm
+-
+-/*
+- * int _save_msa_context(struct sigcontext *sc)
+- *
+- * Save the upper 64 bits of each vector register along with the MSA_CSR
+- * register into sc. Returns zero on success, else non-zero.
+- */
+-LEAF(_save_msa_context)
+-      save_sc_msareg  0, SC_MSAREGS, a0, t0
+-      save_sc_msareg  1, SC_MSAREGS, a0, t0
+-      save_sc_msareg  2, SC_MSAREGS, a0, t0
+-      save_sc_msareg  3, SC_MSAREGS, a0, t0
+-      save_sc_msareg  4, SC_MSAREGS, a0, t0
+-      save_sc_msareg  5, SC_MSAREGS, a0, t0
+-      save_sc_msareg  6, SC_MSAREGS, a0, t0
+-      save_sc_msareg  7, SC_MSAREGS, a0, t0
+-      save_sc_msareg  8, SC_MSAREGS, a0, t0
+-      save_sc_msareg  9, SC_MSAREGS, a0, t0
+-      save_sc_msareg  10, SC_MSAREGS, a0, t0
+-      save_sc_msareg  11, SC_MSAREGS, a0, t0
+-      save_sc_msareg  12, SC_MSAREGS, a0, t0
+-      save_sc_msareg  13, SC_MSAREGS, a0, t0
+-      save_sc_msareg  14, SC_MSAREGS, a0, t0
+-      save_sc_msareg  15, SC_MSAREGS, a0, t0
+-      save_sc_msareg  16, SC_MSAREGS, a0, t0
+-      save_sc_msareg  17, SC_MSAREGS, a0, t0
+-      save_sc_msareg  18, SC_MSAREGS, a0, t0
+-      save_sc_msareg  19, SC_MSAREGS, a0, t0
+-      save_sc_msareg  20, SC_MSAREGS, a0, t0
+-      save_sc_msareg  21, SC_MSAREGS, a0, t0
+-      save_sc_msareg  22, SC_MSAREGS, a0, t0
+-      save_sc_msareg  23, SC_MSAREGS, a0, t0
+-      save_sc_msareg  24, SC_MSAREGS, a0, t0
+-      save_sc_msareg  25, SC_MSAREGS, a0, t0
+-      save_sc_msareg  26, SC_MSAREGS, a0, t0
+-      save_sc_msareg  27, SC_MSAREGS, a0, t0
+-      save_sc_msareg  28, SC_MSAREGS, a0, t0
+-      save_sc_msareg  29, SC_MSAREGS, a0, t0
+-      save_sc_msareg  30, SC_MSAREGS, a0, t0
+-      save_sc_msareg  31, SC_MSAREGS, a0, t0
+-      jr      ra
+-       li     v0, 0
+-      END(_save_msa_context)
+-
+-#ifdef CONFIG_MIPS32_COMPAT
+-
+-/*
+- * int _save_msa_context32(struct sigcontext32 *sc)
+- *
+- * Save the upper 64 bits of each vector register along with the MSA_CSR
+- * register into sc. Returns zero on success, else non-zero.
+- */
+-LEAF(_save_msa_context32)
+-      save_sc_msareg  0, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  1, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  2, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  3, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  4, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  5, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  6, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  7, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  8, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  9, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  10, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  11, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  12, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  13, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  14, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  15, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  16, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  17, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  18, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  19, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  20, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  21, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  22, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  23, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  24, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  25, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  26, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  27, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  28, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  29, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  30, SC32_MSAREGS, a0, t0
+-      save_sc_msareg  31, SC32_MSAREGS, a0, t0
+-      jr      ra
+-       li     v0, 0
+-      END(_save_msa_context32)
+-
+-#endif /* CONFIG_MIPS32_COMPAT */
+-
+-      .macro restore_sc_msareg        wr, off, sc, tmp
+-#ifdef CONFIG_64BIT
+-      EX ld   \tmp, (\off+(\wr*8))(\sc)
+-      insert_d \wr, 1, \tmp
+-#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
+-      EX lw   \tmp, (\off+(\wr*8)+0)(\sc)
+-      insert_w \wr, 2, \tmp
+-      EX lw   \tmp, (\off+(\wr*8)+4)(\sc)
+-      insert_w \wr, 3, \tmp
+-#else /* CONFIG_CPU_BIG_ENDIAN */
+-      EX lw   \tmp, (\off+(\wr*8)+4)(\sc)
+-      insert_w \wr, 2, \tmp
+-      EX lw   \tmp, (\off+(\wr*8)+0)(\sc)
+-      insert_w \wr, 3, \tmp
+-#endif
+-      .endm
+-
+-/*
+- * int _restore_msa_context(struct sigcontext *sc)
+- */
+-LEAF(_restore_msa_context)
+-      restore_sc_msareg       0, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       1, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       2, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       3, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       4, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       5, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       6, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       7, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       8, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       9, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       10, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       11, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       12, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       13, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       14, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       15, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       16, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       17, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       18, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       19, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       20, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       21, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       22, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       23, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       24, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       25, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       26, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       27, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       28, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       29, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       30, SC_MSAREGS, a0, t0
+-      restore_sc_msareg       31, SC_MSAREGS, a0, t0
+-      jr      ra
+-       li     v0, 0
+-      END(_restore_msa_context)
+-
+-#ifdef CONFIG_MIPS32_COMPAT
+-
+-/*
+- * int _restore_msa_context32(struct sigcontext32 *sc)
+- */
+-LEAF(_restore_msa_context32)
+-      restore_sc_msareg       0, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       1, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       2, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       3, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       4, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       5, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       6, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       7, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       8, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       9, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       10, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       11, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       12, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       13, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       14, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       15, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       16, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       17, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       18, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       19, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       20, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       21, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       22, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       23, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       24, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       25, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       26, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       27, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       28, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       29, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       30, SC32_MSAREGS, a0, t0
+-      restore_sc_msareg       31, SC32_MSAREGS, a0, t0
+-      jr      ra
+-       li     v0, 0
+-      END(_restore_msa_context32)
+-
+-#endif /* CONFIG_MIPS32_COMPAT */
+-
+-#endif /* CONFIG_CPU_HAS_MSA */
+-
+       .set    reorder
+ 
+       .type   fault@function
+--- a/arch/mips/kernel/signal.c
++++ b/arch/mips/kernel/signal.c
+@@ -31,7 +31,6 @@
+ #include <linux/bitops.h>
+ #include <asm/cacheflush.h>
+ #include <asm/fpu.h>
+-#include <asm/msa.h>
+ #include <asm/sim.h>
+ #include <asm/ucontext.h>
+ #include <asm/cpu-features.h>
+@@ -48,9 +47,6 @@ static int (*restore_fp_context)(struct
+ extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
+ extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
+ 
+-extern asmlinkage int _save_msa_context(struct sigcontext __user *sc);
+-extern asmlinkage int _restore_msa_context(struct sigcontext __user *sc);
+-
+ struct sigframe {
+       u32 sf_ass[4];          /* argument save space for o32 */
+       u32 sf_pad[2];          /* Was: signal trampoline */
+@@ -100,60 +96,20 @@ static int copy_fp_from_sigcontext(struc
+ }
+ 
+ /*
+- * These functions will save only the upper 64 bits of the vector registers,
+- * since the lower 64 bits have already been saved as the scalar FP context.
+- */
+-static int copy_msa_to_sigcontext(struct sigcontext __user *sc)
+-{
+-      int i;
+-      int err = 0;
+-
+-      for (i = 0; i < NUM_FPU_REGS; i++) {
+-              err |=
+-                  __put_user(get_fpr64(&current->thread.fpu.fpr[i], 1),
+-                             &sc->sc_msaregs[i]);
+-      }
+-      err |= __put_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
+-
+-      return err;
+-}
+-
+-static int copy_msa_from_sigcontext(struct sigcontext __user *sc)
+-{
+-      int i;
+-      int err = 0;
+-      u64 val;
+-
+-      for (i = 0; i < NUM_FPU_REGS; i++) {
+-              err |= __get_user(val, &sc->sc_msaregs[i]);
+-              set_fpr64(&current->thread.fpu.fpr[i], 1, val);
+-      }
+-      err |= __get_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
+-
+-      return err;
+-}
+-
+-/*
+  * Helper routines
+  */
+-static int protected_save_fp_context(struct sigcontext __user *sc,
+-                                   unsigned used_math)
++static int protected_save_fp_context(struct sigcontext __user *sc)
+ {
+       int err;
+-      bool save_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
+ #ifndef CONFIG_EVA
+       while (1) {
+               lock_fpu_owner();
+               if (is_fpu_owner()) {
+                       err = save_fp_context(sc);
+-                      if (save_msa && !err)
+-                              err = _save_msa_context(sc);
+                       unlock_fpu_owner();
+               } else {
+                       unlock_fpu_owner();
+                       err = copy_fp_to_sigcontext(sc);
+-                      if (save_msa && !err)
+-                              err = copy_msa_to_sigcontext(sc);
+               }
+               if (likely(!err))
+                       break;
+@@ -169,38 +125,24 @@ static int protected_save_fp_context(str
+        * EVA does not have FPU EVA instructions so saving fpu context directly
+        * does not work.
+        */
+-      disable_msa();
+       lose_fpu(1);
+       err = save_fp_context(sc); /* this might fail */
+-      if (save_msa && !err)
+-              err = copy_msa_to_sigcontext(sc);
+ #endif
+       return err;
+ }
+ 
+-static int protected_restore_fp_context(struct sigcontext __user *sc,
+-                                      unsigned used_math)
++static int protected_restore_fp_context(struct sigcontext __user *sc)
+ {
+       int err, tmp __maybe_unused;
+-      bool restore_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
+ #ifndef CONFIG_EVA
+       while (1) {
+               lock_fpu_owner();
+               if (is_fpu_owner()) {
+                       err = restore_fp_context(sc);
+-                      if (restore_msa && !err) {
+-                              enable_msa();
+-                              err = _restore_msa_context(sc);
+-                      } else {
+-                              /* signal handler may have used MSA */
+-                              disable_msa();
+-                      }
+                       unlock_fpu_owner();
+               } else {
+                       unlock_fpu_owner();
+                       err = copy_fp_from_sigcontext(sc);
+-                      if (!err && (used_math & USEDMATH_MSA))
+-                              err = copy_msa_from_sigcontext(sc);
+               }
+               if (likely(!err))
+                       break;
+@@ -216,11 +158,8 @@ static int protected_restore_fp_context(
+        * EVA does not have FPU EVA instructions so restoring fpu context
+        * directly does not work.
+        */
+-      enable_msa();
+       lose_fpu(0);
+       err = restore_fp_context(sc); /* this might fail */
+-      if (restore_msa && !err)
+-              err = copy_msa_from_sigcontext(sc);
+ #endif
+       return err;
+ }
+@@ -252,8 +191,7 @@ int setup_sigcontext(struct pt_regs *reg
+               err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
+       }
+ 
+-      used_math = used_math() ? USEDMATH_FP : 0;
+-      used_math |= thread_msa_context_live() ? USEDMATH_MSA : 0;
++      used_math = !!used_math();
+       err |= __put_user(used_math, &sc->sc_used_math);
+ 
+       if (used_math) {
+@@ -261,7 +199,7 @@ int setup_sigcontext(struct pt_regs *reg
+                * Save FPU state to signal context. Signal handler
+                * will "inherit" current FPU state.
+                */
+-              err |= protected_save_fp_context(sc, used_math);
++              err |= protected_save_fp_context(sc);
+       }
+       return err;
+ }
+@@ -286,14 +224,14 @@ int fpcsr_pending(unsigned int __user *f
+ }
+ 
+ static int
+-check_and_restore_fp_context(struct sigcontext __user *sc, unsigned used_math)
++check_and_restore_fp_context(struct sigcontext __user *sc)
+ {
+       int err, sig;
+ 
+       err = sig = fpcsr_pending(&sc->sc_fpc_csr);
+       if (err > 0)
+               err = 0;
+-      err |= protected_restore_fp_context(sc, used_math);
++      err |= protected_restore_fp_context(sc);
+       return err ?: sig;
+ }
+ 
+@@ -333,10 +271,9 @@ int restore_sigcontext(struct pt_regs *r
+       if (used_math) {
+               /* restore fpu context if we have used it before */
+               if (!err)
+-                      err = check_and_restore_fp_context(sc, used_math);
++                      err = check_and_restore_fp_context(sc);
+       } else {
+-              /* signal handler may have used FPU or MSA. Disable them. */
+-              disable_msa();
++              /* signal handler may have used FPU.  Give it up. */
+               lose_fpu(0);
+       }
+ 
+--- a/arch/mips/kernel/signal32.c
++++ b/arch/mips/kernel/signal32.c
+@@ -30,7 +30,6 @@
+ #include <asm/sim.h>
+ #include <asm/ucontext.h>
+ #include <asm/fpu.h>
+-#include <asm/msa.h>
+ #include <asm/war.h>
+ #include <asm/vdso.h>
+ #include <asm/dsp.h>
+@@ -43,9 +42,6 @@ static int (*restore_fp_context32)(struc
+ extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
+ extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
+ 
+-extern asmlinkage int _save_msa_context32(struct sigcontext32 __user *sc);
+-extern asmlinkage int _restore_msa_context32(struct sigcontext32 __user *sc);
+-
+ /*
+  * Including <asm/unistd.h> would give use the 64-bit syscall numbers ...
+  */
+@@ -115,59 +111,19 @@ static int copy_fp_from_sigcontext32(str
+ }
+ 
+ /*
+- * These functions will save only the upper 64 bits of the vector registers,
+- * since the lower 64 bits have already been saved as the scalar FP context.
+- */
+-static int copy_msa_to_sigcontext32(struct sigcontext32 __user *sc)
+-{
+-      int i;
+-      int err = 0;
+-
+-      for (i = 0; i < NUM_FPU_REGS; i++) {
+-              err |=
+-                  __put_user(get_fpr64(&current->thread.fpu.fpr[i], 1),
+-                             &sc->sc_msaregs[i]);
+-      }
+-      err |= __put_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
+-
+-      return err;
+-}
+-
+-static int copy_msa_from_sigcontext32(struct sigcontext32 __user *sc)
+-{
+-      int i;
+-      int err = 0;
+-      u64 val;
+-
+-      for (i = 0; i < NUM_FPU_REGS; i++) {
+-              err |= __get_user(val, &sc->sc_msaregs[i]);
+-              set_fpr64(&current->thread.fpu.fpr[i], 1, val);
+-      }
+-      err |= __get_user(current->thread.fpu.msacsr, &sc->sc_msa_csr);
+-
+-      return err;
+-}
+-
+-/*
+  * sigcontext handlers
+  */
+-static int protected_save_fp_context32(struct sigcontext32 __user *sc,
+-                                     unsigned used_math)
++static int protected_save_fp_context32(struct sigcontext32 __user *sc)
+ {
+       int err;
+-      bool save_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
+       while (1) {
+               lock_fpu_owner();
+               if (is_fpu_owner()) {
+                       err = save_fp_context32(sc);
+-                      if (save_msa && !err)
+-                              err = _save_msa_context32(sc);
+                       unlock_fpu_owner();
+               } else {
+                       unlock_fpu_owner();
+                       err = copy_fp_to_sigcontext32(sc);
+-                      if (save_msa && !err)
+-                              err = copy_msa_to_sigcontext32(sc);
+               }
+               if (likely(!err))
+                       break;
+@@ -181,28 +137,17 @@ static int protected_save_fp_context32(s
+       return err;
+ }
+ 
+-static int protected_restore_fp_context32(struct sigcontext32 __user *sc,
+-                                        unsigned used_math)
++static int protected_restore_fp_context32(struct sigcontext32 __user *sc)
+ {
+       int err, tmp __maybe_unused;
+-      bool restore_msa = cpu_has_msa && (used_math & USEDMATH_MSA);
+       while (1) {
+               lock_fpu_owner();
+               if (is_fpu_owner()) {
+                       err = restore_fp_context32(sc);
+-                      if (restore_msa && !err) {
+-                              enable_msa();
+-                              err = _restore_msa_context32(sc);
+-                      } else {
+-                              /* signal handler may have used MSA */
+-                              disable_msa();
+-                      }
+                       unlock_fpu_owner();
+               } else {
+                       unlock_fpu_owner();
+                       err = copy_fp_from_sigcontext32(sc);
+-                      if (restore_msa && !err)
+-                              err = copy_msa_from_sigcontext32(sc);
+               }
+               if (likely(!err))
+                       break;
+@@ -241,8 +186,7 @@ static int setup_sigcontext32(struct pt_
+               err |= __put_user(mflo3(), &sc->sc_lo3);
+       }
+ 
+-      used_math = used_math() ? USEDMATH_FP : 0;
+-      used_math |= thread_msa_context_live() ? USEDMATH_MSA : 0;
++      used_math = !!used_math();
+       err |= __put_user(used_math, &sc->sc_used_math);
+ 
+       if (used_math) {
+@@ -250,21 +194,20 @@ static int setup_sigcontext32(struct pt_
+                * Save FPU state to signal context.  Signal handler
+                * will "inherit" current FPU state.
+                */
+-              err |= protected_save_fp_context32(sc, used_math);
++              err |= protected_save_fp_context32(sc);
+       }
+       return err;
+ }
+ 
+ static int
+-check_and_restore_fp_context32(struct sigcontext32 __user *sc,
+-                             unsigned used_math)
++check_and_restore_fp_context32(struct sigcontext32 __user *sc)
+ {
+       int err, sig;
+ 
+       err = sig = fpcsr_pending(&sc->sc_fpc_csr);
+       if (err > 0)
+               err = 0;
+-      err |= protected_restore_fp_context32(sc, used_math);
++      err |= protected_restore_fp_context32(sc);
+       return err ?: sig;
+ }
+ 
+@@ -301,10 +244,9 @@ static int restore_sigcontext32(struct p
+       if (used_math) {
+               /* restore fpu context if we have used it before */
+               if (!err)
+-                      err = check_and_restore_fp_context32(sc, used_math);
++                      err = check_and_restore_fp_context32(sc);
+       } else {
+-              /* signal handler may have used FPU or MSA. Disable them. */
+-              disable_msa();
++              /* signal handler may have used FPU.  Give it up. */
+               lose_fpu(0);
+       }
+ 

diff --git a/queue-3.15/series b/queue-3.15/series
index 662c79dc2aab1652d2e3352c00b6a2bd8eb67cbd..33a1d867298b4e15b9c4bba567f3706d929b6036 100644 (file)
--- a/queue-3.15/series
+++ b/queue-3.15/series
@@ -2,3 +2,14 @@ target-fix-left-over-se_lun-lun_sep-pointer-oops.patch
 iscsi-target-avoid-rejecting-incorrect-itt-for-data-out.patch
 iscsi-target-explicily-clear-login-response-pdu-in-exception-path.patch
 iscsi-target-fix-iscsit_del_np-deadlock-on-unload.patch
+input-synaptics-fix-resolution-for-manually-provided-min-max.patch
+input-elantech-deal-with-clickpads-reporting-right-button-events.patch
+input-elantech-don-t-set-bit-1-of-reg_10-when-the-no_hw_res-quirk-is-set.patch
+pci-add-new-id-for-intel-gpu-spurious-interrupt-quirk.patch
+pci-fix-incorrect-vgaarb-conditional-in-warn_on.patch
+mtip32xx-fix-ero-and-nosnoop-values-in-pcie-upstream-on-amd-systems.patch
+mtip32xx-increase-timeout-for-standby-immediate-command.patch
+mtip32xx-remove-dfs_parent-after-pci-unregister.patch
+recordmcount-mips-fix-possible-incorrect-mcount_loc-table-entries-in-modules.patch
+revert-mips-save-restore-msa-context-around-signals.patch
+mips-msc-prevent-out-of-bounds-writes-to-mips-sc-ioremap-d-region.patch