clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider

There are wrongly set parenthesis in the code that are resulting in a
wrong configuration being programmed for PLLM. The original fix was made
by Danny Huang in the downstream kernel. The patch was tested on Nyan Big
Tegra124 chromebook, PLLM rate changing works correctly now and system
doesn't lock up after changing the PLLM rate due to EMC scaling.

Cc: <stable@vger.kernel.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index ebc8481a212288e45742bfdef4357c780c22ae30..6b976b2514f77bdb422ccd96f2517086f6d25977 100644 (file)
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -666,8 +666,8 @@ static void _update_pll_mnp(struct tegra_clk_pll *pll,
                pll_override_writel(val, params->pmc_divp_reg, pll);
 
                val = pll_override_readl(params->pmc_divnm_reg, pll);
-               val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
-                       ~(divn_mask(pll) << div_nmp->override_divn_shift);
+               val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
+                       (divn_mask(pll) << div_nmp->override_divn_shift));
                val |= (cfg->m << div_nmp->override_divm_shift) |
                        (cfg->n << div_nmp->override_divn_shift);
                pll_override_writel(val, params->pmc_divnm_reg, pll);