6.1-stable patches

added patches:
	spi-atmel-quadspi-avoid-overwriting-delay-register-settings.patch

diff --git a/queue-6.1/series b/queue-6.1/series
index a588a8e5d22e1a57a2788e20278b623f5203d749..51117843b4434dbdf5c288c65b0db0404735839c 100644 (file)
--- a/queue-6.1/series
+++ b/queue-6.1/series
@@ -91,3 +91,4 @@ x86-cpu-kvm-srso-fix-possible-missing-ibpb-on-vm-exit.patch
 block-bfq-split-sync-bfq_queues-on-a-per-actuator-basis.patch
 block-bfq-fix-bfqq-uaf-in-bfq_limit_depth.patch
 media-mediatek-vcodec-fix-h264-multi-stateless-decoder-smatch-warning.patch
+spi-atmel-quadspi-avoid-overwriting-delay-register-settings.patch

diff --git a/queue-6.1/spi-atmel-quadspi-avoid-overwriting-delay-register-settings.patch b/queue-6.1/spi-atmel-quadspi-avoid-overwriting-delay-register-settings.patch
new file mode 100644 (file)
index 0000000..2cf4b60
--- /dev/null
+++ b/queue-6.1/spi-atmel-quadspi-avoid-overwriting-delay-register-settings.patch
@@ -0,0 +1,75 @@
+From 329ca3eed4a9a161515a8714be6ba182321385c7 Mon Sep 17 00:00:00 2001
+From: Alexander Dahl <ada@thorsis.com>
+Date: Wed, 18 Sep 2024 10:27:43 +0200
+Subject: spi: atmel-quadspi: Avoid overwriting delay register settings
+
+From: Alexander Dahl <ada@thorsis.com>
+
+commit 329ca3eed4a9a161515a8714be6ba182321385c7 upstream.
+
+Previously the MR and SCR registers were just set with the supposedly
+required values, from cached register values (cached reg content
+initialized to zero).
+
+All parts fixed here did not consider the current register (cache)
+content, which would make future support of cs_setup, cs_hold, and
+cs_inactive impossible.
+
+Setting SCBR in atmel_qspi_setup() erases a possible DLYBS setting from
+atmel_qspi_set_cs_timing().  The DLYBS setting is applied by ORing over
+the current setting, without resetting the bits first.  All writes to MR
+did not consider possible settings of DLYCS and DLYBCT.
+
+Signed-off-by: Alexander Dahl <ada@thorsis.com>
+Fixes: f732646d0ccd ("spi: atmel-quadspi: Add support for configuring CS timing")
+Link: https://patch.msgid.link/20240918082744.379610-2-ada@thorsis.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/spi/atmel-quadspi.c |   14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+--- a/drivers/spi/atmel-quadspi.c
++++ b/drivers/spi/atmel-quadspi.c
+@@ -388,9 +388,9 @@ static int atmel_qspi_set_cfg(struct atm
+        * If the QSPI controller is set in regular SPI mode, set it in
+        * Serial Memory Mode (SMM).
+        */
+-      if (aq->mr != QSPI_MR_SMM) {
+-              atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
+-              aq->mr = QSPI_MR_SMM;
++      if (!(aq->mr & QSPI_MR_SMM)) {
++              aq->mr |= QSPI_MR_SMM;
++              atmel_qspi_write(aq->scr, aq, QSPI_MR);
+       }
+ 
+       /* Clear pending interrupts */
+@@ -545,7 +545,8 @@ static int atmel_qspi_setup(struct spi_d
+       if (ret < 0)
+               return ret;
+ 
+-      aq->scr = QSPI_SCR_SCBR(scbr);
++      aq->scr &= ~QSPI_SCR_SCBR_MASK;
++      aq->scr |= QSPI_SCR_SCBR(scbr);
+       atmel_qspi_write(aq->scr, aq, QSPI_SCR);
+ 
+       pm_runtime_mark_last_busy(ctrl->dev.parent);
+@@ -578,6 +579,7 @@ static int atmel_qspi_set_cs_timing(stru
+       if (ret < 0)
+               return ret;
+ 
++      aq->scr &= ~QSPI_SCR_DLYBS_MASK;
+       aq->scr |= QSPI_SCR_DLYBS(cs_setup);
+       atmel_qspi_write(aq->scr, aq, QSPI_SCR);
+ 
+@@ -593,8 +595,8 @@ static void atmel_qspi_init(struct atmel
+       atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
+ 
+       /* Set the QSPI controller by default in Serial Memory Mode */
+-      atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
+-      aq->mr = QSPI_MR_SMM;
++      aq->mr |= QSPI_MR_SMM;
++      atmel_qspi_write(aq->mr, aq, QSPI_MR);
+ 
+       /* Enable the QSPI controller */
+       atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);