]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
dt-bindings: clock: meson: a1: peripherals: support sys_pll input
authorDmitry Rokosov <ddrokosov@salutedevices.com>
Wed, 15 May 2024 18:47:27 +0000 (21:47 +0300)
committerJerome Brunet <jbrunet@baylibre.com>
Mon, 10 Jun 2024 10:16:45 +0000 (12:16 +0200)
The 'sys_pll' input is an optional clock that can be used to generate
'sys_pll_div16', which serves as one of the sources for the GEN clock.

Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240515185103.20256-5-ddrokosov@salutedevices.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h

index 6d84cee1bd756ebd15d6c1737eab62530fc27648..2568ad7dd0ac1b632b51d02fb975a20ef4875263 100644 (file)
@@ -30,6 +30,8 @@ properties:
       - description: input fixed pll div7
       - description: input hifi pll
       - description: input oscillator (usually at 24MHz)
+      - description: input sys pll
+    minItems: 6 # sys_pll is optional
 
   clock-names:
     items:
@@ -39,6 +41,8 @@ properties:
       - const: fclk_div7
       - const: hifi_pll
       - const: xtal
+      - const: sys_pll
+    minItems: 6 # sys_pll is optional
 
 required:
   - compatible
@@ -65,9 +69,10 @@ examples:
                      <&clkc_pll CLKID_FCLK_DIV5>,
                      <&clkc_pll CLKID_FCLK_DIV7>,
                      <&clkc_pll CLKID_HIFI_PLL>,
-                     <&xtal>;
+                     <&xtal>,
+                     <&clkc_pll CLKID_SYS_PLL>;
             clock-names = "fclk_div2", "fclk_div3",
                           "fclk_div5", "fclk_div7",
-                          "hifi_pll", "xtal";
+                          "hifi_pll", "xtal", "sys_pll";
         };
     };
index 06f198ee7623f6dc32c830949dd7cbc04da7613d..2ce1a06dc735201dbba61d08bcf7e66948647b7b 100644 (file)
 #define CLKID_DMC_SEL          151
 #define CLKID_DMC_DIV          152
 #define CLKID_DMC_SEL2         153
+#define CLKID_SYS_PLL_DIV16    154
 
 #endif /* __A1_PERIPHERALS_CLKC_H */