]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
Revert "drm/nouveau: set DMA mask before creating the flush page"
authorDave Airlie <airlied@redhat.com>
Sat, 8 Nov 2025 09:41:09 +0000 (19:41 +1000)
committerDave Airlie <airlied@redhat.com>
Sat, 8 Nov 2025 09:41:09 +0000 (19:41 +1000)
This reverts commit ebe755605082eddff80eafe0c50915b1366ee98f.

Tested the latest kernel on my GB203 and this seems to break it somehow.

Nov 09 04:16:14 bighp kernel: nouveau 0000:02:00.0: gsp: GSP-FMC boot failed (mbox: 0x0000000b)
Nov 09 04:16:14 bighp kernel: nouveau 0000:02:00.0: gsp: init failed, -5
Nov 09 04:16:14 bighp kernel: nouveau 0000:02:00.0: init failed with -5
Nov 09 04:16:14 bighp kernel: nouveau: drm:00000000:00000080: init failed with -5
Nov 09 04:16:14 bighp kernel: nouveau 0000:02:00.0: drm: Device allocation failed: -5
Nov 09 04:16:14 bighp kernel: nouveau 0000:02:00.0: probe with driver nouveau failed with error -5

Not sure why, I went over the patch and thought it should have worked, but there must be some
32-bit problem maybe in the FMC boot path.

Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c

index 7cc5a7499583788d7278a49cf771719a3a62a63b..8f0261a0d618bf9995b379179743b1df4934b144 100644 (file)
@@ -1695,18 +1695,6 @@ nvkm_device_pci_new(struct pci_dev *pci_dev, const char *cfg, const char *dbg,
        *pdevice = &pdev->device;
        pdev->pdev = pci_dev;
 
-       /* Set DMA mask based on capabilities reported by the MMU subdev. */
-       if (pdev->device.mmu && !pdev->device.pci->agp.bridge)
-               bits = pdev->device.mmu->dma_bits;
-       else
-               bits = 32;
-
-       ret = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(bits));
-       if (ret && bits != 32) {
-               dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32));
-               pdev->device.mmu->dma_bits = 32;
-       }
-
        ret = nvkm_device_ctor(&nvkm_device_pci_func, quirk, &pci_dev->dev,
                               pci_is_pcie(pci_dev) ? NVKM_DEVICE_PCIE :
                               pci_find_capability(pci_dev, PCI_CAP_ID_AGP) ?
@@ -1720,5 +1708,17 @@ nvkm_device_pci_new(struct pci_dev *pci_dev, const char *cfg, const char *dbg,
        if (ret)
                return ret;
 
+       /* Set DMA mask based on capabilities reported by the MMU subdev. */
+       if (pdev->device.mmu && !pdev->device.pci->agp.bridge)
+               bits = pdev->device.mmu->dma_bits;
+       else
+               bits = 32;
+
+       ret = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(bits));
+       if (ret && bits != 32) {
+               dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32));
+               pdev->device.mmu->dma_bits = 32;
+       }
+
        return 0;
 }