media: imx-mipi-csis: Use GENMASK for all register field masks

Multiple register field mask macros use GENMASK, while other define the
mask value manually. Standardize on GENMASK everywhere, as well as on
the _MASK suffix to name the macros. This improves consistency and helps
with readability.

No functional change is intended.

Link: https://lore.kernel.org/r/20250822002734.23516-7-laurent.pinchart@ideasonboard.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>

diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/platform/nxp/imx-mipi-csis.c
index ce889c436cb16f893a6ff9458755305c20494fe0..50f6f4468f7b05c5fc637549c3dd3571a2288251 100644 (file)
--- a/drivers/media/platform/nxp/imx-mipi-csis.c
+++ b/drivers/media/platform/nxp/imx-mipi-csis.c
@@ -57,7 +57,7 @@
 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW       BIT(16)
 #define MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT  BIT(10)
 #define MIPI_CSIS_CMN_CTRL_LANE_NUMBER(n)      ((n) << 8)
-#define MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK    (3 << 8)
+#define MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK    GENMASK(9, 8)
 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL  BIT(2)
 #define MIPI_CSIS_CMN_CTRL_SW_RESET            BIT(1)
 #define MIPI_CSIS_CMN_CTRL_CSI_EN              BIT(0)
@@ -68,7 +68,7 @@
 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x)        ((x) << 24)
 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x)        ((x) << 20)
 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x)        ((x) << 16)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK      (0xf << 4)
+#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK     GENMASK(7, 4)
 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC            BIT(0)
 
 /* CSIS Interrupt mask */
@@ -173,15 +173,15 @@
 
 /* ISP Configuration register */
 #define MIPI_CSIS_ISP_CONFIG_CH(n)             (0x40 + (n) * 0x10)
-#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK      (0xff << 24)
+#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MASK     GENMASK(31, 24)
 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x)       ((x) << 24)
 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE     (0 << 12)
 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL       (1 << 12)
 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD       (2 << 12)       /* i.MX8M[MNP] only */
-#define MIPI_CSIS_ISPCFG_PIXEL_MODE_MASK       (3 << 12)
+#define MIPI_CSIS_ISPCFG_PIXEL_MODE_MASK       GENMASK(13, 12)
 #define MIPI_CSIS_ISPCFG_PARALLEL              BIT(11)
 #define MIPI_CSIS_ISPCFG_DATAFORMAT(fmt)       ((fmt) << 2)
-#define MIPI_CSIS_ISPCFG_DATAFORMAT_MASK       (0x3f << 2)
+#define MIPI_CSIS_ISPCFG_DATAFORMAT_MASK       GENMASK(7, 2)
 
 /* ISP Image Resolution register */
 #define MIPI_CSIS_ISP_RESOL_CH(n)              (0x44 + (n) * 0x10)
@@ -655,7 +655,7 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
        val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
        val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
        val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
-       val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
+       val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK;
        mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
 
        mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L,