arm64/sysreg: Convert LORC_EL1 to automatic generation

Convert LORC_EL1 to automatic register generation as per DDI0487H.a, no
functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-26-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 78e61eb25effd3300211caa7e1424e692f6bd4f4..261b42b88e9f9599a073f87663798df71cd2c073 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -407,7 +407,6 @@
 #define SYS_MAIR_EL1                   sys_reg(3, 0, 10, 2, 0)
 #define SYS_AMAIR_EL1                  sys_reg(3, 0, 10, 3, 0)
 
-#define SYS_LORC_EL1                   sys_reg(3, 0, 10, 4, 3)
 #define SYS_LORID_EL1                  sys_reg(3, 0, 10, 4, 7)
 
 #define SYS_VBAR_EL1                   sys_reg(3, 0, 12, 0, 0)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index ec84a76fe66e6e0b4e0a284b01864622bd502ee6..95fcad79b91744515dd066ef508eaf3f5e142932 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -534,3 +534,10 @@ Sysreg     LORN_EL1        3       0       10      4       2
 Res0   63:8
 Field  7:0     Num
 EndSysreg
+
+Sysreg LORC_EL1        3       0       10      4       3
+Res0   63:10
+Field  9:2     DS
+Res0   1
+Field  0       EN
+EndSysreg