riscv: dts: spacemit: enable K1 SoC QSPI on BPI-F3

Define DTS nodes to enable support for QSPI on the K1 SoC, including the
pin control configuration used.  Enable QSPI on the Banana Pi BPI-F3 board.

Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://lore.kernel.org/r/20251027133008.360237-9-elder@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>

diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 33ca816bfd4b395848df2ebb977a0c31cac3fdf7..02f218a16318e5b6f512bcc37035fac37c25ee84 100644 (file)
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -113,6 +113,12 @@
        status = "okay";
 };
 
+&qspi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&qspi_cfg>;
+       status = "okay";
+};
+
 &i2c2 {
        pinctrl-0 = <&i2c2_0_cfg>;
        pinctrl-names = "default";

diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
index 4eef81d583f3dd37f61b5f365ee32e0477c6c944..e922e05ff856df78c90978b0bb312e5d20ef121a 100644 (file)
--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
@@ -73,6 +73,27 @@
                };
        };
 
+       qspi_cfg: qspi-cfg {
+               qspi-pins {
+                       pinmux = <K1_PADCONF(98, 0)>,    /* QSPI_DATA3 */
+                                <K1_PADCONF(99, 0)>,    /* QSPI_DATA2 */
+                                <K1_PADCONF(100, 0)>,   /* QSPI_DATA1 */
+                                <K1_PADCONF(101, 0)>,   /* QSPI_DATA0 */
+                                <K1_PADCONF(102, 0)>;   /* QSPI_CLK */
+
+                       bias-disable;
+                       drive-strength = <19>;
+                       power-source = <3300>;
+               };
+
+               qspi-cs1-pins {
+                       pinmux = <K1_PADCONF(103, 0)>;   /* QSPI_CS1 */
+                       bias-pull-up = <0>;
+                       drive-strength = <19>;
+                       power-source = <3300>;
+               };
+       };
+
        /omit-if-no-ref/
        uart0_0_cfg: uart0-0-cfg {
                uart0-0-pins {

diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index af35f9cd643513a1c68a00ccfb3ead688a8b1929..47f97105bff0ba860b034845e4baa2f911d2645c 100644 (file)
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -823,6 +823,22 @@
                                status = "disabled";
                        };
 
+                       qspi: spi@d420c000 {
+                               compatible = "spacemit,k1-qspi";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               reg = <0x0 0xd420c000 0x0 0x1000>,
+                                     <0x0 0xb8000000 0x0 0xc00000>;
+                               reg-names = "QuadSPI", "QuadSPI-memory";
+                               clocks = <&syscon_apmu CLK_QSPI_BUS>,
+                                        <&syscon_apmu CLK_QSPI>;
+                               clock-names = "qspi_en", "qspi";
+                               resets = <&syscon_apmu RESET_QSPI>,
+                                        <&syscon_apmu RESET_QSPI_BUS>;
+                               interrupts = <117>;
+                               status = "disabled";
+                       };
+
                        /* sec_uart1: 0xf0612000, not available from Linux */
                };