]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: rockchip: add PCIe network controller to rock-5b
authorSebastian Reichel <sebastian.reichel@collabora.com>
Mon, 18 Sep 2023 14:14:49 +0000 (16:14 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Wed, 4 Oct 2023 21:08:47 +0000 (23:08 +0200)
Enable the RTL8125 network controller, which is connected via
PCIe.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230918141451.131247-2-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts

index 8ab60968f27502b1107741f3a95c920a89cbefbd..0752b0fb4b54a1c1112b3eb052228d85ed3debac 100644 (file)
                #cooling-cells = <2>;
        };
 
+       vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc3v3_pcie2x1l2";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               startup-delay-us = <5000>;
+               vin-supply = <&vcc_3v3_s3>;
+       };
+
        vcc5v0_host: vcc5v0-host-regulator {
                compatible = "regulator-fixed";
                regulator-name = "vcc5v0_host";
        };
 };
 
+&combphy0_ps {
+       status = "okay";
+};
+
 &cpu_b0 {
        cpu-supply = <&vdd_cpu_big0_s0>;
 };
        };
 };
 
+&pcie2x1l2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie2_2_rst>;
+       reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+       vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
+       status = "okay";
+};
+
 &pinctrl {
        hym8563 {
                hym8563_int: hym8563-int {
                };
        };
 
+       pcie2 {
+               pcie2_2_rst: pcie2-2-rst {
+                       rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
        usb {
                vcc5v0_host_en: vcc5v0-host-en {
                        rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;