#define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
#define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
#define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
-#define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
+#define OPTION_MASK_ISA_VPCLMULQDQ_SET \
+ (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_PCLMUL_SET \
+ | OPTION_MASK_ISA_AVX_SET)
#define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
#define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
#define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
#define OPTION_MASK_ISA_AVX_UNSET \
(OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
| OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
- | OPTION_MASK_ISA_AVX2_UNSET )
+ | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
#define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
#define OPTION_MASK_ISA_XSAVE_UNSET \
#define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
#define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
-#define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
+#define OPTION_MASK_ISA_PCLMUL_UNSET \
+ (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
#define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
#define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
#define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
avx512bw,noavx512bw,avx512dq,noavx512dq,fma_or_avx512vl,
avx512vl,noavx512vl,avxvnni,avx512vnnivl,avx512fp16,avxifma,
- avx512ifmavl,avxneconvert,avx512bf16vl"
+ avx512ifmavl,avxneconvert,avx512bf16vl,vpclmulqdqvl"
(const_string "base"))
;; Define instruction set of MMX instructions
(eq_attr "isa" "avxneconvert") (symbol_ref "TARGET_AVXNECONVERT")
(eq_attr "isa" "avx512bf16vl")
(symbol_ref "TARGET_AVX512BF16 && TARGET_AVX512VL")
+ (eq_attr "isa" "vpclmulqdqvl")
+ (symbol_ref "TARGET_VPCLMULQDQ && TARGET_AVX512VL")
(eq_attr "mmx_isa" "native")
(symbol_ref "!TARGET_MMX_WITH_SSE")
(set_attr "mode" "TI")])
(define_insn "pclmulqdq"
- [(set (match_operand:V2DI 0 "register_operand" "=x,x")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x")
- (match_operand:V2DI 2 "vector_operand" "xBm,xm")
+ [(set (match_operand:V2DI 0 "register_operand" "=x,x,v")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v")
+ (match_operand:V2DI 2 "vector_operand" "xBm,xm,vm")
(match_operand:SI 3 "const_0_to_255_operand")]
UNSPEC_PCLMUL))]
"TARGET_PCLMUL"
"@
pclmulqdq\t{%3, %2, %0|%0, %2, %3}
+ vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}
vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "isa" "noavx,avx")
+ [(set_attr "isa" "noavx,avx,vpclmulqdqvl")
(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
- (set_attr "prefix" "orig,vex")
+ (set_attr "prefix" "orig,vex,evex")
(set_attr "mode" "TI")])
(define_expand "avx_vzeroall"
#pragma GCC pop_options
#endif /* __DISABLE_VPCLMULQDQF__ */
-#if !defined(__VPCLMULQDQ__) || !defined(__AVX__)
+#if !defined(__VPCLMULQDQ__)
#pragma GCC push_options
-#pragma GCC target("vpclmulqdq,avx")
+#pragma GCC target("vpclmulqdq")
#define __DISABLE_VPCLMULQDQ__
#endif /* __VPCLMULQDQ__ */
/* { dg-options "-mvpclmulqdq -mavx512vl -mavx512f -O2" } */
/* { dg-final { scan-assembler-times "vpclmulqdq\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vpclmulqdq\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpclmulqdq\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
#include <x86intrin.h>
volatile __m512i x1, x2;
volatile __m256i x3, x4;
+volatile __m128i x5, x6;
void extern
avx512vl_test (void)
{
x1 = _mm512_clmulepi64_epi128(x1, x2, 3);
x3 = _mm256_clmulepi64_epi128(x3, x4, 3);
+ x5 = _mm_clmulepi64_si128(x5, x6, 3);
}