drm/i915/dmc: Limit pipe DMC clock gating w/a to just ADL/DG2/MTL

Supposedly nothing post-MTL (even BMG) needs the pipe DMC clock
gating w/a (Wa_16015201720), so don't apply it.

TODO: check if the ADL/DG2 "clock gating needed during DMC loading" part
      is actually needed, not seeing anything in the docs about it...

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-2-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 1295d8245a2ee4eda48f7ce3fb3d4f22872aaf8b..1d748b9dca443bd98d1888ca4e3039adf864b668 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -488,7 +488,7 @@ static void mtl_pipedmc_clock_gating_wa(struct intel_display *display)
 
 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
 {
-       if (DISPLAY_VER(display) >= 14 && enable)
+       if (display->platform.meteorlake && enable)
                mtl_pipedmc_clock_gating_wa(display);
        else if (DISPLAY_VER(display) == 13)
                adlp_pipedmc_clock_gating_wa(display, enable);