drm/amdgpu: add set_reg_remap callback for NBIO 7.11

This will be used to consolidate the register remap offset
configuration and fix  HDP flushes on systems non-4K pages.

Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
index 05020141c0aeb5dd40a8e540c8a99d6953a39639..7a9adfda5814a651f982883ade25e74290614e3d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
@@ -352,6 +352,20 @@ static void nbio_v7_11_get_clockgating_state(struct amdgpu_device *adev,
                *flags |= AMD_CG_SUPPORT_BIF_LS;
 }
 
+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
+
+static void nbio_v7_11_set_reg_remap(struct amdgpu_device *adev)
+{
+       if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
+               adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
+               adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+       } else {
+               adev->rmmio_remap.reg_offset =
+                       SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
+               adev->rmmio_remap.bus_addr = 0;
+       }
+}
+
 const struct amdgpu_nbio_funcs nbio_v7_11_funcs = {
        .get_hdp_flush_req_offset = nbio_v7_11_get_hdp_flush_req_offset,
        .get_hdp_flush_done_offset = nbio_v7_11_get_hdp_flush_done_offset,
@@ -374,4 +388,5 @@ const struct amdgpu_nbio_funcs nbio_v7_11_funcs = {
        .ih_control = nbio_v7_11_ih_control,
        .init_registers = nbio_v7_11_init_registers,
        .remap_hdp_registers = nbio_v7_11_remap_hdp_registers,
+       .set_reg_remap = nbio_v7_11_set_reg_remap,
 };