+2025-01-17 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR rtl-optimization/118067
+ * lra-constraints.cc (invalid_mode_reg_p): New function.
+ (curr_insn_transform): Use it to check mode returned by target
+ secondary_memory_needed_mode.
+
+2025-01-17 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/118511
+ * config/s390/s390.cc (print_operand) <case 'p'>: Use
+ output_operand_lossage instead of gcc_checking_assert.
+ (print_operand) <case 'q'>: Likewise.
+ (print_operand) <case 'r'>: Likewise.
+
+2025-01-17 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64-sve.md: Rename insns
+
+2025-01-17 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64-builtins.cc: Expand iterators.
+ * config/aarch64/aarch64-simd-builtins.def: Use standard names
+ * config/aarch64/aarch64-simd.md: Use standard names, split insn
+ definitions on signedness of operator and type of operands.
+ * config/aarch64/arm_neon.h: Use standard builtin names.
+ * config/aarch64/iterators.md: Add VSDQ_I_QI_HI iterator to
+ simplify splitting of insn for unsigned scalar arithmetic.
+
+2025-01-17 Carl Love <cel@linux.ibm.com>
+
+ * config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvuxwdp):
+ Remove built-in definition.
+
+2025-01-17 Carl Love <cel@linux.ibm.com>
+
+ * config/rs6000/rs6000-builtins.def (__builtin_vsx_vperm_8hi,
+ __builtin_vsx_vperm_8hi_uns): Remove built-in definitions.
+
+2025-01-17 Carl Love <cel@linux.ibm.com>
+
+ * doc/extend.texi: Fix spelling mistake in description of the
+ vec_sel built-in. Add documentation of the 128-bit vec_perm
+ instance.
+
+2025-01-17 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr-c.cc (DEF_BUILTIN): Add ATTRS argument to macro
+ definition.
+ * config/avr/avr.cc: Same.
+ (avr_init_builtins) <attr_const>: New variable that can be used
+ as ATTRS argument in DEF_BUILTIN.
+ * config/avr/builtins.def (DEF_BUILTIN): Add ATTRS parameter
+ to all definitions.
+
+2025-01-17 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/118329
+ * config/avr/avr-modes.def: Add INT_N (PSI, 24).
+ * config/avr/avr.cc (avr_init_builtin_int24)
+ <__int24>: Remove definition.
+ <__uint24>: Adjust definition to INT_N interface.
+
+2025-01-17 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/118522
+ * match.pd ((FTYPE) N CMP (FTYPE) M): Add convert, as in GENERIC
+ integral types with the same precision and sign might actually not
+ be compatible types.
+
+2025-01-17 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/92539
+ * tree-ssa-loop-ivcanon.cc (tree_unroll_loops_completely_1):
+ Also try force-evaluation if ivcanon did not yet run.
+ (canonicalize_loop_induction_variables):
+ When niter was computed constant by force evaluation add a
+ canonical IV if we didn't unroll.
+ * tree-ssa-loop-niter.cc (loop_niter_by_eval): When we
+ don't find a proper PHI try if the exit condition scans
+ over a STRING_CST and simulate that.
+
+2025-01-17 Monk Chiang <monk.chiang@sifive.com>
+
+ * config/riscv/riscv.cc
+ (is_zicfilp_p): New function.
+ (is_zicfiss_p): New function.
+ * config/riscv/riscv-zicfilp.cc: Update.
+ * config/riscv/riscv.h: Update.
+ * config/riscv/riscv.md: Update.
+ * config/riscv/riscv-c.cc: Add CFI predefine marco.
+
+2025-01-17 Monk Chiang <monk.chiang@sifive.com>
+
+ * config/riscv/riscv.cc
+ (riscv_file_end): Add .note.gnu.property.
+
+2025-01-17 Monk Chiang <monk.chiang@sifive.com>
+
+ * common/config/riscv/riscv-common.cc: Add ZICFILP ISA
+ string.
+ * config.gcc: Add riscv-zicfilp.o
+ * config/riscv/riscv-passes.def (INSERT_PASS_BEFORE):
+ Insert landing pad instructions.
+ * config/riscv/riscv-protos.h (make_pass_insert_landing_pad):
+ Declare.
+ * config/riscv/riscv-zicfilp.cc: New file.
+ * config/riscv/riscv.cc
+ (riscv_trampoline_init): Add landing pad instructions.
+ (riscv_legitimize_call_address): Likewise.
+ (riscv_output_mi_thunk): Likewise.
+ * config/riscv/riscv.h: Update.
+ * config/riscv/riscv.md: Add landing pad patterns.
+ * config/riscv/riscv.opt (TARGET_ZICFILP): Define.
+ * config/riscv/t-riscv: Add build rule for
+ riscv-zicfilp.o
+
+2025-01-17 Monk Chiang <monk.chiang@sifive.com>
+
+ * common/config/riscv/riscv-common.cc: Add ZICFISS ISA string.
+ * config/riscv/predicates.md: New predicate x1x5_operand.
+ * config/riscv/riscv.cc
+ (riscv_expand_prologue): Insert shadow stack instructions.
+ (riscv_expand_epilogue): Likewise.
+ (riscv_for_each_saved_reg): Assign t0 or ra register for
+ sspopchk instruction.
+ (need_shadow_stack_push_pop_p): New function. Omit shadow
+ stack operation on leaf function.
+ * config/riscv/riscv.h
+ (need_shadow_stack_push_pop_p): Define.
+ * config/riscv/riscv.md: Add shadow stack patterns.
+ (save_stack_nonlocal): Add shadow stack instructions for setjump.
+ (restore_stack_nonlocal): Add shadow stack instructions for longjump.
+ * config/riscv/riscv.opt (TARGET_ZICFISS): Define.
+
2025-01-16 Tamar Christina <tamar.christina@arm.com>
Richard Sandiford <richard.sandiford@arm.com>
+2025-01-17 Harald Anlauf <anlauf@gmx.de>
+
+ PR libfortran/118536
+ * gfortran.dg/unsigned_write_2.f90: New test.
+
+2025-01-17 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ * gcc.target/i386/pr118067-2.c: New.
+
+2025-01-17 Jakub Jelinek <jakub@redhat.com>
+
+ * c-c++-common/cpp/embed-10.c: Allow a different error wording for
+ C++.
+
+2025-01-17 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ PR d/117115
+ * gdc.dg/pr117115.d: New test.
+
+2025-01-17 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/118511
+ * gcc.target/s390/pr118511.c: New test.
+
+2025-01-17 Tamar Christina <tamar.christina@arm.com>
+
+ * gcc.target/aarch64/sve/saturating_arithmetic.inc:
+ Template file for auto-vectorizer tests.
+ * gcc.target/aarch64/sve/saturating_arithmetic_1.c:
+ Instantiate 8-bit vector tests.
+ * gcc.target/aarch64/sve/saturating_arithmetic_2.c:
+ Instantiate 16-bit vector tests.
+ * gcc.target/aarch64/sve/saturating_arithmetic_3.c:
+ Instantiate 32-bit vector tests.
+ * gcc.target/aarch64/sve/saturating_arithmetic_4.c:
+ Instantiate 64-bit vector tests.
+
+2025-01-17 Tamar Christina <tamar.christina@arm.com>
+
+ * gcc.target/aarch64/scalar_intrinsics.c: Update testcases.
+ * gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect.inc:
+ Template file for unsigned vector saturating arithmetic tests.
+ * gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_1.c:
+ 8-bit vector type tests.
+ * gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_2.c:
+ 16-bit vector type tests.
+ * gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_3.c:
+ 32-bit vector type tests.
+ * gcc.target/aarch64/advsimd-intrinsics/saturating_arithmetic_autovect_4.c:
+ 64-bit vector type tests.
+ * gcc.target/aarch64/saturating_arithmetic.inc: Template file
+ for scalar saturating arithmetic tests.
+ * gcc.target/aarch64/saturating_arithmetic_1.c: 8-bit tests.
+ * gcc.target/aarch64/saturating_arithmetic_2.c: 16-bit tests.
+ * gcc.target/aarch64/saturating_arithmetic_3.c: 32-bit tests.
+ * gcc.target/aarch64/saturating_arithmetic_4.c: 64-bit tests.
+ * gcc.target/aarch64/saturating-arithmetic-signed.c: New file.
+
+2025-01-17 Carl Love <cel@linux.ibm.com>
+
+ * gcc.target/powerpc/vsx-builtin-3.c: Add vec_perm test cases for
+ arguments of type vector signed long long int, long long bool,
+ bool, bool short, bool char and pixel, vector unsigned long long
+ int, unsigned int, unsigned short int, unsigned char. Cast
+ arguments for debug prints to unsigned long long.
+ * gcc.target/powerpc/builtins-4-int128-runnable.c: Add vec_perm
+ test cases for signed and unsigned int128 arguments.
+
+2025-01-17 Carl Love <cel@linux.ibm.com>
+
+ * gcc.target/powerpc/builtins-1-p10-runnable.c: Remove #define
+ DEBUG. Replace vec_i_expected value with correct value.
+
+2025-01-17 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ PR c++/118049
+ * g++.dg/modules/auto-5_a.C: New test.
+ * g++.dg/modules/auto-5_b.C: New test.
+ * g++.dg/modules/auto-5_c.C: New test.
+ * g++.dg/modules/auto-6_a.H: New test.
+ * g++.dg/modules/auto-6_b.C: New test.
+
+2025-01-17 Tobias Burnus <tburnus@baylibre.com>
+
+ PR fortran/118321
+ * g++.dg/gomp/adjust-args-4.C: New test.
+
+2025-01-17 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ PR c++/118147
+ * g++.dg/cpp0x/nsdmi-defer7.C: New test.
+
+2025-01-17 Richard Biener <rguenther@suse.de>
+
+ PR testsuite/117958
+ * g++.dg/tree-ssa/pr117123.C: XFAIL parts on aarch64-*-*.
+
+2025-01-17 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/118329
+ * gcc.target/avr/pr115830-add.c (__int24, __uint24): Add __extension__
+ to respective typedefs.
+ * gcc.target/avr/pr115830-sub-ext.c: Same.
+ * gcc.target/avr/pr115830-sub.c: Same.
+ * gcc.target/avr/torture/get-mem.c: Same.
+ * gcc.target/avr/torture/set-mem.c: Same.
+ * gcc.target/avr/torture/ifelse-c.h: Same.
+ * gcc.target/avr/torture/ifelse-d.h: Same.
+ * gcc.target/avr/torture/ifelse-q.h: Same.
+ * gcc.target/avr/torture/ifelse-r.h: Same.
+ * gcc.target/avr/torture/int24-mul.c: Same.
+ * gcc.target/avr/torture/pr109907-2.c: Same.
+ * gcc.target/avr/torture/pr61443.c: Same.
+ * gcc.target/avr/torture/pr63633-ice-mult.c: Same.
+ * gcc.target/avr/torture/shift-l-u24.c: Same.
+ * gcc.target/avr/torture/shift-r-i24.c: Same.
+ * gcc.target/avr/torture/shift-r-u24.c: Same.
+ * gcc.target/avr/torture/add-extend.c: Same.
+ * gcc.target/avr/torture/sub-extend.c: Same.
+ * gcc.target/avr/torture/sub-zerox.c: Same.
+ * gcc.target/avr/torture/test-gprs.h: Same.
+
+2025-01-17 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/118522
+ * gcc.dg/bitint-120.c: New test.
+
+2025-01-17 Simon Martin <simon@nasilyan.com>
+
+ PR c++/118255
+ * g++.dg/lookup/pr99116-1.C: Adjust test expectation.
+ * g++.dg/template/friend84.C: New test.
+
+2025-01-17 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/92539
+ * g++.dg/warn/Warray-bounds-pr92539.C: New testcase.
+ * gcc.dg/tree-ssa/sccp-16.c: New testcase.
+ * g++.dg/vect/pr87621.cc: Use larger power to avoid
+ inner loop unrolling.
+ * gcc.dg/vect/pr89440.c: Use larger loop bound to avoid
+ inner loop unrolling.
+ * gcc.dg/pr77975.c: Scan cunrolli dump and adjust.
+
+2025-01-17 Sandra Loosemore <sloosemore@baylibre.com>
+
+ * c-c++-common/gomp/metadirective-device.c: Don't add extra options
+ for target ia32.
+ * c-c++-common/gomp/metadirective-target-device-1.c: Likewise.
+
+2025-01-17 Monk Chiang <monk.chiang@sifive.com>
+
+ * c-c++-common/fcf-protection-1.c: Update.
+ * c-c++-common/fcf-protection-2.c: Update.
+ * c-c++-common/fcf-protection-3.c: Update.
+ * c-c++-common/fcf-protection-4.c: Update.
+ * c-c++-common/fcf-protection-5.c: Update.
+ * c-c++-common/fcf-protection-6.c: Update.
+ * c-c++-common/fcf-protection-7.c: Update.
+ * gcc.target/riscv/ssp-1.c: Update.
+ * gcc.target/riscv/ssp-2.c: Update.
+ * gcc.target/riscv/zicfilp-call.c: Update.
+ * gcc.target/riscv/interrupt-no-lpad.c: Update.
+
+2025-01-17 Monk Chiang <monk.chiang@sifive.com>
+
+ * gcc.target/riscv/interrupt-no-lpad.c: New test.
+ * gcc.target/riscv/zicfilp-call.c: New test.
+ Co-Developed-by: Greg McGary <gkm@rivosinc.com>,
+ Kito Cheng <kito.cheng@gmail.com>
+
+2025-01-17 Monk Chiang <monk.chiang@sifive.com>
+
+ * gcc.target/riscv/ssp-1.c: New test.
+ * gcc.target/riscv/ssp-2.c: New test.
+ Co-Developed-by: Greg McGary <gkm@rivosinc.com>,
+ Kito Cheng <kito.cheng@gmail.com>
+
2025-01-16 Patrick Palka <ppalka@redhat.com>
PR c++/105440
projects / thirdparty / gcc.git / commitdiff
