ice: Adjust PTP init for 2x50G E825C devices

>From FW/HW perspective, 2 port topology in E825C devices requires
merging of 2 port mapping internally and breakout mapping externally.
As a consequence, it requires different port numbering from PTP code
perspective.
For that topology, pf_id can not be used to index PTP ports. Even if
the 2nd port is identified as port with pf_id = 1, all PHY operations
need to be performed as it was port 2. Thus, special mapping is needed
for the 2nd port.
This change adds detection of 2x50G topology and applies 'custom'
mapping on the 2nd port.

Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Link: https://lore.kernel.org/r/20240528-next-2024-05-28-ptp-refactors-v1-11-c082739bb6f6@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
index cfac1d432c155069b47cf18c2293cc168d7064c4..91cbae1eec89a0b7267a799a6d2445ff72a31783 100644 (file)
--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h
@@ -157,6 +157,8 @@
 #define GLGEN_RTRIG_CORER_M                    BIT(0)
 #define GLGEN_RTRIG_GLOBR_M                    BIT(1)
 #define GLGEN_STAT                             0x000B612C
+#define GLGEN_SWITCH_MODE_CONFIG               0x000B81E0
+#define GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M   BIT(2)
 #define GLGEN_VFLRSTAT(_i)                     (0x00093A04 + ((_i) * 4))
 #define PFGEN_CTRL                             0x00091000
 #define PFGEN_CTRL_PFSWR_M                     BIT(0)
@@ -177,6 +179,8 @@
 #define GLINT_CTL_ITR_GRAN_50_M                        ICE_M(0xF, 24)
 #define GLINT_CTL_ITR_GRAN_25_S                        28
 #define GLINT_CTL_ITR_GRAN_25_M                        ICE_M(0xF, 28)
+#define GLGEN_MAC_LINK_TOPO                    0x000B81DC
+#define GLGEN_MAC_LINK_TOPO_LINK_TOPO_M                GENMASK(1, 0)
 #define GLINT_DYN_CTL(_INT)                    (0x00160000 + ((_INT) * 4))
 #define GLINT_DYN_CTL_INTENA_M                 BIT(0)
 #define GLINT_DYN_CTL_CLEARPBA_M               BIT(1)

diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
index 3af0f4a2c3be8933a50e01b816a76c1b15ed670b..adbb9cffe20c202747db01d702a773d92b10bb37 100644 (file)
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -1469,6 +1469,8 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
                return;
 
        ptp_port = &pf->ptp.port;
+       if (ice_is_e825c(hw) && hw->ptp.is_2x50g_muxed_topo)
+               port *= 2;
        if (WARN_ON_ONCE(ptp_port->port_num != port))
                return;
 
@@ -3282,6 +3284,9 @@ void ice_ptp_init(struct ice_pf *pf)
        }
 
        ptp->port.port_num = hw->pf_id;
+       if (ice_is_e825c(hw) && hw->ptp.is_2x50g_muxed_topo)
+               ptp->port.port_num = hw->pf_id * 2;
+
        err = ice_ptp_init_port(pf, &ptp->port);
        if (err)
                goto err;

diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 2c41921f76e80ecafec0cfdcdbbd8b4b6cb996ae..1e9a4ccd0ea2783f0c96c5c5cfd120bd89296982 100644 (file)
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -2644,6 +2644,26 @@ static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port,
        return 0;
 }
 
+/**
+ * ice_is_muxed_topo - detect breakout 2x50G topology for E825C
+ * @hw: pointer to the HW struct
+ *
+ * Return: true if it's 2x50 breakout topology, false otherwise
+ */
+static bool ice_is_muxed_topo(struct ice_hw *hw)
+{
+       u8 link_topo;
+       bool mux;
+       u32 val;
+
+       val = rd32(hw, GLGEN_SWITCH_MODE_CONFIG);
+       mux = FIELD_GET(GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M, val);
+       val = rd32(hw, GLGEN_MAC_LINK_TOPO);
+       link_topo = FIELD_GET(GLGEN_MAC_LINK_TOPO_LINK_TOPO_M, val);
+
+       return (mux && link_topo == ICE_LINK_TOPO_UP_TO_2_LINKS);
+}
+
 /**
  * ice_ptp_init_phy_e825c - initialize PHY parameters
  * @hw: pointer to the HW struct
@@ -2676,6 +2696,8 @@ static void ice_ptp_init_phy_e825c(struct ice_hw *hw)
                        return;
                }
        }
+
+       ptp->is_2x50g_muxed_topo = ice_is_muxed_topo(hw);
 }
 
 /* E822 family functions

diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h
index 841860784e3ce9c67862f50bbd98341cec5ff26d..5f0da6850b03b5358418b41d6fee3b00d44fe0e1 100644 (file)
--- a/drivers/net/ethernet/intel/ice/ice_type.h
+++ b/drivers/net/ethernet/intel/ice/ice_type.h
@@ -853,11 +853,20 @@ enum ice_phy_model {
        ICE_PHY_ETH56G,
 };
 
+/* Global Link Topology */
+enum ice_global_link_topo {
+       ICE_LINK_TOPO_UP_TO_2_LINKS,
+       ICE_LINK_TOPO_UP_TO_4_LINKS,
+       ICE_LINK_TOPO_UP_TO_8_LINKS,
+       ICE_LINK_TOPO_RESERVED,
+};
+
 struct ice_ptp_hw {
        enum ice_phy_model phy_model;
        union ice_phy_params phy;
        u8 num_lports;
        u8 ports_per_phy;
+       bool is_2x50g_muxed_topo;
 };
 
 /* Port hardware description */