arm64: dts: qcom: sdm670: add camss and cci

Add the camera subsystem and CCI used to interface with cameras on the
Snapdragon 670.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250205035013.206890-8-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 3ecf41cf2b879b875ddc868cda891ea318a96cc3..c33f3de779f6ef457a3336fa4fbe39175c378cce 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -6,6 +6,7 @@
  * Copyright (c) 2022, Richard Acayan. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
@@ -1189,6 +1190,34 @@
                        gpio-ranges = <&tlmm 0 0 151>;
                        wakeup-parent = <&pdc>;
 
+                       cci0_default: cci0-default-state {
+                               pins = "gpio17", "gpio18";
+                               function = "cci_i2c";
+                               drive-strength = <2>;
+                               bias-pull-up;
+                       };
+
+                       cci0_sleep: cci0-sleep-state {
+                               pins = "gpio17", "gpio18";
+                               function = "cci_i2c";
+                               drive-strength = <2>;
+                               bias-pull-down;
+                       };
+
+                       cci1_default: cci1-default-state {
+                               pins = "gpio19", "gpio20";
+                               function = "cci_i2c";
+                               drive-strength = <2>;
+                               bias-pull-up;
+                       };
+
+                       cci1_sleep: cci1-sleep-state {
+                               pins = "gpio19", "gpio20";
+                               function = "cci_i2c";
+                               drive-strength = <2>;
+                               bias-pull-down;
+                       };
+
                        qup_i2c0_default: qup-i2c0-default-state {
                                pins = "gpio0", "gpio1";
                                function = "qup0";
@@ -1595,6 +1624,174 @@
                        #interrupt-cells = <4>;
                };
 
+               cci: cci@ac4a000 {
+                       compatible = "qcom,sdm670-cci", "qcom,msm8996-cci";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       reg = <0 0x0ac4a000 0 0x4000>;
+                       interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+                       power-domains = <&camcc TITAN_TOP_GDSC>;
+
+                       clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+                                <&camcc CAM_CC_SOC_AHB_CLK>,
+                                <&camcc CAM_CC_CPAS_AHB_CLK>,
+                                <&camcc CAM_CC_CCI_CLK>;
+                       clock-names = "camnoc_axi",
+                                     "soc_ahb",
+                                     "cpas_ahb",
+                                     "cci";
+
+                       pinctrl-names = "default", "sleep";
+                       pinctrl-0 = <&cci0_default &cci1_default>;
+                       pinctrl-1 = <&cci0_sleep &cci1_sleep>;
+
+                       status = "disabled";
+
+                       cci_i2c0: i2c-bus@0 {
+                               reg = <0>;
+                               clock-frequency = <1000000>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+
+                       cci_i2c1: i2c-bus@1 {
+                               reg = <1>;
+                               clock-frequency = <1000000>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+               };
+
+               camss: isp@acb3000 {
+                       compatible = "qcom,sdm670-camss";
+                       reg = <0 0x0acb3000 0 0x1000>,
+                             <0 0x0acba000 0 0x1000>,
+                             <0 0x0acc8000 0 0x1000>,
+                             <0 0x0ac65000 0 0x1000>,
+                             <0 0x0ac66000 0 0x1000>,
+                             <0 0x0ac67000 0 0x1000>,
+                             <0 0x0acaf000 0 0x4000>,
+                             <0 0x0acb6000 0 0x4000>,
+                             <0 0x0acc4000 0 0x4000>;
+                       reg-names = "csid0",
+                                   "csid1",
+                                   "csid2",
+                                   "csiphy0",
+                                   "csiphy1",
+                                   "csiphy2",
+                                   "vfe0",
+                                   "vfe1",
+                                   "vfe_lite";
+
+                       interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "csid0",
+                                         "csid1",
+                                         "csid2",
+                                         "csiphy0",
+                                         "csiphy1",
+                                         "csiphy2",
+                                         "vfe0",
+                                         "vfe1",
+                                         "vfe_lite";
+
+                       clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+                                <&camcc CAM_CC_CPAS_AHB_CLK>,
+                                <&camcc CAM_CC_IFE_0_CSID_CLK>,
+                                <&camcc CAM_CC_IFE_1_CSID_CLK>,
+                                <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+                                <&camcc CAM_CC_CSIPHY0_CLK>,
+                                <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+                                <&camcc CAM_CC_CSIPHY1_CLK>,
+                                <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+                                <&camcc CAM_CC_CSIPHY2_CLK>,
+                                <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+                                <&gcc GCC_CAMERA_AHB_CLK>,
+                                <&gcc GCC_CAMERA_AXI_CLK>,
+                                <&camcc CAM_CC_SOC_AHB_CLK>,
+                                <&camcc CAM_CC_IFE_0_CLK>,
+                                <&camcc CAM_CC_IFE_0_AXI_CLK>,
+                                <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+                                <&camcc CAM_CC_IFE_1_CLK>,
+                                <&camcc CAM_CC_IFE_1_AXI_CLK>,
+                                <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+                                <&camcc CAM_CC_IFE_LITE_CLK>,
+                                <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>;
+                       clock-names = "camnoc_axi",
+                                     "cpas_ahb",
+                                     "csi0",
+                                     "csi1",
+                                     "csi2",
+                                     "csiphy0",
+                                     "csiphy0_timer",
+                                     "csiphy1",
+                                     "csiphy1_timer",
+                                     "csiphy2",
+                                     "csiphy2_timer",
+                                     "gcc_camera_ahb",
+                                     "gcc_camera_axi",
+                                     "soc_ahb",
+                                     "vfe0",
+                                     "vfe0_axi",
+                                     "vfe0_cphy_rx",
+                                     "vfe1",
+                                     "vfe1_axi",
+                                     "vfe1_cphy_rx",
+                                     "vfe_lite",
+                                     "vfe_lite_cphy_rx";
+
+                       iommus = <&apps_smmu 0x808 0x0>,
+                                <&apps_smmu 0x810 0x8>,
+                                <&apps_smmu 0xc08 0x0>,
+                                <&apps_smmu 0xc10 0x8>;
+
+                       power-domains = <&camcc IFE_0_GDSC>,
+                                       <&camcc IFE_1_GDSC>,
+                                       <&camcc TITAN_TOP_GDSC>;
+                       power-domain-names = "ife0",
+                                            "ife1",
+                                            "top";
+
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+
+                                       camss_endpoint0: endpoint {
+                                               status = "disabled";
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+
+                                       camss_endpoint1: endpoint {
+                                               status = "disabled";
+                                       };
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+
+                                       camss_endpoint2: endpoint {
+                                               status = "disabled";
+                                       };
+                               };
+                       };
+               };
+
                camcc: clock-controller@ad00000 {
                        compatible = "qcom,sdm670-camcc", "qcom,sdm845-camcc";
                        reg = <0 0x0ad00000 0 0x10000>;