--- /dev/null
+From 5ff9ede85c2aafe3df8acdb210fc3d6dc825ec99 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 11 Feb 2025 18:15:59 +0100
+Subject: acct: perform last write from workqueue
+
+From: Christian Brauner <brauner@kernel.org>
+
+[ Upstream commit 56d5f3eba3f5de0efdd556de4ef381e109b973a9 ]
+
+In [1] it was reported that the acct(2) system call can be used to
+trigger NULL deref in cases where it is set to write to a file that
+triggers an internal lookup. This can e.g., happen when pointing acc(2)
+to /sys/power/resume. At the point the where the write to this file
+happens the calling task has already exited and called exit_fs(). A
+lookup will thus trigger a NULL-deref when accessing current->fs.
+
+Reorganize the code so that the the final write happens from the
+workqueue but with the caller's credentials. This preserves the
+(strange) permission model and has almost no regression risk.
+
+This api should stop to exist though.
+
+Link: https://lore.kernel.org/r/20250127091811.3183623-1-quzicheng@huawei.com [1]
+Link: https://lore.kernel.org/r/20250211-work-acct-v1-1-1c16aecab8b3@kernel.org
+Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
+Reported-by: Zicheng Qu <quzicheng@huawei.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Christian Brauner <brauner@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/acct.c | 120 +++++++++++++++++++++++++++++---------------------
+ 1 file changed, 70 insertions(+), 50 deletions(-)
+
+diff --git a/kernel/acct.c b/kernel/acct.c
+index cdfe1b0ce0e39..bddb31472f9e2 100644
+--- a/kernel/acct.c
++++ b/kernel/acct.c
+@@ -85,48 +85,50 @@ struct bsd_acct_struct {
+ atomic_long_t count;
+ struct rcu_head rcu;
+ struct mutex lock;
+- int active;
++ bool active;
++ bool check_space;
+ unsigned long needcheck;
+ struct file *file;
+ struct pid_namespace *ns;
+ struct work_struct work;
+ struct completion done;
++ acct_t ac;
+ };
+
+-static void do_acct_process(struct bsd_acct_struct *acct);
++static void fill_ac(struct bsd_acct_struct *acct);
++static void acct_write_process(struct bsd_acct_struct *acct);
+
+ /*
+ * Check the amount of free space and suspend/resume accordingly.
+ */
+-static int check_free_space(struct bsd_acct_struct *acct)
++static bool check_free_space(struct bsd_acct_struct *acct)
+ {
+ struct kstatfs sbuf;
+
+- if (time_is_after_jiffies(acct->needcheck))
+- goto out;
++ if (!acct->check_space)
++ return acct->active;
+
+ /* May block */
+ if (vfs_statfs(&acct->file->f_path, &sbuf))
+- goto out;
++ return acct->active;
+
+ if (acct->active) {
+ u64 suspend = sbuf.f_blocks * SUSPEND;
+ do_div(suspend, 100);
+ if (sbuf.f_bavail <= suspend) {
+- acct->active = 0;
++ acct->active = false;
+ pr_info("Process accounting paused\n");
+ }
+ } else {
+ u64 resume = sbuf.f_blocks * RESUME;
+ do_div(resume, 100);
+ if (sbuf.f_bavail >= resume) {
+- acct->active = 1;
++ acct->active = true;
+ pr_info("Process accounting resumed\n");
+ }
+ }
+
+ acct->needcheck = jiffies + ACCT_TIMEOUT*HZ;
+-out:
+ return acct->active;
+ }
+
+@@ -171,7 +173,11 @@ static void acct_pin_kill(struct fs_pin *pin)
+ {
+ struct bsd_acct_struct *acct = to_acct(pin);
+ mutex_lock(&acct->lock);
+- do_acct_process(acct);
++ /*
++ * Fill the accounting struct with the exiting task's info
++ * before punting to the workqueue.
++ */
++ fill_ac(acct);
+ schedule_work(&acct->work);
+ wait_for_completion(&acct->done);
+ cmpxchg(&acct->ns->bacct, pin, NULL);
+@@ -184,6 +190,9 @@ static void close_work(struct work_struct *work)
+ {
+ struct bsd_acct_struct *acct = container_of(work, struct bsd_acct_struct, work);
+ struct file *file = acct->file;
++
++ /* We were fired by acct_pin_kill() which holds acct->lock. */
++ acct_write_process(acct);
+ if (file->f_op->flush)
+ file->f_op->flush(file, NULL);
+ __fput_sync(file);
+@@ -426,12 +435,26 @@ static u32 encode_float(u64 value)
+ * do_exit() or when switching to a different output file.
+ */
+
+-static void fill_ac(acct_t *ac)
++static void fill_ac(struct bsd_acct_struct *acct)
+ {
+ struct pacct_struct *pacct = ¤t->signal->pacct;
++ struct file *file = acct->file;
++ acct_t *ac = &acct->ac;
+ u64 elapsed, run_time;
+ struct tty_struct *tty;
+
++ lockdep_assert_held(&acct->lock);
++
++ if (time_is_after_jiffies(acct->needcheck)) {
++ acct->check_space = false;
++
++ /* Don't fill in @ac if nothing will be written. */
++ if (!acct->active)
++ return;
++ } else {
++ acct->check_space = true;
++ }
++
+ /*
+ * Fill the accounting struct with the needed info as recorded
+ * by the different kernel functions.
+@@ -478,64 +501,61 @@ static void fill_ac(acct_t *ac)
+ ac->ac_majflt = encode_comp_t(pacct->ac_majflt);
+ ac->ac_exitcode = pacct->ac_exitcode;
+ spin_unlock_irq(¤t->sighand->siglock);
+-}
+-/*
+- * do_acct_process does all actual work. Caller holds the reference to file.
+- */
+-static void do_acct_process(struct bsd_acct_struct *acct)
+-{
+- acct_t ac;
+- unsigned long flim;
+- const struct cred *orig_cred;
+- struct file *file = acct->file;
+-
+- /*
+- * Accounting records are not subject to resource limits.
+- */
+- flim = rlimit(RLIMIT_FSIZE);
+- current->signal->rlim[RLIMIT_FSIZE].rlim_cur = RLIM_INFINITY;
+- /* Perform file operations on behalf of whoever enabled accounting */
+- orig_cred = override_creds(file->f_cred);
+
+- /*
+- * First check to see if there is enough free_space to continue
+- * the process accounting system.
+- */
+- if (!check_free_space(acct))
+- goto out;
+-
+- fill_ac(&ac);
+ /* we really need to bite the bullet and change layout */
+- ac.ac_uid = from_kuid_munged(file->f_cred->user_ns, orig_cred->uid);
+- ac.ac_gid = from_kgid_munged(file->f_cred->user_ns, orig_cred->gid);
++ ac->ac_uid = from_kuid_munged(file->f_cred->user_ns, current_uid());
++ ac->ac_gid = from_kgid_munged(file->f_cred->user_ns, current_gid());
+ #if ACCT_VERSION == 1 || ACCT_VERSION == 2
+ /* backward-compatible 16 bit fields */
+- ac.ac_uid16 = ac.ac_uid;
+- ac.ac_gid16 = ac.ac_gid;
++ ac->ac_uid16 = ac->ac_uid;
++ ac->ac_gid16 = ac->ac_gid;
+ #elif ACCT_VERSION == 3
+ {
+ struct pid_namespace *ns = acct->ns;
+
+- ac.ac_pid = task_tgid_nr_ns(current, ns);
++ ac->ac_pid = task_tgid_nr_ns(current, ns);
+ rcu_read_lock();
+- ac.ac_ppid = task_tgid_nr_ns(rcu_dereference(current->real_parent),
+- ns);
++ ac->ac_ppid = task_tgid_nr_ns(rcu_dereference(current->real_parent), ns);
+ rcu_read_unlock();
+ }
+ #endif
++}
++
++static void acct_write_process(struct bsd_acct_struct *acct)
++{
++ struct file *file = acct->file;
++ const struct cred *cred;
++ acct_t *ac = &acct->ac;
++
++ /* Perform file operations on behalf of whoever enabled accounting */
++ cred = override_creds(file->f_cred);
++
+ /*
+- * Get freeze protection. If the fs is frozen, just skip the write
+- * as we could deadlock the system otherwise.
++ * First check to see if there is enough free_space to continue
++ * the process accounting system. Then get freeze protection. If
++ * the fs is frozen, just skip the write as we could deadlock
++ * the system otherwise.
+ */
+- if (file_start_write_trylock(file)) {
++ if (check_free_space(acct) && file_start_write_trylock(file)) {
+ /* it's been opened O_APPEND, so position is irrelevant */
+ loff_t pos = 0;
+- __kernel_write(file, &ac, sizeof(acct_t), &pos);
++ __kernel_write(file, ac, sizeof(acct_t), &pos);
+ file_end_write(file);
+ }
+-out:
++
++ revert_creds(cred);
++}
++
++static void do_acct_process(struct bsd_acct_struct *acct)
++{
++ unsigned long flim;
++
++ /* Accounting records are not subject to resource limits. */
++ flim = rlimit(RLIMIT_FSIZE);
++ current->signal->rlim[RLIMIT_FSIZE].rlim_cur = RLIM_INFINITY;
++ fill_ac(acct);
++ acct_write_process(acct);
+ current->signal->rlim[RLIMIT_FSIZE].rlim_cur = flim;
+- revert_creds(orig_cred);
+ }
+
+ /**
+--
+2.39.5
+
--- /dev/null
+From ef54c35dbe20a4eb3b4a60db39fbbe9bba71f4d0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 18 Dec 2023 11:32:06 +0800
+Subject: drm/amdgpu: Check extended configuration space register when system
+ uses large bar
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ma Jun <Jun.Ma2@amd.com>
+
+[ Upstream commit e372baeb3d336b20fd9463784c577fd8824497cd ]
+
+Some customer platforms do not enable mmconfig for various reasons,
+such as bios bug, and therefore cannot access the GPU extend configuration
+space through mmio.
+
+When the system enters the d3cold state and resumes, the amdgpu driver
+fails to resume because the extend configuration space registers of
+GPU can't be restored. At this point, Usually we only see some failure
+dmesg log printed by amdgpu driver, it is difficult to find the root
+cause.
+
+Therefor print a warnning message if the system can't access the
+extended configuration space register when using large bar.
+
+Signed-off-by: Ma Jun <Jun.Ma2@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Stable-dep-of: 099bffc7cadf ("drm/amdgpu: disable BAR resize on Dell G5 SE")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 49fcb69ca4a1b..dc8ed896d05f0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -766,6 +766,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
++ /* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */
++ if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR))
++ DRM_WARN("System can't access extended configuration space,please check!!\n");
++
+ /* skip if the bios has already enabled large BAR */
+ if (adev->gmc.real_vram_size &&
+ (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
+--
+2.39.5
+
--- /dev/null
+From 14f4fd30ea0b92040a84e186ab4155dd499d5d48 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Feb 2025 10:55:05 -0500
+Subject: drm/amdgpu: disable BAR resize on Dell G5 SE
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+[ Upstream commit 099bffc7cadff40bfab1517c3461c53a7a38a0d7 ]
+
+There was a quirk added to add a workaround for a Sapphire
+RX 5600 XT Pulse that didn't allow BAR resizing. However,
+the quirk caused a regression with runtime pm on Dell laptops
+using those chips, rather than narrowing the scope of the
+resizing quirk, add a quirk to prevent amdgpu from resizing
+the BAR on those Dell platforms unless runtime pm is disabled.
+
+v2: update commit message, add runpm check
+
+Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1707
+Fixes: 907830b0fc9e ("PCI: Add a REBAR size quirk for Sapphire RX 5600 XT Pulse")
+Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 5235053f443cef4210606e5fb71f99b915a9723d)
+Cc: stable@vger.kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index dc8ed896d05f0..69bfaa9a8f90b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -766,6 +766,13 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
++ /* resizing on Dell G5 SE platforms causes problems with runtime pm */
++ if ((amdgpu_runtime_pm != 0) &&
++ adev->pdev->vendor == PCI_VENDOR_ID_ATI &&
++ adev->pdev->device == 0x731f &&
++ adev->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
++ return 0;
++
+ /* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */
+ if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR))
+ DRM_WARN("System can't access extended configuration space,please check!!\n");
+--
+2.39.5
+
--- /dev/null
+From f7a4374c57c2b426cbb08ff68dc8420ad88aaebd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 8 Jun 2020 15:39:33 -0400
+Subject: drm/amdgpu: skip BAR resizing if the bios already did it
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+[ Upstream commit b7221f2b4655bb9a95ed6f86658713c8dd543d41 ]
+
+No need to do it again.
+
+Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Stable-dep-of: 099bffc7cadf ("drm/amdgpu: disable BAR resize on Dell G5 SE")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 9dcb38bab0e10..49fcb69ca4a1b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -766,6 +766,11 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
++ /* skip if the bios has already enabled large BAR */
++ if (adev->gmc.real_vram_size &&
++ (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
++ return 0;
++
+ /* Check if the root BUS has 64bit memory resources */
+ root = adev->pdev->bus;
+ while (root->parent)
+--
+2.39.5
+
--- /dev/null
+From 49c69c4d6853e9d07018a203666e3bf62a00541b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 13 Feb 2025 15:20:55 +0000
+Subject: drop_monitor: fix incorrect initialization order
+
+From: Gavrilov Ilia <Ilia.Gavrilov@infotecs.ru>
+
+[ Upstream commit 07b598c0e6f06a0f254c88dafb4ad50f8a8c6eea ]
+
+Syzkaller reports the following bug:
+
+BUG: spinlock bad magic on CPU#1, syz-executor.0/7995
+ lock: 0xffff88805303f3e0, .magic: 00000000, .owner: <none>/-1, .owner_cpu: 0
+CPU: 1 PID: 7995 Comm: syz-executor.0 Tainted: G E 5.10.209+ #1
+Hardware name: VMware, Inc. VMware Virtual Platform/440BX Desktop Reference Platform, BIOS 6.00 11/12/2020
+Call Trace:
+ __dump_stack lib/dump_stack.c:77 [inline]
+ dump_stack+0x119/0x179 lib/dump_stack.c:118
+ debug_spin_lock_before kernel/locking/spinlock_debug.c:83 [inline]
+ do_raw_spin_lock+0x1f6/0x270 kernel/locking/spinlock_debug.c:112
+ __raw_spin_lock_irqsave include/linux/spinlock_api_smp.h:117 [inline]
+ _raw_spin_lock_irqsave+0x50/0x70 kernel/locking/spinlock.c:159
+ reset_per_cpu_data+0xe6/0x240 [drop_monitor]
+ net_dm_cmd_trace+0x43d/0x17a0 [drop_monitor]
+ genl_family_rcv_msg_doit+0x22f/0x330 net/netlink/genetlink.c:739
+ genl_family_rcv_msg net/netlink/genetlink.c:783 [inline]
+ genl_rcv_msg+0x341/0x5a0 net/netlink/genetlink.c:800
+ netlink_rcv_skb+0x14d/0x440 net/netlink/af_netlink.c:2497
+ genl_rcv+0x29/0x40 net/netlink/genetlink.c:811
+ netlink_unicast_kernel net/netlink/af_netlink.c:1322 [inline]
+ netlink_unicast+0x54b/0x800 net/netlink/af_netlink.c:1348
+ netlink_sendmsg+0x914/0xe00 net/netlink/af_netlink.c:1916
+ sock_sendmsg_nosec net/socket.c:651 [inline]
+ __sock_sendmsg+0x157/0x190 net/socket.c:663
+ ____sys_sendmsg+0x712/0x870 net/socket.c:2378
+ ___sys_sendmsg+0xf8/0x170 net/socket.c:2432
+ __sys_sendmsg+0xea/0x1b0 net/socket.c:2461
+ do_syscall_64+0x30/0x40 arch/x86/entry/common.c:46
+ entry_SYSCALL_64_after_hwframe+0x62/0xc7
+RIP: 0033:0x7f3f9815aee9
+Code: ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 b0 ff ff ff f7 d8 64 89 01 48
+RSP: 002b:00007f3f972bf0c8 EFLAGS: 00000246 ORIG_RAX: 000000000000002e
+RAX: ffffffffffffffda RBX: 00007f3f9826d050 RCX: 00007f3f9815aee9
+RDX: 0000000020000000 RSI: 0000000020001300 RDI: 0000000000000007
+RBP: 00007f3f981b63bd R08: 0000000000000000 R09: 0000000000000000
+R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000
+R13: 000000000000006e R14: 00007f3f9826d050 R15: 00007ffe01ee6768
+
+If drop_monitor is built as a kernel module, syzkaller may have time
+to send a netlink NET_DM_CMD_START message during the module loading.
+This will call the net_dm_monitor_start() function that uses
+a spinlock that has not yet been initialized.
+
+To fix this, let's place resource initialization above the registration
+of a generic netlink family.
+
+Found by InfoTeCS on behalf of Linux Verification Center
+(linuxtesting.org) with Syzkaller.
+
+Fixes: 9a8afc8d3962 ("Network Drop Monitor: Adding drop monitor implementation & Netlink protocol")
+Cc: stable@vger.kernel.org
+Signed-off-by: Ilia Gavrilov <Ilia.Gavrilov@infotecs.ru>
+Reviewed-by: Ido Schimmel <idosch@nvidia.com>
+Link: https://patch.msgid.link/20250213152054.2785669-1-Ilia.Gavrilov@infotecs.ru
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/core/drop_monitor.c | 29 ++++++++++++++---------------
+ 1 file changed, 14 insertions(+), 15 deletions(-)
+
+diff --git a/net/core/drop_monitor.c b/net/core/drop_monitor.c
+index b37465af47e4b..0c8afafcce436 100644
+--- a/net/core/drop_monitor.c
++++ b/net/core/drop_monitor.c
+@@ -1650,30 +1650,30 @@ static int __init init_net_drop_monitor(void)
+ return -ENOSPC;
+ }
+
+- rc = genl_register_family(&net_drop_monitor_family);
+- if (rc) {
+- pr_err("Could not create drop monitor netlink family\n");
+- return rc;
++ for_each_possible_cpu(cpu) {
++ net_dm_cpu_data_init(cpu);
++ net_dm_hw_cpu_data_init(cpu);
+ }
+- WARN_ON(net_drop_monitor_family.mcgrp_offset != NET_DM_GRP_ALERT);
+
+ rc = register_netdevice_notifier(&dropmon_net_notifier);
+ if (rc < 0) {
+ pr_crit("Failed to register netdevice notifier\n");
++ return rc;
++ }
++
++ rc = genl_register_family(&net_drop_monitor_family);
++ if (rc) {
++ pr_err("Could not create drop monitor netlink family\n");
+ goto out_unreg;
+ }
++ WARN_ON(net_drop_monitor_family.mcgrp_offset != NET_DM_GRP_ALERT);
+
+ rc = 0;
+
+- for_each_possible_cpu(cpu) {
+- net_dm_cpu_data_init(cpu);
+- net_dm_hw_cpu_data_init(cpu);
+- }
+-
+ goto out;
+
+ out_unreg:
+- genl_unregister_family(&net_drop_monitor_family);
++ WARN_ON(unregister_netdevice_notifier(&dropmon_net_notifier));
+ out:
+ return rc;
+ }
+@@ -1682,19 +1682,18 @@ static void exit_net_drop_monitor(void)
+ {
+ int cpu;
+
+- BUG_ON(unregister_netdevice_notifier(&dropmon_net_notifier));
+-
+ /*
+ * Because of the module_get/put we do in the trace state change path
+ * we are guarnateed not to have any current users when we get here
+ */
++ BUG_ON(genl_unregister_family(&net_drop_monitor_family));
++
++ BUG_ON(unregister_netdevice_notifier(&dropmon_net_notifier));
+
+ for_each_possible_cpu(cpu) {
+ net_dm_hw_cpu_data_fini(cpu);
+ net_dm_cpu_data_fini(cpu);
+ }
+-
+- BUG_ON(genl_unregister_family(&net_drop_monitor_family));
+ }
+
+ module_init(init_net_drop_monitor);
+--
+2.39.5
+
--- /dev/null
+From 645ae17a4489a28b8b1464207bcfe3e26925a3ed Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 7 Sep 2021 19:58:18 -0700
+Subject: kernel/acct.c: use dedicated helper to access rlimit values
+
+From: Yang Yang <yang.yang29@zte.com.cn>
+
+[ Upstream commit 3c91dda97eea704ac257ddb138d1154adab8db62 ]
+
+Use rlimit() helper instead of manually writing whole chain from
+task to rlimit value. See patch "posix-cpu-timers: Use dedicated
+helper to access rlimit values".
+
+Link: https://lkml.kernel.org/r/20210728030822.524789-1-yang.yang29@zte.com.cn
+Signed-off-by: Yang Yang <yang.yang29@zte.com.cn>
+Reported-by: Zeal Robot <zealci@zte.com.cn>
+Cc: Randy Dunlap <rdunlap@infradead.org>
+Cc: sh_def@163.com <sh_def@163.com>
+Cc: Yang Yang <yang.yang29@zte.com.cn>
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Stable-dep-of: 56d5f3eba3f5 ("acct: perform last write from workqueue")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/acct.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/kernel/acct.c b/kernel/acct.c
+index 79f93a45973fa..cdfe1b0ce0e39 100644
+--- a/kernel/acct.c
++++ b/kernel/acct.c
+@@ -492,7 +492,7 @@ static void do_acct_process(struct bsd_acct_struct *acct)
+ /*
+ * Accounting records are not subject to resource limits.
+ */
+- flim = current->signal->rlim[RLIMIT_FSIZE].rlim_cur;
++ flim = rlimit(RLIMIT_FSIZE);
+ current->signal->rlim[RLIMIT_FSIZE].rlim_cur = RLIM_INFINITY;
+ /* Perform file operations on behalf of whoever enabled accounting */
+ orig_cred = override_creds(file->f_cred);
+--
+2.39.5
+
--- /dev/null
+From 3f80983e62ddaaa0d8aa2188b5a663130c0e10c4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 15 Dec 2020 20:42:52 -0800
+Subject: kernel/acct.c: use #elif instead of #end and #elif
+
+From: Hui Su <sh_def@163.com>
+
+[ Upstream commit 35189b8ff18ee0c6f7c04f4c674584d1149d5c55 ]
+
+Cleanup: use #elif instead of #end and #elif.
+
+Link: https://lkml.kernel.org/r/20201015150736.GA91603@rlk
+Signed-off-by: Hui Su <sh_def@163.com>
+Reviewed-by: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Stable-dep-of: 56d5f3eba3f5 ("acct: perform last write from workqueue")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/acct.c | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+diff --git a/kernel/acct.c b/kernel/acct.c
+index a98ce49d12fa0..79f93a45973fa 100644
+--- a/kernel/acct.c
++++ b/kernel/acct.c
+@@ -397,9 +397,7 @@ static comp2_t encode_comp2_t(u64 value)
+ return (value & (MAXFRACT2>>1)) | (exp << (MANTSIZE2-1));
+ }
+ }
+-#endif
+-
+-#if ACCT_VERSION == 3
++#elif ACCT_VERSION == 3
+ /*
+ * encode an u64 into a 32 bit IEEE float
+ */
+@@ -514,8 +512,7 @@ static void do_acct_process(struct bsd_acct_struct *acct)
+ /* backward-compatible 16 bit fields */
+ ac.ac_uid16 = ac.ac_uid;
+ ac.ac_gid16 = ac.ac_gid;
+-#endif
+-#if ACCT_VERSION == 3
++#elif ACCT_VERSION == 3
+ {
+ struct pid_namespace *ns = acct->ns;
+
+--
+2.39.5
+
--- /dev/null
+From 8b9defccfcd6bc7363f18a104d22c2db65a38d75 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 8 Mar 2023 14:47:34 +0800
+Subject: Revert "riscv: Set more data to cacheinfo"
+
+From: Song Shuai <suagrfillet@gmail.com>
+
+[ Upstream commit 6a24915145c922b79d3ac78f681137a4c14a6d6b ]
+
+This reverts commit baf7cbd94b5688f167443a2cc3dcea3300132099.
+
+There are some duplicate cache attributes populations executed
+in both ci_leaf_init() and later cache_setup_properties().
+
+Revert the commit baf7cbd94b56 ("riscv: Set more data to cacheinfo")
+to setup only the level and type attributes at this early place.
+
+Signed-off-by: Song Shuai <suagrfillet@gmail.com>
+Acked-by: Sudeep Holla <sudeep.holla@arm.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Link: https://lore.kernel.org/r/20230308064734.512457-1-suagrfillet@gmail.com
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/kernel/cacheinfo.c | 66 ++++++++---------------------------
+ 1 file changed, 15 insertions(+), 51 deletions(-)
+
+diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
+index 09892077ae087..31d8f35c4f077 100644
+--- a/arch/riscv/kernel/cacheinfo.c
++++ b/arch/riscv/kernel/cacheinfo.c
+@@ -55,53 +55,12 @@ uintptr_t get_cache_geometry(u32 level, enum cache_type type)
+ 0;
+ }
+
+-static void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type,
+- unsigned int level, unsigned int size,
+- unsigned int sets, unsigned int line_size)
++static void ci_leaf_init(struct cacheinfo *this_leaf,
++ struct device_node *node,
++ enum cache_type type, unsigned int level)
+ {
+ this_leaf->level = level;
+ this_leaf->type = type;
+- this_leaf->size = size;
+- this_leaf->number_of_sets = sets;
+- this_leaf->coherency_line_size = line_size;
+-
+- /*
+- * If the cache is fully associative, there is no need to
+- * check the other properties.
+- */
+- if (sets == 1)
+- return;
+-
+- /*
+- * Set the ways number for n-ways associative, make sure
+- * all properties are big than zero.
+- */
+- if (sets > 0 && size > 0 && line_size > 0)
+- this_leaf->ways_of_associativity = (size / sets) / line_size;
+-}
+-
+-static void fill_cacheinfo(struct cacheinfo **this_leaf,
+- struct device_node *node, unsigned int level)
+-{
+- unsigned int size, sets, line_size;
+-
+- if (!of_property_read_u32(node, "cache-size", &size) &&
+- !of_property_read_u32(node, "cache-block-size", &line_size) &&
+- !of_property_read_u32(node, "cache-sets", &sets)) {
+- ci_leaf_init((*this_leaf)++, CACHE_TYPE_UNIFIED, level, size, sets, line_size);
+- }
+-
+- if (!of_property_read_u32(node, "i-cache-size", &size) &&
+- !of_property_read_u32(node, "i-cache-sets", &sets) &&
+- !of_property_read_u32(node, "i-cache-block-size", &line_size)) {
+- ci_leaf_init((*this_leaf)++, CACHE_TYPE_INST, level, size, sets, line_size);
+- }
+-
+- if (!of_property_read_u32(node, "d-cache-size", &size) &&
+- !of_property_read_u32(node, "d-cache-sets", &sets) &&
+- !of_property_read_u32(node, "d-cache-block-size", &line_size)) {
+- ci_leaf_init((*this_leaf)++, CACHE_TYPE_DATA, level, size, sets, line_size);
+- }
+ }
+
+ int init_cache_level(unsigned int cpu)
+@@ -154,24 +113,29 @@ int populate_cache_leaves(unsigned int cpu)
+ struct device_node *prev = NULL;
+ int levels = 1, level = 1;
+
+- /* Level 1 caches in cpu node */
+- fill_cacheinfo(&this_leaf, np, level);
++ if (of_property_read_bool(np, "cache-size"))
++ ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
++ if (of_property_read_bool(np, "i-cache-size"))
++ ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
++ if (of_property_read_bool(np, "d-cache-size"))
++ ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);
+
+- /* Next level caches in cache nodes */
+ prev = np;
+ while ((np = of_find_next_cache_node(np))) {
+ of_node_put(prev);
+ prev = np;
+-
+ if (!of_device_is_compatible(np, "cache"))
+ break;
+ if (of_property_read_u32(np, "cache-level", &level))
+ break;
+ if (level <= levels)
+ break;
+-
+- fill_cacheinfo(&this_leaf, np, level);
+-
++ if (of_property_read_bool(np, "cache-size"))
++ ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
++ if (of_property_read_bool(np, "i-cache-size"))
++ ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
++ if (of_property_read_bool(np, "d-cache-size"))
++ ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);
+ levels = level;
+ }
+ of_node_put(np);
+--
+2.39.5
+
--- /dev/null
+From 2765d9652afac0a32f530d242038dfcb971dbb99 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 31 Aug 2020 15:33:50 +0800
+Subject: riscv: Add cache information in AUX vector
+
+From: Zong Li <zong.li@sifive.com>
+
+[ Upstream commit 38f5bd23deae24c8fa67a2c574b6d43df27a8aa8 ]
+
+There are no standard CSR registers to provide cache information, the
+way for RISC-V is to get this information from DT. Currently, AT_L1I_X,
+AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall
+could use them to get information of cache through AUX vector.
+
+The result of 'getconf -a' as follows:
+LEVEL1_ICACHE_SIZE 32768
+LEVEL1_ICACHE_ASSOC 8
+LEVEL1_ICACHE_LINESIZE 64
+LEVEL1_DCACHE_SIZE 32768
+LEVEL1_DCACHE_ASSOC 8
+LEVEL1_DCACHE_LINESIZE 64
+LEVEL2_CACHE_SIZE 2097152
+LEVEL2_CACHE_ASSOC 32
+LEVEL2_CACHE_LINESIZE 64
+
+Signed-off-by: Zong Li <zong.li@sifive.com>
+Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
+Reviewed-by: Pekka Enberg <penberg@kernel.org>
+Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
+Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/include/asm/cacheinfo.h | 5 +++++
+ arch/riscv/include/asm/elf.h | 13 +++++++++++
+ arch/riscv/include/uapi/asm/auxvec.h | 23 +++++++++++++++++++-
+ arch/riscv/kernel/cacheinfo.c | 32 +++++++++++++++++++++++++++-
+ 4 files changed, 71 insertions(+), 2 deletions(-)
+
+diff --git a/arch/riscv/include/asm/cacheinfo.h b/arch/riscv/include/asm/cacheinfo.h
+index 5d9662e9aba85..d1a365215ec00 100644
+--- a/arch/riscv/include/asm/cacheinfo.h
++++ b/arch/riscv/include/asm/cacheinfo.h
+@@ -1,4 +1,7 @@
+ /* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (C) 2020 SiFive
++ */
+
+ #ifndef _ASM_RISCV_CACHEINFO_H
+ #define _ASM_RISCV_CACHEINFO_H
+@@ -11,5 +14,7 @@ struct riscv_cacheinfo_ops {
+ };
+
+ void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops);
++uintptr_t get_cache_size(u32 level, enum cache_type type);
++uintptr_t get_cache_geometry(u32 level, enum cache_type type);
+
+ #endif /* _ASM_RISCV_CACHEINFO_H */
+diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
+index ef04084bf0dee..4031cce8dd734 100644
+--- a/arch/riscv/include/asm/elf.h
++++ b/arch/riscv/include/asm/elf.h
+@@ -11,6 +11,7 @@
+ #include <uapi/asm/elf.h>
+ #include <asm/auxvec.h>
+ #include <asm/byteorder.h>
++#include <asm/cacheinfo.h>
+
+ /*
+ * These are used to set parameters in the core dumps.
+@@ -60,6 +61,18 @@ extern unsigned long elf_hwcap;
+ do { \
+ NEW_AUX_ENT(AT_SYSINFO_EHDR, \
+ (elf_addr_t)current->mm->context.vdso); \
++ NEW_AUX_ENT(AT_L1I_CACHESIZE, \
++ get_cache_size(1, CACHE_TYPE_INST)); \
++ NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \
++ get_cache_geometry(1, CACHE_TYPE_INST)); \
++ NEW_AUX_ENT(AT_L1D_CACHESIZE, \
++ get_cache_size(1, CACHE_TYPE_DATA)); \
++ NEW_AUX_ENT(AT_L1D_CACHEGEOMETRY, \
++ get_cache_geometry(1, CACHE_TYPE_DATA)); \
++ NEW_AUX_ENT(AT_L2_CACHESIZE, \
++ get_cache_size(2, CACHE_TYPE_UNIFIED)); \
++ NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \
++ get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \
+ } while (0)
+
+
+diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h
+index 22e0ae8884061..32c73ba1d5313 100644
+--- a/arch/riscv/include/uapi/asm/auxvec.h
++++ b/arch/riscv/include/uapi/asm/auxvec.h
+@@ -10,7 +10,28 @@
+ /* vDSO location */
+ #define AT_SYSINFO_EHDR 33
+
++/*
++ * The set of entries below represent more extensive information
++ * about the caches, in the form of two entry per cache type,
++ * one entry containing the cache size in bytes, and the other
++ * containing the cache line size in bytes in the bottom 16 bits
++ * and the cache associativity in the next 16 bits.
++ *
++ * The associativity is such that if N is the 16-bit value, the
++ * cache is N way set associative. A value if 0xffff means fully
++ * associative, a value of 1 means directly mapped.
++ *
++ * For all these fields, a value of 0 means that the information
++ * is not known.
++ */
++#define AT_L1I_CACHESIZE 40
++#define AT_L1I_CACHEGEOMETRY 41
++#define AT_L1D_CACHESIZE 42
++#define AT_L1D_CACHEGEOMETRY 43
++#define AT_L2_CACHESIZE 44
++#define AT_L2_CACHEGEOMETRY 45
++
+ /* entries in ARCH_DLINFO */
+-#define AT_VECTOR_SIZE_ARCH 1
++#define AT_VECTOR_SIZE_ARCH 7
+
+ #endif /* _UAPI_ASM_RISCV_AUXVEC_H */
+diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
+index 8cd8224f47ee1..09892077ae087 100644
+--- a/arch/riscv/kernel/cacheinfo.c
++++ b/arch/riscv/kernel/cacheinfo.c
+@@ -3,7 +3,6 @@
+ * Copyright (C) 2017 SiFive
+ */
+
+-#include <linux/cacheinfo.h>
+ #include <linux/cpu.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+@@ -25,6 +24,37 @@ cache_get_priv_group(struct cacheinfo *this_leaf)
+ return NULL;
+ }
+
++static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type)
++{
++ struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(smp_processor_id());
++ struct cacheinfo *this_leaf;
++ int index;
++
++ for (index = 0; index < this_cpu_ci->num_leaves; index++) {
++ this_leaf = this_cpu_ci->info_list + index;
++ if (this_leaf->level == level && this_leaf->type == type)
++ return this_leaf;
++ }
++
++ return NULL;
++}
++
++uintptr_t get_cache_size(u32 level, enum cache_type type)
++{
++ struct cacheinfo *this_leaf = get_cacheinfo(level, type);
++
++ return this_leaf ? this_leaf->size : 0;
++}
++
++uintptr_t get_cache_geometry(u32 level, enum cache_type type)
++{
++ struct cacheinfo *this_leaf = get_cacheinfo(level, type);
++
++ return this_leaf ? (this_leaf->ways_of_associativity << 16 |
++ this_leaf->coherency_line_size) :
++ 0;
++}
++
+ static void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type,
+ unsigned int level, unsigned int size,
+ unsigned int sets, unsigned int line_size)
+--
+2.39.5
+
--- /dev/null
+From df149035c335d53ff1d1193c7407784f1cd91a30 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 20 Feb 2020 10:45:18 +0530
+Subject: riscv: cacheinfo: Implement cache_get_priv_group with a generic ops
+ structure
+
+From: Yash Shah <yash.shah@sifive.com>
+
+[ Upstream commit 087958a17658dcd92cdc9292e6ce4319a25198fb ]
+
+Implement cache_get_priv_group() that will make use of a generic ops
+structure to return a private attribute group for custom cache info.
+
+Using riscv_set_cacheinfo_ops() users can hook their own custom function
+to return the private attribute group for cacheinfo. In future we can
+add more ops to this generic ops structure for SOC specific cacheinfo.
+
+Signed-off-by: Yash Shah <yash.shah@sifive.com>
+Reviewed-by: Anup Patel <anup@brainfault.org>
+Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
+Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/include/asm/cacheinfo.h | 15 +++++++++++++++
+ arch/riscv/kernel/cacheinfo.c | 17 +++++++++++++++++
+ 2 files changed, 32 insertions(+)
+ create mode 100644 arch/riscv/include/asm/cacheinfo.h
+
+diff --git a/arch/riscv/include/asm/cacheinfo.h b/arch/riscv/include/asm/cacheinfo.h
+new file mode 100644
+index 0000000000000..5d9662e9aba85
+--- /dev/null
++++ b/arch/riscv/include/asm/cacheinfo.h
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#ifndef _ASM_RISCV_CACHEINFO_H
++#define _ASM_RISCV_CACHEINFO_H
++
++#include <linux/cacheinfo.h>
++
++struct riscv_cacheinfo_ops {
++ const struct attribute_group * (*get_priv_group)(struct cacheinfo
++ *this_leaf);
++};
++
++void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops);
++
++#endif /* _ASM_RISCV_CACHEINFO_H */
+diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
+index d930bd073b7b2..21dadeba06753 100644
+--- a/arch/riscv/kernel/cacheinfo.c
++++ b/arch/riscv/kernel/cacheinfo.c
+@@ -7,6 +7,23 @@
+ #include <linux/cpu.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
++#include <asm/cacheinfo.h>
++
++static struct riscv_cacheinfo_ops *rv_cache_ops;
++
++void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops)
++{
++ rv_cache_ops = ops;
++}
++EXPORT_SYMBOL_GPL(riscv_set_cacheinfo_ops);
++
++const struct attribute_group *
++cache_get_priv_group(struct cacheinfo *this_leaf)
++{
++ if (rv_cache_ops && rv_cache_ops->get_priv_group)
++ return rv_cache_ops->get_priv_group(this_leaf);
++ return NULL;
++}
+
+ static void ci_leaf_init(struct cacheinfo *this_leaf,
+ struct device_node *node,
+--
+2.39.5
+
--- /dev/null
+From c99eb453dd4dc4b7f1f1976bcaac31b1e48cf91e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Jun 2024 21:14:24 +0800
+Subject: riscv: cacheinfo: initialize cacheinfo's level and type from ACPI
+ PPTT
+
+From: Yunhui Cui <cuiyunhui@bytedance.com>
+
+[ Upstream commit 604f32ea6909b0ebb8ab0bf1ab7dc66ee3dc8955 ]
+
+Before cacheinfo can be built correctly, we need to initialize level
+and type. Since RISC-V currently does not have a register group that
+describes cache-related attributes like ARM64, we cannot obtain them
+directly, so now we obtain cache leaves from the ACPI PPTT table
+(acpi_get_cache_info()) and set the cache type through split_levels.
+
+Suggested-by: Jeremy Linton <jeremy.linton@arm.com>
+Suggested-by: Sudeep Holla <sudeep.holla@arm.com>
+Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
+Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
+Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
+Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
+Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
+Link: https://lore.kernel.org/r/20240617131425.7526-2-cuiyunhui@bytedance.com
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
+index 1d173fdbf4632..4464174836efc 100644
+--- a/arch/riscv/kernel/cacheinfo.c
++++ b/arch/riscv/kernel/cacheinfo.c
+@@ -3,6 +3,7 @@
+ * Copyright (C) 2017 SiFive
+ */
+
++#include <linux/acpi.h>
+ #include <linux/cpu.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+@@ -112,6 +113,27 @@ int populate_cache_leaves(unsigned int cpu)
+ struct device_node *prev = NULL;
+ int levels = 1, level = 1;
+
++ if (!acpi_disabled) {
++ int ret, fw_levels, split_levels;
++
++ ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
++ if (ret)
++ return ret;
++
++ BUG_ON((split_levels > fw_levels) ||
++ (split_levels + fw_levels > this_cpu_ci->num_leaves));
++
++ for (; level <= this_cpu_ci->num_levels; level++) {
++ if (level <= split_levels) {
++ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
++ } else {
++ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
++ }
++ }
++ return 0;
++ }
++
+ if (of_property_read_bool(np, "cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+ if (of_property_read_bool(np, "i-cache-size"))
+--
+2.39.5
+
--- /dev/null
+From 55bab6338ee414d53bfca90435a21a67630c0828 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Jun 2024 21:14:23 +0800
+Subject: riscv: cacheinfo: remove the useless input parameter (node) of
+ ci_leaf_init()
+
+From: Yunhui Cui <cuiyunhui@bytedance.com>
+
+[ Upstream commit ee3fab10cb1566562aa683f319066eaeecccf918 ]
+
+ci_leaf_init() is a declared static function. The implementation of the
+function body and the caller do not use the parameter (struct device_node
+*node) input parameter, so remove it.
+
+Fixes: 6a24915145c9 ("Revert "riscv: Set more data to cacheinfo"")
+Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
+Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
+Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
+Link: https://lore.kernel.org/r/20240617131425.7526-1-cuiyunhui@bytedance.com
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/kernel/cacheinfo.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
+index 31d8f35c4f077..1d173fdbf4632 100644
+--- a/arch/riscv/kernel/cacheinfo.c
++++ b/arch/riscv/kernel/cacheinfo.c
+@@ -56,7 +56,6 @@ uintptr_t get_cache_geometry(u32 level, enum cache_type type)
+ }
+
+ static void ci_leaf_init(struct cacheinfo *this_leaf,
+- struct device_node *node,
+ enum cache_type type, unsigned int level)
+ {
+ this_leaf->level = level;
+@@ -114,11 +113,11 @@ int populate_cache_leaves(unsigned int cpu)
+ int levels = 1, level = 1;
+
+ if (of_property_read_bool(np, "cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+ if (of_property_read_bool(np, "i-cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
+ if (of_property_read_bool(np, "d-cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
+
+ prev = np;
+ while ((np = of_find_next_cache_node(np))) {
+@@ -131,11 +130,11 @@ int populate_cache_leaves(unsigned int cpu)
+ if (level <= levels)
+ break;
+ if (of_property_read_bool(np, "cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+ if (of_property_read_bool(np, "i-cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
+ if (of_property_read_bool(np, "d-cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
+ levels = level;
+ }
+ of_node_put(np);
+--
+2.39.5
+
--- /dev/null
+From db056268c2d9008c0934fa6b3cb57d4cfcd6b320 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 4 Nov 2024 13:03:13 -0600
+Subject: riscv: cacheinfo: Use of_property_present() for non-boolean
+ properties
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Rob Herring <robh@kernel.org>
+
+[ Upstream commit fb8179ce2996bffaa36a04e2b6262843b01b7565 ]
+
+The use of of_property_read_bool() for non-boolean properties is
+deprecated in favor of of_property_present() when testing for property
+presence.
+
+Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
+Reviewed-by: Clément Léger <cleger@rivosinc.com>
+Cc: stable@vger.kernel.org
+Fixes: 76d2a0493a17 ("RISC-V: Init and Halt Code")
+Link: https://lore.kernel.org/r/20241104190314.270095-1-robh@kernel.org
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/kernel/cacheinfo.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
+index 69897100e4263..86efb7e62c552 100644
+--- a/arch/riscv/kernel/cacheinfo.c
++++ b/arch/riscv/kernel/cacheinfo.c
+@@ -137,11 +137,11 @@ int populate_cache_leaves(unsigned int cpu)
+ if (!np)
+ return -ENOENT;
+
+- if (of_property_read_bool(np, "cache-size"))
++ if (of_property_present(np, "cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+- if (of_property_read_bool(np, "i-cache-size"))
++ if (of_property_present(np, "i-cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
+- if (of_property_read_bool(np, "d-cache-size"))
++ if (of_property_present(np, "d-cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
+
+ prev = np;
+@@ -154,11 +154,11 @@ int populate_cache_leaves(unsigned int cpu)
+ break;
+ if (level <= levels)
+ break;
+- if (of_property_read_bool(np, "cache-size"))
++ if (of_property_present(np, "cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+- if (of_property_read_bool(np, "i-cache-size"))
++ if (of_property_present(np, "i-cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
+- if (of_property_read_bool(np, "d-cache-size"))
++ if (of_property_present(np, "d-cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
+ levels = level;
+ }
+--
+2.39.5
+
--- /dev/null
+From ce8f9224c6726c4f14bb17a7803521c08fd0b92b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 13 Sep 2024 10:00:52 +0200
+Subject: riscv: Prevent a bad reference count on CPU nodes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Miquel Sabaté Solà <mikisabate@gmail.com>
+
+[ Upstream commit 37233169a6ea912020c572f870075a63293b786a ]
+
+When populating cache leaves we previously fetched the CPU device node
+at the very beginning. But when ACPI is enabled we go through a
+specific branch which returns early and does not call 'of_node_put' for
+the node that was acquired.
+
+Since we are not using a CPU device node for the ACPI code anyways, we
+can simply move the initialization of it just passed the ACPI block, and
+we are guaranteed to have an 'of_node_put' call for the acquired node.
+This prevents a bad reference count of the CPU device node.
+
+Moreover, the previous function did not check for errors when acquiring
+the device node, so a return -ENOENT has been added for that case.
+
+Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
+Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
+Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
+Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
+Fixes: 604f32ea6909 ("riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT")
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/r/20240913080053.36636-1-mikisabate@gmail.com
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/kernel/cacheinfo.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
+index 4464174836efc..69897100e4263 100644
+--- a/arch/riscv/kernel/cacheinfo.c
++++ b/arch/riscv/kernel/cacheinfo.c
+@@ -109,8 +109,7 @@ int populate_cache_leaves(unsigned int cpu)
+ {
+ struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+ struct cacheinfo *this_leaf = this_cpu_ci->info_list;
+- struct device_node *np = of_cpu_device_node_get(cpu);
+- struct device_node *prev = NULL;
++ struct device_node *np, *prev;
+ int levels = 1, level = 1;
+
+ if (!acpi_disabled) {
+@@ -134,6 +133,10 @@ int populate_cache_leaves(unsigned int cpu)
+ return 0;
+ }
+
++ np = of_cpu_device_node_get(cpu);
++ if (!np)
++ return -ENOENT;
++
+ if (of_property_read_bool(np, "cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+ if (of_property_read_bool(np, "i-cache-size"))
+--
+2.39.5
+
--- /dev/null
+From fb166e44b79839e51320a1a11396e73de92da357 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 31 Aug 2020 15:33:48 +0800
+Subject: riscv: Set more data to cacheinfo
+
+From: Zong Li <zong.li@sifive.com>
+
+[ Upstream commit baf7cbd94b5688f167443a2cc3dcea3300132099 ]
+
+Set cacheinfo.{size,sets,line_size} for each cache node, then we can
+get these information from userland through auxiliary vector.
+
+Signed-off-by: Zong Li <zong.li@sifive.com>
+Reviewed-by: Pekka Enberg <penberg@kernel.org>
+Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
+Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/kernel/cacheinfo.c | 66 +++++++++++++++++++++++++++--------
+ 1 file changed, 51 insertions(+), 15 deletions(-)
+
+diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
+index 21dadeba06753..8cd8224f47ee1 100644
+--- a/arch/riscv/kernel/cacheinfo.c
++++ b/arch/riscv/kernel/cacheinfo.c
+@@ -25,12 +25,53 @@ cache_get_priv_group(struct cacheinfo *this_leaf)
+ return NULL;
+ }
+
+-static void ci_leaf_init(struct cacheinfo *this_leaf,
+- struct device_node *node,
+- enum cache_type type, unsigned int level)
++static void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type,
++ unsigned int level, unsigned int size,
++ unsigned int sets, unsigned int line_size)
+ {
+ this_leaf->level = level;
+ this_leaf->type = type;
++ this_leaf->size = size;
++ this_leaf->number_of_sets = sets;
++ this_leaf->coherency_line_size = line_size;
++
++ /*
++ * If the cache is fully associative, there is no need to
++ * check the other properties.
++ */
++ if (sets == 1)
++ return;
++
++ /*
++ * Set the ways number for n-ways associative, make sure
++ * all properties are big than zero.
++ */
++ if (sets > 0 && size > 0 && line_size > 0)
++ this_leaf->ways_of_associativity = (size / sets) / line_size;
++}
++
++static void fill_cacheinfo(struct cacheinfo **this_leaf,
++ struct device_node *node, unsigned int level)
++{
++ unsigned int size, sets, line_size;
++
++ if (!of_property_read_u32(node, "cache-size", &size) &&
++ !of_property_read_u32(node, "cache-block-size", &line_size) &&
++ !of_property_read_u32(node, "cache-sets", &sets)) {
++ ci_leaf_init((*this_leaf)++, CACHE_TYPE_UNIFIED, level, size, sets, line_size);
++ }
++
++ if (!of_property_read_u32(node, "i-cache-size", &size) &&
++ !of_property_read_u32(node, "i-cache-sets", &sets) &&
++ !of_property_read_u32(node, "i-cache-block-size", &line_size)) {
++ ci_leaf_init((*this_leaf)++, CACHE_TYPE_INST, level, size, sets, line_size);
++ }
++
++ if (!of_property_read_u32(node, "d-cache-size", &size) &&
++ !of_property_read_u32(node, "d-cache-sets", &sets) &&
++ !of_property_read_u32(node, "d-cache-block-size", &line_size)) {
++ ci_leaf_init((*this_leaf)++, CACHE_TYPE_DATA, level, size, sets, line_size);
++ }
+ }
+
+ int init_cache_level(unsigned int cpu)
+@@ -83,29 +124,24 @@ int populate_cache_leaves(unsigned int cpu)
+ struct device_node *prev = NULL;
+ int levels = 1, level = 1;
+
+- if (of_property_read_bool(np, "cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
+- if (of_property_read_bool(np, "i-cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
+- if (of_property_read_bool(np, "d-cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);
++ /* Level 1 caches in cpu node */
++ fill_cacheinfo(&this_leaf, np, level);
+
++ /* Next level caches in cache nodes */
+ prev = np;
+ while ((np = of_find_next_cache_node(np))) {
+ of_node_put(prev);
+ prev = np;
++
+ if (!of_device_is_compatible(np, "cache"))
+ break;
+ if (of_property_read_u32(np, "cache-level", &level))
+ break;
+ if (level <= levels)
+ break;
+- if (of_property_read_bool(np, "cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
+- if (of_property_read_bool(np, "i-cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
+- if (of_property_read_bool(np, "d-cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);
++
++ fill_cacheinfo(&this_leaf, np, level);
++
+ levels = level;
+ }
+ of_node_put(np);
+--
+2.39.5
+
phy-exynos5-usbdrd-fix-mpll_multiplier-and-ssc_refclksel-masks-in-refclk.patch
sched-core-prevent-rescheduling-when-interrupts-are-disabled.patch
pfifo_tail_enqueue-drop-new-packet-when-sch-limit-0.patch
+drop_monitor-fix-incorrect-initialization-order.patch
+kernel-acct.c-use-elif-instead-of-end-and-elif.patch
+kernel-acct.c-use-dedicated-helper-to-access-rlimit-.patch
+acct-perform-last-write-from-workqueue.patch
+drm-amdgpu-skip-bar-resizing-if-the-bios-already-did.patch
+drm-amdgpu-check-extended-configuration-space-regist.patch
+drm-amdgpu-disable-bar-resize-on-dell-g5-se.patch
+riscv-cacheinfo-implement-cache_get_priv_group-with-.patch
+riscv-set-more-data-to-cacheinfo.patch
+riscv-add-cache-information-in-aux-vector.patch
+revert-riscv-set-more-data-to-cacheinfo.patch
+riscv-cacheinfo-remove-the-useless-input-parameter-n.patch
+riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch
+riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch
+riscv-cacheinfo-use-of_property_present-for-non-bool.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
