x86/msr: Replace wrmsr(msr, low, 0) with wrmsrq(msr, low)

The third argument in wrmsr(msr, low, 0) is unnecessary.  Instead, use
wrmsrq(msr, low), which automatically sets the higher 32 bits of the
MSR value to 0.

Signed-off-by: Xin Li (Intel) <xin@zytor.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Sean Christopherson <seanjc@google.com>
Cc: Stefano Stabellini <sstabellini@kernel.org>
Cc: Uros Bizjak <ubizjak@gmail.com>
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>
Link: https://lore.kernel.org/r/20250427092027.1598740-15-xin@zytor.com

diff --git a/arch/x86/hyperv/hv_apic.c b/arch/x86/hyperv/hv_apic.c
index a079a14270913f31ec53440bd9b11ecef316e9ed..bfde0a3498b900f14b063d09ffd66925ccbfe743 100644 (file)
--- a/arch/x86/hyperv/hv_apic.c
+++ b/arch/x86/hyperv/hv_apic.c
@@ -76,10 +76,10 @@ static void hv_apic_write(u32 reg, u32 val)
 {
        switch (reg) {
        case APIC_EOI:
-               wrmsr(HV_X64_MSR_EOI, val, 0);
+               wrmsrq(HV_X64_MSR_EOI, val);
                break;
        case APIC_TASKPRI:
-               wrmsr(HV_X64_MSR_TPR, val, 0);
+               wrmsrq(HV_X64_MSR_TPR, val);
                break;
        default:
                native_apic_mem_write(reg, val);
@@ -93,7 +93,7 @@ static void hv_apic_eoi_write(void)
        if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1))
                return;
 
-       wrmsr(HV_X64_MSR_EOI, APIC_EOI_ACK, 0);
+       wrmsrq(HV_X64_MSR_EOI, APIC_EOI_ACK);
 }
 
 static bool cpu_is_self(int cpu)

diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 0174dd5483275d3127f86a50e0766eab9d730468..68e10e30fe9baafb5f2fb4f87c78c8f1c2439a8f 100644 (file)
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -209,7 +209,7 @@ static inline void native_apic_msr_write(u32 reg, u32 v)
            reg == APIC_LVR)
                return;
 
-       wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
+       wrmsrq(APIC_BASE_MSR + (reg >> 4), v);
 }
 
 static inline void native_apic_msr_eoi(void)

diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_to.h
index 4f21df7af71501e68abcc507cc7ad84561b7776a..499b1c15cc8b57f0152c645d6617fe6e497d348b 100644 (file)
--- a/arch/x86/include/asm/switch_to.h
+++ b/arch/x86/include/asm/switch_to.h
@@ -61,7 +61,7 @@ static inline void refresh_sysenter_cs(struct thread_struct *thread)
                return;
 
        this_cpu_write(cpu_tss_rw.x86_tss.ss1, thread->sysenter_cs);
-       wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
+       wrmsrq(MSR_IA32_SYSENTER_CS, thread->sysenter_cs);
 }
 #endif
 

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index e153cd1d36fe7d12492245af359f4bcbcec672f0..d8365c4d9057a1c448c9e2a705de6c9c312dcd6d 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1207,7 +1207,7 @@ void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr)
        if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask)
                return;
 
-       wrmsr(amd_msr_dr_addr_masks[dr], mask, 0);
+       wrmsrq(amd_msr_dr_addr_masks[dr], mask);
        per_cpu(amd_dr_addr_mask, cpu)[dr] = mask;
 }
 

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index cefc99990bde2207d1d7db15ed8d195f2500295c..ef9751d577c35282df852898402f67d26a26049e 100644 (file)
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1982,9 +1982,9 @@ void enable_sep_cpu(void)
         */
 
        tss->x86_tss.ss1 = __KERNEL_CS;
-       wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
-       wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
-       wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
+       wrmsrq(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1);
+       wrmsrq(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1));
+       wrmsrq(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32);
 
        put_cpu();
 }
@@ -2198,7 +2198,7 @@ static inline void setup_getcpu(int cpu)
        struct desc_struct d = { };
 
        if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))
-               wrmsr(MSR_TSC_AUX, cpudata, 0);
+               wrmsrq(MSR_TSC_AUX, cpudata);
 
        /* Store CPU and node number in limit. */
        d.limit0 = cpudata;

diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
index 324bd4919300cc606b149f35c253acbf8e5657c9..1190c48a16b2cda023b1c30677c1590397f990ed 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
@@ -905,7 +905,7 @@ int resctrl_arch_measure_cycles_lat_fn(void *_plr)
         * Disable hardware prefetchers.
         */
        rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
-       wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0);
+       wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits);
        mem_r = READ_ONCE(plr->kmem);
        /*
         * Dummy execute of the time measurement to load the needed
@@ -1001,7 +1001,7 @@ static int measure_residency_fn(struct perf_event_attr *miss_attr,
         * Disable hardware prefetchers.
         */
        rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high);
-       wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0);
+       wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits);
 
        /* Initialize rest of local variables */
        /*

diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
index f724b8f6a6a41a79d08296e7a21313fbbc8ab9d2..c85ace29ea3aff0793a9bf2cec78577e8d1a5442 100644 (file)
--- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c
+++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c
@@ -1708,7 +1708,7 @@ void resctrl_arch_mon_event_config_write(void *_config_info)
                pr_warn_once("Invalid event id %d\n", config_info->evtid);
                return;
        }
-       wrmsr(MSR_IA32_EVT_CFG_BASE + index, config_info->mon_config, 0);
+       wrmsrq(MSR_IA32_EVT_CFG_BASE + index, config_info->mon_config);
 }
 
 static void mbm_config_write_domain(struct rdt_resource *r,

diff --git a/arch/x86/kernel/cpu/umwait.c b/arch/x86/kernel/cpu/umwait.c
index 0050eae153bbbba51144408ef330c9712becf688..933fcd7ff2502bdb2556ff3c3da85c6904eacdaf 100644 (file)
--- a/arch/x86/kernel/cpu/umwait.c
+++ b/arch/x86/kernel/cpu/umwait.c
@@ -33,7 +33,7 @@ static DEFINE_MUTEX(umwait_lock);
 static void umwait_update_control_msr(void * unused)
 {
        lockdep_assert_irqs_disabled();
-       wrmsr(MSR_IA32_UMWAIT_CONTROL, READ_ONCE(umwait_control_cached), 0);
+       wrmsrq(MSR_IA32_UMWAIT_CONTROL, READ_ONCE(umwait_control_cached));
 }
 
 /*
@@ -71,7 +71,7 @@ static int umwait_cpu_offline(unsigned int cpu)
         * the original control MSR value in umwait_init(). So there
         * is no race condition here.
         */
-       wrmsr(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached, 0);
+       wrmsrq(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached);
 
        return 0;
 }

diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index 27f7192e1c6193a634b03cfc6e895a43c7241c33..f3642226e0a558e14ec11cad190ba7fbca39d583 100644 (file)
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -400,7 +400,7 @@ static void kvm_disable_steal_time(void)
        if (!has_steal_clock)
                return;
 
-       wrmsr(MSR_KVM_STEAL_TIME, 0, 0);
+       wrmsrq(MSR_KVM_STEAL_TIME, 0);
 }
 
 static u64 kvm_steal_clock(int cpu)