]> git.ipfire.org Git - thirdparty/openwrt.git/commitdiff
realtek: Work around missing 10g-qxgmii PHY mode
authorSven Eckelmann <se@simonwunderlich.de>
Tue, 30 Sep 2025 07:06:57 +0000 (09:06 +0200)
committerRobert Marko <robimarko@gmail.com>
Tue, 30 Sep 2025 18:12:27 +0000 (20:12 +0200)
The current SerDes implementation for RTL931x handles 10G-QXGMII via the
"usxgmii" PHY mode. This is not 100% correct because it is not a single
port with 10G (max) but 4 ports with 2.5G each.

To allow setting of the "10g-qxgmii" phy mode, just change the code for now
to use the same codepaths as USXGMII. This has to be cleaned up further
during the SerDes driver rewrites.

Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20239
Signed-off-by: Robert Marko <robimarko@gmail.com>
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c
target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c

index c805d954ec9e07d3be0b19fc01afa790ca0a96f6..a7f7e43d0e76c0a9a9833569c09826f127a8f711 100644 (file)
@@ -359,6 +359,12 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
 
                if (of_get_phy_mode(dn, &interface))
                        interface = PHY_INTERFACE_MODE_NA;
+
+               if (interface == PHY_INTERFACE_MODE_10G_QXGMII) {
+                       interface = PHY_INTERFACE_MODE_USXGMII;
+                       dev_warn(priv->dev, "handle mode 10g-qsxgmii internally as usxgmii for now\n");
+               }
+
                if (interface == PHY_INTERFACE_MODE_USXGMII)
                        priv->ports[pn].is2G5 = priv->ports[pn].is10G = true;
                if (interface == PHY_INTERFACE_MODE_10GBASER)
index 0f55bf51f48fddcdba1a4d14658dc4470978aaf8..ea28055c401f25439348a6bc47c97525d37d7531 100644 (file)
@@ -1562,6 +1562,11 @@ static int rtmdio_probe(struct platform_device *pdev)
                        priv->interfaces[pn] = PHY_INTERFACE_MODE_NA;
                dev_dbg(dev, "phy mode of port %d is %s\n", pn, phy_modes(priv->interfaces[pn]));
 
+               if (priv->interfaces[pn] == PHY_INTERFACE_MODE_10G_QXGMII) {
+                       priv->interfaces[pn] = PHY_INTERFACE_MODE_USXGMII;
+                       dev_warn(dev, "handle mode 10g-qsxgmii internally as usxgmii for now\n");
+               }
+
                /*
                 * TODO: The MDIO driver does not need any info about the SerDes. As long as
                 * the PCS driver cannot completely control the SerDes, look up the information