endif
PHONY += dtbs
-dtbs dts/dt.dtb: checkdtc u-boot
+dtbs: dts/dt.dtb
+ @:
+dts/dt.dtb: checkdtc u-boot
$(Q)$(MAKE) $(build)=dts dtbs
quiet_cmd_copy = COPY $@
define filechk_version.h
(echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \
echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \
- echo \#define CC_VERSION_STRING \"$$($(CC) --version | head -n 1)\"; \
- echo \#define LD_VERSION_STRING \"$$($(LD) --version | head -n 1)\"; )
+ echo \#define CC_VERSION_STRING \"$$(LC_ALL=C $(CC) --version | head -n 1)\"; \
+ echo \#define LD_VERSION_STRING \"$$(LC_ALL=C $(LD) --version | head -n 1)\"; )
endef
# The SOURCE_DATE_EPOCH mechanism requires a date that behaves like GNU date.
bool "Support vexpress_ca9x4"
select CPU_V7
-config TARGET_KWB
- bool "Support kwb"
+config TARGET_BRXRE1
+ bool "Support BRXRE1"
select CPU_V7
select SUPPORT_SPL
-config TARGET_TSERIES
- bool "Support tseries"
+config TARGET_BRPPT1
+ bool "Support BRPPT1"
select CPU_V7
select SUPPORT_SPL
source "arch/arm/imx-common/Kconfig"
source "board/bosch/shc/Kconfig"
-source "board/BuR/kwb/Kconfig"
-source "board/BuR/tseries/Kconfig"
+source "board/BuR/brxre1/Kconfig"
+source "board/BuR/brppt1/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/gplugd/Kconfig"
}
#ifdef CONFIG_SPL_BUILD
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
endif
endif
-ifneq ($(CONFIG_ARMV7_NONSEC),)
-obj-y += nonsec_virt.o
-obj-y += virt-v7.o
-obj-y += virt-dt.o
-endif
-
-ifneq ($(CONFIG_ARMV7_PSCI),)
-obj-y += psci.o
-endif
+obj-$(CONFIG_ARMV7_NONSEC) += nonsec_virt.o virt-v7.o virt-dt.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
obj-$(CONFIG_IPROC) += iproc-common/
obj-$(CONFIG_KONA) += kona-common/
.ops = &ccu_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
- .num_policy_masks = 2,
+ .num_policy_masks = 1,
.policy_freq_offset = 0x00000008,
.freq_bit_shift = 8,
.policy_ctl_offset = 0x0000000c,
.policy1_mask_offset = 0x00000014,
.policy2_mask_offset = 0x00000018,
.policy3_mask_offset = 0x0000001c,
- .policy0_mask2_offset = 0x00000048,
- .policy1_mask2_offset = 0x0000004c,
- .policy2_mask2_offset = 0x00000050,
- .policy3_mask2_offset = 0x00000054,
.lvm_en_offset = 0x00000034,
.freq_id = 2,
.freq_tbl = slave_axi_freq_tbl,
if (ret)
return ret;
- if (!c->use_cnt) {
- c->use_cnt++;
+ if (!c->use_cnt)
ret = c->ops->enable(c, 1);
- }
+ c->use_cnt++;
return ret;
}
if (!c->ops || !c->ops->enable)
return;
- if (c->use_cnt) {
+ if (c->use_cnt > 0) {
c->use_cnt--;
- c->ops->enable(c, 0);
+ if (c->use_cnt == 0)
+ c->ops->enable(c, 0);
}
/* disable parent */
return BOOT_DEVICE_NAND;
}
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
return gd->arch.omap_boot_device;
}
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
return gd->arch.omap_boot_mode;
}
/* move stamp fordward with absoulte diff ticks */
gd->arch.tbl += (now - gd->arch.lastinc);
} else { /* we have rollover of incrementer */
- gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK /
+ gd->arch.tbl += ((TIMER_OVERFLOW_VAL / (TIMER_CLOCK /
CONFIG_SYS_HZ)) - gd->arch.lastinc) + now;
}
gd->arch.lastinc = now;
return 0;
}
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
WEAK(smp_kick_all_cpus)
/* Kick secondary cpus up by SGI 0 interrupt */
- mov x29, lr /* Save LR */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
ldr x0, =GICD_BASE
- bl gic_kick_secondary_cpus
+ b gic_kick_secondary_cpus
#endif
- mov lr, x29 /* Restore LR */
ret
ENDPROC(smp_kick_all_cpus)
return 0;
}
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
switch (spl_boot_device()) {
case BOOT_DEVICE_RAM:
# SPDX-License-Identifier: GPL-2.0+
#
-dtb-$(CONFIG_AT91FAMILY) += at91sam9g45-gurnard.dtb
+dtb-$(CONFIG_AT91FAMILY) += at91sam9260-smartweb.dtb \
+ at91sam9g20-taurus.dtb \
+ at91sam9g45-corvus.dtb \
+ at91sam9g45-gurnard.dtb
+
dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
--- /dev/null
+/*
+ * at91sam9260-smartweb.dts
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+#include "at91sam9260.dtsi"
+
+/ {
+ model = "Siemens smartweb";
+ compatible = "atmel,at91sam9260", "atmel,at91sam9";
+
+ chosen {
+ stdout-path = &dbgu;
+ };
+
+ memory {
+ reg = <0x20000000 0x4000000>;
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <18432000>;
+ };
+ };
+
+ ahb {
+ apb {
+ pinctrl@fffff400 {
+ board {
+ pinctrl_pck0_as_mck: pck0_as_mck {
+ atmel,pins =
+ <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */
+ };
+
+ };
+ };
+
+ dbgu: serial@fffff200 {
+ status = "okay";
+ };
+
+ usart0: serial@fffb0000 {
+ pinctrl-0 =
+ <&pinctrl_usart0
+ &pinctrl_usart0_rts
+ &pinctrl_usart0_cts
+ &pinctrl_usart0_dtr_dsr
+ &pinctrl_usart0_dcd
+ &pinctrl_usart0_ri>;
+ status = "okay";
+ };
+
+ usart1: serial@fffb4000 {
+ status = "okay";
+ };
+
+ macb0: ethernet@fffc4000 {
+ phy-mode = "rmii";
+ status = "okay";
+ };
+
+ usb1: gadget@fffa4000 {
+ atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ ssc0: ssc@fffbc000 {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_ssc0_tx>;
+ };
+
+ rtc@fffffd20 {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+ status = "okay";
+ };
+
+ watchdog@fffffd40 {
+ status = "okay";
+ };
+
+ gpbr: syscon@fffffd50 {
+ status = "okay";
+ };
+ };
+
+ nand0: nand@40000000 {
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ status = "okay";
+ };
+
+ usb0: ohci@00500000 {
+ num-ports = <2>;
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+/*
+ * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
+ *
+ * Copyright (C) 2011 Atmel,
+ * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
+ * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+
+/ {
+ model = "Atmel AT91SAM9260 family SoC";
+ compatible = "atmel,at91sam9260";
+ interrupt-parent = <&aic>;
+
+ aliases {
+ serial0 = &dbgu;
+ serial1 = &usart0;
+ serial2 = &usart1;
+ serial3 = &usart2;
+ serial4 = &usart3;
+ serial5 = &uart0;
+ serial6 = &uart1;
+ gpio0 = &pioA;
+ gpio1 = &pioB;
+ gpio2 = &pioC;
+ tcb0 = &tcb0;
+ tcb1 = &tcb1;
+ i2c0 = &i2c0;
+ ssc0 = &ssc0;
+ };
+ cpus {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
+ };
+
+ memory {
+ reg = <0x20000000 0x04000000>;
+ };
+
+ clocks {
+ slow_xtal: slow_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ main_xtal: main_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ adc_op_clk: adc_op_clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5000000>;
+ };
+ };
+
+ sram0: sram@002ff000 {
+ compatible = "mmio-sram";
+ reg = <0x002ff000 0x2000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ aic: interrupt-controller@fffff000 {
+ #interrupt-cells = <3>;
+ compatible = "atmel,at91rm9200-aic";
+ interrupt-controller;
+ reg = <0xfffff000 0x200>;
+ atmel,external-irqs = <29 30 31>;
+ };
+
+ ramc0: ramc@ffffea00 {
+ compatible = "atmel,at91sam9260-sdramc";
+ reg = <0xffffea00 0x200>;
+ };
+
+ pmc: pmc@fffffc00 {
+ compatible = "atmel,at91sam9260-pmc", "syscon";
+ reg = <0xfffffc00 0x100>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ main_osc: main_osc {
+ compatible = "atmel,at91rm9200-clk-main-osc";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+ clocks = <&main_xtal>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main";
+ #clock-cells = <0>;
+ clocks = <&main_osc>;
+ };
+
+ slow_rc_osc: slow_rc_osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-accuracy = <50000000>;
+ };
+
+ clk32k: slck {
+ compatible = "atmel,at91sam9260-clk-slow";
+ #clock-cells = <0>;
+ clocks = <&slow_rc_osc>, <&slow_xtal>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+ clocks = <&main>;
+ reg = <0>;
+ atmel,clk-input-range = <1000000 32000000>;
+ #atmel,pll-clk-output-range-cells = <4>;
+ atmel,pll-clk-output-ranges = <80000000 160000000 0 1>,
+ <150000000 240000000 2 1>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_LOCKB>;
+ clocks = <&main>;
+ reg = <1>;
+ atmel,clk-input-range = <1000000 5000000>;
+ #atmel,pll-clk-output-range-cells = <4>;
+ atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+ atmel,clk-output-range = <0 105000000>;
+ atmel,clk-divisors = <1 2 4 0>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ atmel,clk-divisors = <1 2 4 0>;
+ clocks = <&pllb>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&pmc>;
+ clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+
+ prog0: prog0 {
+ #clock-cells = <0>;
+ reg = <0>;
+ interrupts = <AT91_PMC_PCKRDY(0)>;
+ };
+
+ prog1: prog1 {
+ #clock-cells = <0>;
+ reg = <1>;
+ interrupts = <AT91_PMC_PCKRDY(1)>;
+ };
+ };
+
+ systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ uhpck: uhpck {
+ #clock-cells = <0>;
+ reg = <6>;
+ clocks = <&usb>;
+ };
+
+ udpck: udpck {
+ #clock-cells = <0>;
+ reg = <7>;
+ clocks = <&usb>;
+ };
+
+ pck0: pck0 {
+ #clock-cells = <0>;
+ reg = <8>;
+ clocks = <&prog0>;
+ };
+
+ pck1: pck1 {
+ #clock-cells = <0>;
+ reg = <9>;
+ clocks = <&prog1>;
+ };
+ };
+
+ periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mck>;
+
+ pioA_clk: pioA_clk {
+ #clock-cells = <0>;
+ reg = <2>;
+ };
+
+ pioB_clk: pioB_clk {
+ #clock-cells = <0>;
+ reg = <3>;
+ };
+
+ pioC_clk: pioC_clk {
+ #clock-cells = <0>;
+ reg = <4>;
+ };
+
+ adc_clk: adc_clk {
+ #clock-cells = <0>;
+ reg = <5>;
+ };
+
+ usart0_clk: usart0_clk {
+ #clock-cells = <0>;
+ reg = <6>;
+ };
+
+ usart1_clk: usart1_clk {
+ #clock-cells = <0>;
+ reg = <7>;
+ };
+
+ usart2_clk: usart2_clk {
+ #clock-cells = <0>;
+ reg = <8>;
+ };
+
+ mci0_clk: mci0_clk {
+ #clock-cells = <0>;
+ reg = <9>;
+ };
+
+ udc_clk: udc_clk {
+ #clock-cells = <0>;
+ reg = <10>;
+ };
+
+ twi0_clk: twi0_clk {
+ reg = <11>;
+ #clock-cells = <0>;
+ };
+
+ spi0_clk: spi0_clk {
+ #clock-cells = <0>;
+ reg = <12>;
+ };
+
+ spi1_clk: spi1_clk {
+ #clock-cells = <0>;
+ reg = <13>;
+ };
+
+ ssc0_clk: ssc0_clk {
+ #clock-cells = <0>;
+ reg = <14>;
+ };
+
+ tc0_clk: tc0_clk {
+ #clock-cells = <0>;
+ reg = <17>;
+ };
+
+ tc1_clk: tc1_clk {
+ #clock-cells = <0>;
+ reg = <18>;
+ };
+
+ tc2_clk: tc2_clk {
+ #clock-cells = <0>;
+ reg = <19>;
+ };
+
+ ohci_clk: ohci_clk {
+ #clock-cells = <0>;
+ reg = <20>;
+ };
+
+ macb0_clk: macb0_clk {
+ #clock-cells = <0>;
+ reg = <21>;
+ };
+
+ isi_clk: isi_clk {
+ #clock-cells = <0>;
+ reg = <22>;
+ };
+
+ usart3_clk: usart3_clk {
+ #clock-cells = <0>;
+ reg = <23>;
+ };
+
+ uart0_clk: uart0_clk {
+ #clock-cells = <0>;
+ reg = <24>;
+ };
+
+ uart1_clk: uart1_clk {
+ #clock-cells = <0>;
+ reg = <25>;
+ };
+
+ tc3_clk: tc3_clk {
+ #clock-cells = <0>;
+ reg = <26>;
+ };
+
+ tc4_clk: tc4_clk {
+ #clock-cells = <0>;
+ reg = <27>;
+ };
+
+ tc5_clk: tc5_clk {
+ #clock-cells = <0>;
+ reg = <28>;
+ };
+ };
+ };
+
+ rstc@fffffd00 {
+ compatible = "atmel,at91sam9260-rstc";
+ reg = <0xfffffd00 0x10>;
+ clocks = <&clk32k>;
+ };
+
+ shdwc@fffffd10 {
+ compatible = "atmel,at91sam9260-shdwc";
+ reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
+ };
+
+ pit: timer@fffffd30 {
+ compatible = "atmel,at91sam9260-pit";
+ reg = <0xfffffd30 0xf>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
+ };
+
+ tcb0: timer@fffa0000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0xfffa0000 0x100>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
+ 18 IRQ_TYPE_LEVEL_HIGH 0
+ 19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ };
+
+ tcb1: timer@fffdc000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0xfffdc000 0x100>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
+ 27 IRQ_TYPE_LEVEL_HIGH 0
+ 28 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ };
+
+ pinctrl@fffff400 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+ ranges = <0xfffff400 0xfffff400 0x600>;
+
+ atmel,mux-mask = <
+ /* A B */
+ 0xffffffff 0xffc00c3b /* pioA */
+ 0xffffffff 0x7fff3ccf /* pioB */
+ 0xffffffff 0x007fffff /* pioC */
+ >;
+
+ /* shared pinctrl settings */
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins =
+ <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
+ AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */
+ };
+ };
+
+ usart0 {
+ pinctrl_usart0: usart0-0 {
+ atmel,pins =
+ <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
+ };
+
+ pinctrl_usart0_rts: usart0_rts-0 {
+ atmel,pins =
+ <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
+ };
+
+ pinctrl_usart0_cts: usart0_cts-0 {
+ atmel,pins =
+ <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */
+ };
+
+ pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
+ atmel,pins =
+ <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A */
+ AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */
+ };
+
+ pinctrl_usart0_dcd: usart0_dcd-0 {
+ atmel,pins =
+ <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
+ };
+
+ pinctrl_usart0_ri: usart0_ri-0 {
+ atmel,pins =
+ <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
+ };
+ };
+
+ usart1 {
+ pinctrl_usart1: usart1-0 {
+ atmel,pins =
+ <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
+ };
+
+ pinctrl_usart1_rts: usart1_rts-0 {
+ atmel,pins =
+ <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */
+ };
+
+ pinctrl_usart1_cts: usart1_cts-0 {
+ atmel,pins =
+ <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */
+ };
+ };
+
+ usart2 {
+ pinctrl_usart2: usart2-0 {
+ atmel,pins =
+ <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB9 periph A */
+ };
+
+ pinctrl_usart2_rts: usart2_rts-0 {
+ atmel,pins =
+ <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */
+ };
+
+ pinctrl_usart2_cts: usart2_cts-0 {
+ atmel,pins =
+ <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
+ };
+ };
+
+ usart3 {
+ pinctrl_usart3: usart3-0 {
+ atmel,pins =
+ <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB10 periph A with pullup */
+ AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
+ };
+
+ pinctrl_usart3_rts: usart3_rts-0 {
+ atmel,pins =
+ <AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_usart3_cts: usart3_cts-0 {
+ atmel,pins =
+ <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ uart0 {
+ pinctrl_uart0: uart0-0 {
+ atmel,pins =
+ <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA31 periph B with pullup */
+ AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1: uart1-0 {
+ atmel,pins =
+ <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB12 periph A with pullup */
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
+ };
+ };
+
+ nand {
+ pinctrl_nand: nand-0 {
+ atmel,pins =
+ <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC13 gpio RDY pin pull_up */
+ AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
+ };
+ };
+
+ macb {
+ pinctrl_macb_rmii: macb_rmii-0 {
+ atmel,pins =
+ <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
+ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
+ AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
+ AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
+ AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
+ AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
+ AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
+ AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA19 periph A */
+ AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA20 periph A */
+ AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
+ };
+
+ pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+ atmel,pins =
+ <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */
+ AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA23 periph B */
+ AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
+ AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
+ AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */
+ AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
+ AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
+ AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
+ };
+
+ pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
+ atmel,pins =
+ <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */
+ AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */
+ AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */
+ AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
+ AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */
+ AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
+ AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
+ AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
+ };
+ };
+
+ mmc0 {
+ pinctrl_mmc0_clk: mmc0_clk-0 {
+ atmel,pins =
+ <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
+ };
+
+ pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+ atmel,pins =
+ <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
+ AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA6 periph A with pullup */
+ };
+
+ pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+ atmel,pins =
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */
+ AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */
+ };
+
+ pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
+ atmel,pins =
+ <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */
+ AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */
+ };
+
+ pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
+ atmel,pins =
+ <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
+ AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */
+ AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA3 periph B with pullup */
+ };
+ };
+
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
+ AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A */
+ AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */
+ AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB20 periph A */
+ AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
+ };
+ };
+
+ spi0 {
+ pinctrl_spi0: spi0-0 {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */
+ AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */
+ };
+ };
+
+ spi1 {
+ pinctrl_spi1: spi1-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI1_MOSI pin */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI1_SPCK pin */
+ };
+ };
+
+ i2c_gpio0 {
+ pinctrl_i2c_gpio0: i2c_gpio0-0 {
+ atmel,pins =
+ <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE
+ AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+ };
+ };
+
+ tcb0 {
+ pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+ atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+ atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+ atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+ atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+ atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+ atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+ atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+ atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+ atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ tcb1 {
+ pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+ atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+ atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+ atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+ atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+ atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+ atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+ atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+ atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+ atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ pioA: gpio@fffff400 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ };
+
+ pioB: gpio@fffff600 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ };
+
+ pioC: gpio@fffff800 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioC_clk>;
+ };
+ };
+
+ dbgu: serial@fffff200 {
+ compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0xfffff200 0x200>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart0: serial@fffb0000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfffb0000 0x200>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&usart0_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart1: serial@fffb4000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfffb4000 0x200>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&usart1_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart2: serial@fffb8000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfffb8000 0x200>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&usart2_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart3: serial@fffd0000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfffd0000 0x200>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart3>;
+ clocks = <&usart3_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ uart0: serial@fffd4000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfffd4000 0x200>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&uart0_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ uart1: serial@fffd8000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfffd8000 0x200>;
+ interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ clocks = <&uart1_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ macb0: ethernet@fffc4000 {
+ compatible = "cdns,at91sam9260-macb", "cdns,macb";
+ reg = <0xfffc4000 0x100>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&macb0_clk>, <&macb0_clk>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+
+ usb1: gadget@fffa4000 {
+ compatible = "atmel,at91sam9260-udc";
+ reg = <0xfffa4000 0x4000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&udc_clk>, <&udpck>;
+ clock-names = "pclk", "hclk";
+ status = "disabled";
+ };
+
+ i2c0: i2c@fffac000 {
+ compatible = "atmel,at91sam9260-i2c";
+ reg = <0xfffac000 0x100>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi0_clk>;
+ status = "disabled";
+ };
+
+ mmc0: mmc@fffa8000 {
+ compatible = "atmel,hsmci";
+ reg = <0xfffa8000 0x600>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ clocks = <&mci0_clk>;
+ clock-names = "mci_clk";
+ status = "disabled";
+ };
+
+ ssc0: ssc@fffbc000 {
+ compatible = "atmel,at91rm9200-ssc";
+ reg = <0xfffbc000 0x4000>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&ssc0_clk>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+
+ spi0: spi@fffc8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffc8000 0x200>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&spi0_clk>;
+ clock-names = "spi_clk";
+ status = "disabled";
+ };
+
+ spi1: spi@fffcc000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffcc000 0x200>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&spi1_clk>;
+ clock-names = "spi_clk";
+ status = "disabled";
+ };
+
+ adc0: adc@fffe0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91sam9260-adc";
+ reg = <0xfffe0000 0x100>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&adc_clk>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
+ atmel,adc-use-external-triggers;
+ atmel,adc-channels-used = <0xf>;
+ atmel,adc-vref = <3300>;
+ atmel,adc-startup-time = <15>;
+ atmel,adc-res = <8 10>;
+ atmel,adc-res-names = "lowres", "highres";
+ atmel,adc-use-res = "highres";
+
+ trigger@0 {
+ reg = <0>;
+ trigger-name = "timer-counter-0";
+ trigger-value = <0x1>;
+ };
+ trigger@1 {
+ reg = <1>;
+ trigger-name = "timer-counter-1";
+ trigger-value = <0x3>;
+ };
+
+ trigger@2 {
+ reg = <2>;
+ trigger-name = "timer-counter-2";
+ trigger-value = <0x5>;
+ };
+
+ trigger@3 {
+ reg = <3>;
+ trigger-name = "external";
+ trigger-value = <0xd>;
+ trigger-external;
+ };
+ };
+
+ rtc@fffffd20 {
+ compatible = "atmel,at91sam9260-rtt";
+ reg = <0xfffffd20 0x10>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
+ status = "disabled";
+ };
+
+ watchdog@fffffd40 {
+ compatible = "atmel,at91sam9260-wdt";
+ reg = <0xfffffd40 0x10>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
+ atmel,watchdog-type = "hardware";
+ atmel,reset-type = "all";
+ atmel,dbg-halt;
+ status = "disabled";
+ };
+
+ gpbr: syscon@fffffd50 {
+ compatible = "atmel,at91sam9260-gpbr", "syscon";
+ reg = <0xfffffd50 0x10>;
+ status = "disabled";
+ };
+ };
+
+ nand0: nand@40000000 {
+ compatible = "atmel,at91rm9200-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40000000 0x10000000
+ 0xffffe800 0x200
+ >;
+ atmel,nand-addr-offset = <21>;
+ atmel,nand-cmd-offset = <22>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ gpios = <&pioC 13 GPIO_ACTIVE_HIGH
+ &pioC 14 GPIO_ACTIVE_HIGH
+ 0
+ >;
+ status = "disabled";
+ };
+
+ usb0: ohci@00500000 {
+ compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+ reg = <0x00500000 0x100000>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
+ status = "disabled";
+ };
+ };
+
+ i2c@0 {
+ compatible = "i2c-gpio";
+ gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
+ &pioA 24 GPIO_ACTIVE_HIGH /* scl */
+ >;
+ i2c-gpio,sda-open-drain;
+ i2c-gpio,scl-open-drain;
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c_gpio0>;
+ status = "disabled";
+ };
+};
--- /dev/null
+/*
+ * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
+ *
+ * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
+ *
+ * Licensed under GPLv2 only.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+
+/ {
+ model = "Atmel AT91SAM9261 family SoC";
+ compatible = "atmel,at91sam9261";
+ interrupt-parent = <&aic>;
+
+ aliases {
+ serial0 = &dbgu;
+ serial1 = &usart0;
+ serial2 = &usart1;
+ serial3 = &usart2;
+ gpio0 = &pioA;
+ gpio1 = &pioB;
+ gpio2 = &pioC;
+ tcb0 = &tcb0;
+ i2c0 = &i2c0;
+ ssc0 = &ssc0;
+ ssc1 = &ssc1;
+ ssc2 = &ssc2;
+ };
+
+ cpus {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
+ };
+
+ memory {
+ reg = <0x20000000 0x08000000>;
+ };
+
+ clocks {
+ main_xtal: main_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ slow_xtal: slow_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ sram: sram@00300000 {
+ compatible = "mmio-sram";
+ reg = <0x00300000 0x28000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usb0: ohci@00500000 {
+ compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+ reg = <0x00500000 0x100000>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&ohci_clk>, <&hclk0>, <&uhpck>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
+ status = "disabled";
+ };
+
+ fb0: fb@0x00600000 {
+ compatible = "atmel,at91sam9261-lcdc";
+ reg = <0x00600000 0x1000>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fb>;
+ clocks = <&lcd_clk>, <&hclk1>;
+ clock-names = "lcdc_clk", "hclk";
+ status = "disabled";
+ };
+
+ nand0: nand@40000000 {
+ compatible = "atmel,at91rm9200-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40000000 0x10000000>;
+ atmel,nand-addr-offset = <22>;
+ atmel,nand-cmd-offset = <21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+
+ gpios = <&pioC 15 GPIO_ACTIVE_HIGH>,
+ <&pioC 14 GPIO_ACTIVE_HIGH>,
+ <0>;
+ status = "disabled";
+ };
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ tcb0: timer@fffa0000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0xfffa0000 0x100>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
+ <18 IRQ_TYPE_LEVEL_HIGH 0>,
+ <19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
+ };
+
+ usb1: gadget@fffa4000 {
+ compatible = "atmel,at91sam9261-udc";
+ reg = <0xfffa4000 0x4000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&udc_clk>, <&udpck>;
+ clock-names = "pclk", "hclk";
+ atmel,matrix = <&matrix>;
+ status = "disabled";
+ };
+
+ mmc0: mmc@fffa8000 {
+ compatible = "atmel,hsmci";
+ reg = <0xfffa8000 0x600>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mci0_clk>;
+ clock-names = "mci_clk";
+ status = "disabled";
+ };
+
+ i2c0: i2c@fffac000 {
+ compatible = "atmel,at91sam9261-i2c";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c_twi>;
+ reg = <0xfffac000 0x100>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi0_clk>;
+ status = "disabled";
+ };
+
+ usart0: serial@fffb0000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfffb0000 0x200>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&usart0_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart1: serial@fffb4000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfffb4000 0x200>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&usart1_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart2: serial@fffb8000{
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfffb8000 0x200>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&usart2_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ ssc0: ssc@fffbc000 {
+ compatible = "atmel,at91rm9200-ssc";
+ reg = <0xfffbc000 0x4000>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&ssc0_clk>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+
+ ssc1: ssc@fffc0000 {
+ compatible = "atmel,at91rm9200-ssc";
+ reg = <0xfffc0000 0x4000>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&ssc1_clk>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+
+ ssc2: ssc@fffc4000 {
+ compatible = "atmel,at91rm9200-ssc";
+ reg = <0xfffc4000 0x4000>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
+ clocks = <&ssc2_clk>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+
+ spi0: spi@fffc8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffc8000 0x200>;
+ cs-gpios = <0>, <0>, <0>, <0>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&spi0_clk>;
+ clock-names = "spi_clk";
+ status = "disabled";
+ };
+
+ spi1: spi@fffcc000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffcc000 0x200>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&spi1_clk>;
+ clock-names = "spi_clk";
+ status = "disabled";
+ };
+
+ ramc: ramc@ffffea00 {
+ compatible = "atmel,at91sam9260-sdramc";
+ reg = <0xffffea00 0x200>;
+ };
+
+ matrix: matrix@ffffee00 {
+ compatible = "atmel,at91sam9260-bus-matrix", "syscon";
+ reg = <0xffffee00 0x200>;
+ };
+
+ aic: interrupt-controller@fffff000 {
+ #interrupt-cells = <3>;
+ compatible = "atmel,at91rm9200-aic";
+ interrupt-controller;
+ reg = <0xfffff000 0x200>;
+ atmel,external-irqs = <29 30 31>;
+ };
+
+ dbgu: serial@fffff200 {
+ compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0xfffff200 0x200>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ pinctrl@fffff400 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+ ranges = <0xfffff400 0xfffff400 0x600>;
+
+ atmel,mux-mask =
+ /* A B */
+ <0xffffffff 0xfffffff7>, /* pioA */
+ <0xffffffff 0xfffffff4>, /* pioB */
+ <0xffffffff 0xffffff07>; /* pioC */
+
+ /* shared pinctrl settings */
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins =
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ usart0 {
+ pinctrl_usart0: usart0-0 {
+ atmel,pins =
+ <AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_usart0_rts: usart0_rts-0 {
+ atmel,pins =
+ <AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_usart0_cts: usart0_cts-0 {
+ atmel,pins =
+ <AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ usart1 {
+ pinctrl_usart1: usart1-0 {
+ atmel,pins =
+ <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_usart1_rts: usart1_rts-0 {
+ atmel,pins =
+ <AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_usart1_cts: usart1_cts-0 {
+ atmel,pins =
+ <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ usart2 {
+ pinctrl_usart2: usart2-0 {
+ atmel,pins =
+ <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_usart2_rts: usart2_rts-0 {
+ atmel,pins =
+ <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_usart2_cts: usart2_cts-0 {
+ atmel,pins =
+ <AT91_PIOA 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ nand {
+ pinctrl_nand: nand-0 {
+ atmel,pins =
+ <AT91_PIOC 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ mmc0 {
+ pinctrl_mmc0_clk: mmc0_clk-0 {
+ atmel,pins =
+ <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+ atmel,pins =
+ <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+ atmel,pins =
+ <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
+ <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ ssc1 {
+ pinctrl_ssc1_tx: ssc1_tx-0 {
+ atmel,pins =
+ <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+ <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+ <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ssc1_rx: ssc1_rx-0 {
+ atmel,pins =
+ <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+ <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+ <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ ssc2 {
+ pinctrl_ssc2_tx: ssc2_tx-0 {
+ atmel,pins =
+ <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+ <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+ <AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ssc2_rx: ssc2_rx-0 {
+ atmel,pins =
+ <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+ <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+ <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ spi0 {
+ pinctrl_spi0: spi0-0 {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ spi1 {
+ pinctrl_spi1: spi1-0 {
+ atmel,pins =
+ <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ tcb0 {
+ pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+ atmel,pins = <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+ atmel,pins = <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+ atmel,pins = <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+ atmel,pins = <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+ atmel,pins = <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+ atmel,pins = <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+ atmel,pins = <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+ atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+ atmel,pins = <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ i2c0 {
+ pinctrl_i2c_bitbang: i2c-0-bitbang {
+ atmel,pins =
+ <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>,
+ <AT91_PIOA 8 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_i2c_twi: i2c-0-twi {
+ atmel,pins =
+ <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ fb {
+ pinctrl_fb: fb-0 {
+ atmel,pins =
+ <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+ <AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+ <AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+ <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+ <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+ <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ pioA: gpio@fffff400 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ };
+
+ pioB: gpio@fffff600 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ };
+
+ pioC: gpio@fffff800 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioC_clk>;
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ compatible = "atmel,at91rm9200-pmc", "syscon";
+ reg = <0xfffffc00 0x100>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ main_osc: main_osc {
+ compatible = "atmel,at91rm9200-clk-main-osc";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+ clocks = <&main_xtal>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main";
+ #clock-cells = <0>;
+ clocks = <&main_osc>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+ clocks = <&main>;
+ reg = <0>;
+ atmel,clk-input-range = <1000000 32000000>;
+ #atmel,pll-clk-output-range-cells = <4>;
+ atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
+ <190000000 240000000 2 1>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_LOCKB>;
+ clocks = <&main>;
+ reg = <1>;
+ atmel,clk-input-range = <1000000 5000000>;
+ #atmel,pll-clk-output-range-cells = <4>;
+ atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+ clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
+ atmel,clk-output-range = <0 94000000>;
+ atmel,clk-divisors = <1 2 4 0>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ atmel,clk-divisors = <1 2 4 0>;
+ clocks = <&pllb>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&pmc>;
+ clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
+
+ prog0: prog0 {
+ #clock-cells = <0>;
+ reg = <0>;
+ interrupts = <AT91_PMC_PCKRDY(0)>;
+ };
+
+ prog1: prog1 {
+ #clock-cells = <0>;
+ reg = <1>;
+ interrupts = <AT91_PMC_PCKRDY(1)>;
+ };
+
+ prog2: prog2 {
+ #clock-cells = <0>;
+ reg = <2>;
+ interrupts = <AT91_PMC_PCKRDY(2)>;
+ };
+
+ prog3: prog3 {
+ #clock-cells = <0>;
+ reg = <3>;
+ interrupts = <AT91_PMC_PCKRDY(3)>;
+ };
+ };
+
+ systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ uhpck: uhpck {
+ #clock-cells = <0>;
+ reg = <6>;
+ clocks = <&usb>;
+ };
+
+ udpck: udpck {
+ #clock-cells = <0>;
+ reg = <7>;
+ clocks = <&usb>;
+ };
+
+ pck0: pck0 {
+ #clock-cells = <0>;
+ reg = <8>;
+ clocks = <&prog0>;
+ };
+
+ pck1: pck1 {
+ #clock-cells = <0>;
+ reg = <9>;
+ clocks = <&prog1>;
+ };
+
+ pck2: pck2 {
+ #clock-cells = <0>;
+ reg = <10>;
+ clocks = <&prog2>;
+ };
+
+ pck3: pck3 {
+ #clock-cells = <0>;
+ reg = <11>;
+ clocks = <&prog3>;
+ };
+
+ hclk0: hclk0 {
+ #clock-cells = <0>;
+ reg = <16>;
+ clocks = <&mck>;
+ };
+
+ hclk1: hclk1 {
+ #clock-cells = <0>;
+ reg = <17>;
+ clocks = <&mck>;
+ };
+ };
+
+ periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mck>;
+
+ pioA_clk: pioA_clk {
+ #clock-cells = <0>;
+ reg = <2>;
+ };
+
+ pioB_clk: pioB_clk {
+ #clock-cells = <0>;
+ reg = <3>;
+ };
+
+ pioC_clk: pioC_clk {
+ #clock-cells = <0>;
+ reg = <4>;
+ };
+
+ usart0_clk: usart0_clk {
+ #clock-cells = <0>;
+ reg = <6>;
+ };
+
+ usart1_clk: usart1_clk {
+ #clock-cells = <0>;
+ reg = <7>;
+ };
+
+ usart2_clk: usart2_clk {
+ #clock-cells = <0>;
+ reg = <8>;
+ };
+
+ mci0_clk: mci0_clk {
+ #clock-cells = <0>;
+ reg = <9>;
+ };
+
+ udc_clk: udc_clk {
+ #clock-cells = <0>;
+ reg = <10>;
+ };
+
+ twi0_clk: twi0_clk {
+ reg = <11>;
+ #clock-cells = <0>;
+ };
+
+ spi0_clk: spi0_clk {
+ #clock-cells = <0>;
+ reg = <12>;
+ };
+
+ spi1_clk: spi1_clk {
+ #clock-cells = <0>;
+ reg = <13>;
+ };
+
+ ssc0_clk: ssc0_clk {
+ #clock-cells = <0>;
+ reg = <14>;
+ };
+
+ ssc1_clk: ssc1_clk {
+ #clock-cells = <0>;
+ reg = <15>;
+ };
+
+ ssc2_clk: ssc2_clk {
+ #clock-cells = <0>;
+ reg = <16>;
+ };
+
+ tc0_clk: tc0_clk {
+ #clock-cells = <0>;
+ reg = <17>;
+ };
+
+ tc1_clk: tc1_clk {
+ #clock-cells = <0>;
+ reg = <18>;
+ };
+
+ tc2_clk: tc2_clk {
+ #clock-cells = <0>;
+ reg = <19>;
+ };
+
+ ohci_clk: ohci_clk {
+ #clock-cells = <0>;
+ reg = <20>;
+ };
+
+ lcd_clk: lcd_clk {
+ #clock-cells = <0>;
+ reg = <21>;
+ };
+ };
+ };
+
+ rstc@fffffd00 {
+ compatible = "atmel,at91sam9260-rstc";
+ reg = <0xfffffd00 0x10>;
+ clocks = <&slow_xtal>;
+ };
+
+ shdwc@fffffd10 {
+ compatible = "atmel,at91sam9260-shdwc";
+ reg = <0xfffffd10 0x10>;
+ clocks = <&slow_xtal>;
+ };
+
+ pit: timer@fffffd30 {
+ compatible = "atmel,at91sam9260-pit";
+ reg = <0xfffffd30 0xf>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
+ };
+
+ rtc@fffffd20 {
+ compatible = "atmel,at91sam9260-rtt";
+ reg = <0xfffffd20 0x10>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&slow_xtal>;
+ status = "disabled";
+ };
+
+ watchdog@fffffd40 {
+ compatible = "atmel,at91sam9260-wdt";
+ reg = <0xfffffd40 0x10>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&slow_xtal>;
+ status = "disabled";
+ };
+
+ gpbr: syscon@fffffd50 {
+ compatible = "atmel,at91sam9260-gpbr", "syscon";
+ reg = <0xfffffd50 0x10>;
+ status = "disabled";
+ };
+ };
+ };
+
+ i2c@0 {
+ compatible = "i2c-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c_bitbang>;
+ gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */
+ <&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */
+ i2c-gpio,sda-open-drain;
+ i2c-gpio,scl-open-drain;
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+};
--- /dev/null
+/*
+ * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 only.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+
+/ {
+ model = "Atmel AT91SAM9263 family SoC";
+ compatible = "atmel,at91sam9263";
+ interrupt-parent = <&aic>;
+
+ aliases {
+ serial0 = &dbgu;
+ serial1 = &usart0;
+ serial2 = &usart1;
+ serial3 = &usart2;
+ gpio0 = &pioA;
+ gpio1 = &pioB;
+ gpio2 = &pioC;
+ gpio3 = &pioD;
+ gpio4 = &pioE;
+ tcb0 = &tcb0;
+ i2c0 = &i2c0;
+ ssc0 = &ssc0;
+ ssc1 = &ssc1;
+ pwm0 = &pwm0;
+ };
+
+ cpus {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
+ };
+
+ memory {
+ reg = <0x20000000 0x08000000>;
+ };
+
+ clocks {
+ main_xtal: main_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ slow_xtal: slow_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ sram0: sram@00300000 {
+ compatible = "mmio-sram";
+ reg = <0x00300000 0x14000>;
+ };
+
+ sram1: sram@00500000 {
+ compatible = "mmio-sram";
+ reg = <0x00500000 0x4000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ aic: interrupt-controller@fffff000 {
+ #interrupt-cells = <3>;
+ compatible = "atmel,at91rm9200-aic";
+ interrupt-controller;
+ reg = <0xfffff000 0x200>;
+ atmel,external-irqs = <30 31>;
+ };
+
+ pmc: pmc@fffffc00 {
+ compatible = "atmel,at91rm9200-pmc", "syscon";
+ reg = <0xfffffc00 0x100>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+
+ main_osc: main_osc {
+ compatible = "atmel,at91rm9200-clk-main-osc";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+ clocks = <&main_xtal>;
+ };
+
+ main: mainck {
+ compatible = "atmel,at91rm9200-clk-main";
+ #clock-cells = <0>;
+ clocks = <&main_osc>;
+ };
+
+ plla: pllack {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+ clocks = <&main>;
+ reg = <0>;
+ atmel,clk-input-range = <1000000 32000000>;
+ #atmel,pll-clk-output-range-cells = <4>;
+ atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
+ <190000000 240000000 2 1>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91rm9200-clk-pll";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_LOCKB>;
+ clocks = <&main>;
+ reg = <1>;
+ atmel,clk-input-range = <1000000 32000000>;
+ #atmel,pll-clk-output-range-cells = <4>;
+ atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
+ <190000000 240000000 2 1>;
+ };
+
+ mck: masterck {
+ compatible = "atmel,at91rm9200-clk-master";
+ #clock-cells = <0>;
+ interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+ clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
+ atmel,clk-output-range = <0 120000000>;
+ atmel,clk-divisors = <1 2 4 0>;
+ };
+
+ usb: usbck {
+ compatible = "atmel,at91rm9200-clk-usb";
+ #clock-cells = <0>;
+ atmel,clk-divisors = <1 2 4 0>;
+ clocks = <&pllb>;
+ };
+
+ prog: progck {
+ compatible = "atmel,at91rm9200-clk-programmable";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&pmc>;
+ clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
+
+ prog0: prog0 {
+ #clock-cells = <0>;
+ reg = <0>;
+ interrupts = <AT91_PMC_PCKRDY(0)>;
+ };
+
+ prog1: prog1 {
+ #clock-cells = <0>;
+ reg = <1>;
+ interrupts = <AT91_PMC_PCKRDY(1)>;
+ };
+
+ prog2: prog2 {
+ #clock-cells = <0>;
+ reg = <2>;
+ interrupts = <AT91_PMC_PCKRDY(2)>;
+ };
+
+ prog3: prog3 {
+ #clock-cells = <0>;
+ reg = <3>;
+ interrupts = <AT91_PMC_PCKRDY(3)>;
+ };
+ };
+
+ systemck {
+ compatible = "atmel,at91rm9200-clk-system";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ uhpck: uhpck {
+ #clock-cells = <0>;
+ reg = <6>;
+ clocks = <&usb>;
+ };
+
+ udpck: udpck {
+ #clock-cells = <0>;
+ reg = <7>;
+ clocks = <&usb>;
+ };
+
+ pck0: pck0 {
+ #clock-cells = <0>;
+ reg = <8>;
+ clocks = <&prog0>;
+ };
+
+ pck1: pck1 {
+ #clock-cells = <0>;
+ reg = <9>;
+ clocks = <&prog1>;
+ };
+
+ pck2: pck2 {
+ #clock-cells = <0>;
+ reg = <10>;
+ clocks = <&prog2>;
+ };
+
+ pck3: pck3 {
+ #clock-cells = <0>;
+ reg = <11>;
+ clocks = <&prog3>;
+ };
+ };
+
+ periphck {
+ compatible = "atmel,at91rm9200-clk-peripheral";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mck>;
+
+ pioA_clk: pioA_clk {
+ #clock-cells = <0>;
+ reg = <2>;
+ };
+
+ pioB_clk: pioB_clk {
+ #clock-cells = <0>;
+ reg = <3>;
+ };
+
+ pioCDE_clk: pioCDE_clk {
+ #clock-cells = <0>;
+ reg = <4>;
+ };
+
+ usart0_clk: usart0_clk {
+ #clock-cells = <0>;
+ reg = <7>;
+ };
+
+ usart1_clk: usart1_clk {
+ #clock-cells = <0>;
+ reg = <8>;
+ };
+
+ usart2_clk: usart2_clk {
+ #clock-cells = <0>;
+ reg = <9>;
+ };
+
+ mci0_clk: mci0_clk {
+ #clock-cells = <0>;
+ reg = <10>;
+ };
+
+ mci1_clk: mci1_clk {
+ #clock-cells = <0>;
+ reg = <11>;
+ };
+
+ can_clk: can_clk {
+ #clock-cells = <0>;
+ reg = <12>;
+ };
+
+ twi0_clk: twi0_clk {
+ #clock-cells = <0>;
+ reg = <13>;
+ };
+
+ spi0_clk: spi0_clk {
+ #clock-cells = <0>;
+ reg = <14>;
+ };
+
+ spi1_clk: spi1_clk {
+ #clock-cells = <0>;
+ reg = <15>;
+ };
+
+ ssc0_clk: ssc0_clk {
+ #clock-cells = <0>;
+ reg = <16>;
+ };
+
+ ssc1_clk: ssc1_clk {
+ #clock-cells = <0>;
+ reg = <17>;
+ };
+
+ ac97_clk: ac97_clk {
+ #clock-cells = <0>;
+ reg = <18>;
+ };
+
+ tcb_clk: tcb_clk {
+ #clock-cells = <0>;
+ reg = <19>;
+ };
+
+ pwm_clk: pwm_clk {
+ #clock-cells = <0>;
+ reg = <20>;
+ };
+
+ macb0_clk: macb0_clk {
+ #clock-cells = <0>;
+ reg = <21>;
+ };
+
+ g2de_clk: g2de_clk {
+ #clock-cells = <0>;
+ reg = <23>;
+ };
+
+ udc_clk: udc_clk {
+ #clock-cells = <0>;
+ reg = <24>;
+ };
+
+ isi_clk: isi_clk {
+ #clock-cells = <0>;
+ reg = <25>;
+ };
+
+ lcd_clk: lcd_clk {
+ #clock-cells = <0>;
+ reg = <26>;
+ };
+
+ dma_clk: dma_clk {
+ #clock-cells = <0>;
+ reg = <27>;
+ };
+
+ ohci_clk: ohci_clk {
+ #clock-cells = <0>;
+ reg = <29>;
+ };
+ };
+ };
+
+ ramc0: ramc@ffffe200 {
+ compatible = "atmel,at91sam9260-sdramc";
+ reg = <0xffffe200 0x200>;
+ };
+
+ ramc1: ramc@ffffe800 {
+ compatible = "atmel,at91sam9260-sdramc";
+ reg = <0xffffe800 0x200>;
+ };
+
+ pit: timer@fffffd30 {
+ compatible = "atmel,at91sam9260-pit";
+ reg = <0xfffffd30 0xf>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&mck>;
+ };
+
+ tcb0: timer@fff7c000 {
+ compatible = "atmel,at91rm9200-tcb";
+ reg = <0xfff7c000 0x100>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&tcb_clk>, <&slow_xtal>;
+ clock-names = "t0_clk", "slow_clk";
+ };
+
+ rstc@fffffd00 {
+ compatible = "atmel,at91sam9260-rstc";
+ reg = <0xfffffd00 0x10>;
+ clocks = <&slow_xtal>;
+ };
+
+ shdwc@fffffd10 {
+ compatible = "atmel,at91sam9260-shdwc";
+ reg = <0xfffffd10 0x10>;
+ clocks = <&slow_xtal>;
+ };
+
+ pinctrl@fffff200 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+ ranges = <0xfffff200 0xfffff200 0xa00>;
+
+ atmel,mux-mask = <
+ /* A B */
+ 0xfffffffb 0xffffe07f /* pioA */
+ 0x0007ffff 0x39072fff /* pioB */
+ 0xffffffff 0x3ffffff8 /* pioC */
+ 0xfffffbff 0xffffffff /* pioD */
+ 0xffe00fff 0xfbfcff00 /* pioE */
+ >;
+
+ /* shared pinctrl settings */
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins =
+ <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */
+ AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */
+ };
+ };
+
+ usart0 {
+ pinctrl_usart0: usart0-0 {
+ atmel,pins =
+ <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA26 periph A with pullup */
+ AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
+ };
+
+ pinctrl_usart0_rts: usart0_rts-0 {
+ atmel,pins =
+ <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */
+ };
+
+ pinctrl_usart0_cts: usart0_cts-0 {
+ atmel,pins =
+ <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */
+ };
+ };
+
+ usart1 {
+ pinctrl_usart1: usart1-0 {
+ atmel,pins =
+ <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
+ AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD1 periph A */
+ };
+
+ pinctrl_usart1_rts: usart1_rts-0 {
+ atmel,pins =
+ <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */
+ };
+
+ pinctrl_usart1_cts: usart1_cts-0 {
+ atmel,pins =
+ <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */
+ };
+ };
+
+ usart2 {
+ pinctrl_usart2: usart2-0 {
+ atmel,pins =
+ <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */
+ AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD3 periph A */
+ };
+
+ pinctrl_usart2_rts: usart2_rts-0 {
+ atmel,pins =
+ <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */
+ };
+
+ pinctrl_usart2_cts: usart2_cts-0 {
+ atmel,pins =
+ <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */
+ };
+ };
+
+ nand {
+ pinctrl_nand: nand-0 {
+ atmel,pins =
+ <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PA22 gpio RDY pin pull_up*/
+ AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD15 gpio enable pin pull_up */
+ };
+ };
+
+ macb {
+ pinctrl_macb_rmii: macb_rmii-0 {
+ atmel,pins =
+ <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
+ AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
+ AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
+ AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
+ AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
+ AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
+ AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
+ AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
+ AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
+ AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
+ };
+
+ pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+ atmel,pins =
+ <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
+ AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
+ AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */
+ AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */
+ AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */
+ AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
+ AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
+ AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */
+ };
+ };
+
+ mmc0 {
+ pinctrl_mmc0_clk: mmc0_clk-0 {
+ atmel,pins =
+ <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */
+ };
+
+ pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+ atmel,pins =
+ <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
+ AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */
+ };
+
+ pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+ atmel,pins =
+ <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
+ AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
+ AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
+ };
+
+ pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
+ atmel,pins =
+ <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
+ AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */
+ };
+
+ pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
+ atmel,pins =
+ <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
+ AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
+ AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
+ };
+ };
+
+ mmc1 {
+ pinctrl_mmc1_clk: mmc1_clk-0 {
+ atmel,pins =
+ <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
+ };
+
+ pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
+ atmel,pins =
+ <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
+ AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */
+ };
+
+ pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
+ atmel,pins =
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */
+ AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */
+ };
+
+ pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
+ atmel,pins =
+ <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */
+ AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */
+ };
+
+ pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
+ atmel,pins =
+ <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */
+ AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
+ AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */
+ };
+ };
+
+ ssc0 {
+ pinctrl_ssc0_tx: ssc0_tx-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */
+ AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */
+ AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */
+ };
+
+ pinctrl_ssc0_rx: ssc0_rx-0 {
+ atmel,pins =
+ <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */
+ AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */
+ AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */
+ };
+ };
+
+ ssc1 {
+ pinctrl_ssc1_tx: ssc1_tx-0 {
+ atmel,pins =
+ <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
+ AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
+ };
+
+ pinctrl_ssc1_rx: ssc1_rx-0 {
+ atmel,pins =
+ <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
+ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
+ AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
+ };
+ };
+
+ spi0 {
+ pinctrl_spi0: spi0-0 {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */
+ AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */
+ AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */
+ };
+ };
+
+ spi1 {
+ pinctrl_spi1: spi1-0 {
+ atmel,pins =
+ <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */
+ AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */
+ AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */
+ };
+ };
+
+ tcb0 {
+ pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+ atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+ atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+ atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+ atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+ atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+ atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+ atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+ atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+ atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ fb {
+ pinctrl_fb: fb-0 {
+ atmel,pins =
+ <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A */
+ AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A */
+ AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A */
+ AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB9 periph B */
+ AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A */
+ AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A */
+ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A */
+ AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 periph A */
+ AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 periph A */
+ AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A */
+ AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A */
+ AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A */
+ AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A */
+ AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC12 periph B */
+ AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC18 periph A */
+ AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A */
+ AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A */
+ AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A */
+ AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC24 periph A */
+ AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC17 periph B */
+ AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC26 periph A */
+ AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */
+ };
+ };
+
+ can {
+ pinctrl_can_rx_tx: can_rx_tx {
+ atmel,pins =
+ <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* CANRX, conflicts with IRQ0 */
+ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* CANTX, conflicts with PCK0 */
+ };
+ };
+
+ ac97 {
+ pinctrl_ac97: ac97-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A AC97FS pin */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A AC97CK pin */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A AC97TX pin */
+ AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A AC97RX pin */
+ };
+ };
+
+ pioA: gpio@fffff200 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff200 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ };
+
+ pioB: gpio@fffff400 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ };
+
+ pioC: gpio@fffff600 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioCDE_clk>;
+ };
+
+ pioD: gpio@fffff800 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioCDE_clk>;
+ };
+
+ pioE: gpio@fffffa00 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffffa00 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioCDE_clk>;
+ };
+ };
+
+ dbgu: serial@ffffee00 {
+ compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0xffffee00 0x200>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&mck>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart0: serial@fff8c000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfff8c000 0x200>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart0>;
+ clocks = <&usart0_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart1: serial@fff90000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfff90000 0x200>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart1>;
+ clocks = <&usart1_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ usart2: serial@fff94000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfff94000 0x200>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart2>;
+ clocks = <&usart2_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ ssc0: ssc@fff98000 {
+ compatible = "atmel,at91rm9200-ssc";
+ reg = <0xfff98000 0x4000>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+ clocks = <&ssc0_clk>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+
+ ssc1: ssc@fff9c000 {
+ compatible = "atmel,at91rm9200-ssc";
+ reg = <0xfff9c000 0x4000>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+ clocks = <&ssc1_clk>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+
+ ac97: sound@fffa0000 {
+ compatible = "atmel,at91sam9263-ac97c";
+ reg = <0xfffa0000 0x4000>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ac97>;
+ clocks = <&ac97_clk>;
+ clock-names = "ac97_clk";
+ status = "disabled";
+ };
+
+ macb0: ethernet@fffbc000 {
+ compatible = "cdns,at91sam9260-macb", "cdns,macb";
+ reg = <0xfffbc000 0x100>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb_rmii>;
+ clocks = <&macb0_clk>, <&macb0_clk>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+
+ usb1: gadget@fff78000 {
+ compatible = "atmel,at91sam9263-udc";
+ reg = <0xfff78000 0x4000>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&udc_clk>, <&udpck>;
+ clock-names = "pclk", "hclk";
+ status = "disabled";
+ };
+
+ i2c0: i2c@fff88000 {
+ compatible = "atmel,at91sam9260-i2c";
+ reg = <0xfff88000 0x100>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&twi0_clk>;
+ status = "disabled";
+ };
+
+ mmc0: mmc@fff80000 {
+ compatible = "atmel,hsmci";
+ reg = <0xfff80000 0x600>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mci0_clk>;
+ clock-names = "mci_clk";
+ status = "disabled";
+ };
+
+ mmc1: mmc@fff84000 {
+ compatible = "atmel,hsmci";
+ reg = <0xfff84000 0x600>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mci1_clk>;
+ clock-names = "mci_clk";
+ status = "disabled";
+ };
+
+ watchdog@fffffd40 {
+ compatible = "atmel,at91sam9260-wdt";
+ reg = <0xfffffd40 0x10>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&slow_xtal>;
+ atmel,watchdog-type = "hardware";
+ atmel,reset-type = "all";
+ atmel,dbg-halt;
+ status = "disabled";
+ };
+
+ spi0: spi@fffa4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffa4000 0x200>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&spi0_clk>;
+ clock-names = "spi_clk";
+ status = "disabled";
+ };
+
+ spi1: spi@fffa8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0xfffa8000 0x200>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&spi1_clk>;
+ clock-names = "spi_clk";
+ status = "disabled";
+ };
+
+ pwm0: pwm@fffb8000 {
+ compatible = "atmel,at91sam9rl-pwm";
+ reg = <0xfffb8000 0x300>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
+ #pwm-cells = <3>;
+ clocks = <&pwm_clk>;
+ clock-names = "pwm_clk";
+ status = "disabled";
+ };
+
+ can: can@fffac000 {
+ compatible = "atmel,at91sam9263-can";
+ reg = <0xfffac000 0x300>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can_rx_tx>;
+ clocks = <&can_clk>;
+ clock-names = "can_clk";
+ };
+
+ rtc@fffffd20 {
+ compatible = "atmel,at91sam9260-rtt";
+ reg = <0xfffffd20 0x10>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&slow_xtal>;
+ status = "disabled";
+ };
+
+ rtc@fffffd50 {
+ compatible = "atmel,at91sam9260-rtt";
+ reg = <0xfffffd50 0x10>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&slow_xtal>;
+ status = "disabled";
+ };
+
+ gpbr: syscon@fffffd60 {
+ compatible = "atmel,at91sam9260-gpbr", "syscon";
+ reg = <0xfffffd60 0x50>;
+ status = "disabled";
+ };
+ };
+
+ fb0: fb@0x00700000 {
+ compatible = "atmel,at91sam9263-lcdc";
+ reg = <0x00700000 0x1000>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fb>;
+ clocks = <&lcd_clk>, <&lcd_clk>;
+ clock-names = "lcdc_clk", "hclk";
+ status = "disabled";
+ };
+
+ nand0: nand@40000000 {
+ compatible = "atmel,at91rm9200-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40000000 0x10000000
+ 0xffffe000 0x200
+ >;
+ atmel,nand-addr-offset = <21>;
+ atmel,nand-cmd-offset = <22>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand>;
+ gpios = <&pioA 22 GPIO_ACTIVE_HIGH
+ &pioD 15 GPIO_ACTIVE_HIGH
+ 0
+ >;
+ status = "disabled";
+ };
+
+ usb0: ohci@00a00000 {
+ compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+ reg = <0x00a00000 0x100000>;
+ interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
+ status = "disabled";
+ };
+ };
+
+ i2c@0 {
+ compatible = "i2c-gpio";
+ gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
+ &pioB 5 GPIO_ACTIVE_HIGH /* scl */
+ >;
+ i2c-gpio,sda-open-drain;
+ i2c-gpio,scl-open-drain;
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+};
--- /dev/null
+/*
+ * at91sam9g20-taurus.dts
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+#include "at91sam9g20.dtsi"
+
+/ {
+ model = "Siemens taurus";
+ compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9";
+
+ chosen {
+ stdout-path = &dbgu;
+ };
+
+ memory {
+ reg = <0x20000000 0x4000000>;
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <18432000>;
+ };
+ };
+
+ ahb {
+ apb {
+ pinctrl@fffff400 {
+ board {
+ pinctrl_pck0_as_mck: pck0_as_mck {
+ atmel,pins =
+ <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */
+ };
+
+ };
+ };
+
+ dbgu: serial@fffff200 {
+ status = "okay";
+ };
+
+ usart0: serial@fffb0000 {
+ pinctrl-0 =
+ <&pinctrl_usart0
+ &pinctrl_usart0_rts
+ &pinctrl_usart0_cts
+ &pinctrl_usart0_dtr_dsr
+ &pinctrl_usart0_dcd
+ &pinctrl_usart0_ri>;
+ status = "okay";
+ };
+
+ usart1: serial@fffb4000 {
+ status = "okay";
+ };
+
+ macb0: ethernet@fffc4000 {
+ phy-mode = "rmii";
+ status = "okay";
+ };
+
+ usb1: gadget@fffa4000 {
+ atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ ssc0: ssc@fffbc000 {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_ssc0_tx>;
+ };
+
+ spi0: spi@fffc8000 {
+ cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
+ mtd_dataflash@0 {
+ compatible = "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <50000000>;
+ reg = <1>;
+ };
+ };
+
+ rtc@fffffd20 {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+ status = "okay";
+ };
+
+ watchdog@fffffd40 {
+ status = "okay";
+ };
+
+ gpbr: syscon@fffffd50 {
+ status = "okay";
+ };
+ };
+
+ nand0: nand@40000000 {
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ status = "okay";
+ };
+
+ usb0: ohci@00500000 {
+ num-ports = <2>;
+ status = "okay";
+ };
+ };
+};
--- /dev/null
+/*
+ * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+
+#include "at91sam9260.dtsi"
+
+/ {
+ model = "Atmel AT91SAM9G20 family SoC";
+ compatible = "atmel,at91sam9g20";
+
+ memory {
+ reg = <0x20000000 0x08000000>;
+ };
+
+ sram0: sram@002ff000 {
+ status = "disabled";
+ };
+
+ sram1: sram@002fc000 {
+ compatible = "mmio-sram";
+ reg = <0x002fc000 0x8000>;
+ };
+
+ ahb {
+ apb {
+ i2c0: i2c@fffac000 {
+ compatible = "atmel,at91sam9g20-i2c";
+ };
+
+ ssc0: ssc@fffbc000 {
+ compatible = "atmel,at91sam9rl-ssc";
+ };
+
+ adc0: adc@fffe0000 {
+ atmel,adc-startup-time = <40>;
+ };
+
+ pmc: pmc@fffffc00 {
+ plla: pllack {
+ atmel,clk-input-range = <2000000 32000000>;
+ atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
+ <695000000 750000000 1 0>,
+ <645000000 700000000 2 0>,
+ <595000000 650000000 3 0>,
+ <545000000 600000000 0 1>,
+ <495000000 550000000 1 1>,
+ <445000000 500000000 2 1>,
+ <400000000 450000000 3 1>;
+ };
+
+ pllb: pllbck {
+ compatible = "atmel,at91sam9g20-clk-pllb";
+ atmel,clk-input-range = <2000000 32000000>;
+ atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
+ };
+
+ mck: masterck {
+ atmel,clk-output-range = <0 133000000>;
+ atmel,clk-divisors = <1 2 4 6>;
+ };
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * at91sam9g45-corvus.dts Device Tree file fir Siemens corvus board
+ * (C) Copyright 2016 Heiko Schocher <hs@denx.de>
+ *
+ * based on:
+ * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
+ *
+ * Copyright (C) 2011 Atmel,
+ * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+#include "at91sam9g45.dtsi"
+
+/ {
+ model = "Siemens corvus";
+ compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
+
+ chosen {
+ stdout-path = &dbgu;
+ };
+
+ memory {
+ reg = <0x70000000 0x8000000>;
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ ahb {
+ apb {
+ dbgu: serial@ffffee00 {
+ status = "okay";
+ };
+
+ usart1: serial@fff90000 {
+ pinctrl-0 =
+ <&pinctrl_usart1
+ &pinctrl_usart1_rts
+ &pinctrl_usart1_cts>;
+ status = "okay";
+ };
+
+ macb0: ethernet@fffbc000 {
+ phy-mode = "rmii";
+ status = "okay";
+ };
+
+ watchdog@fffffd40 {
+ status = "okay";
+ };
+
+ spi0: spi@fffa4000{
+ status = "okay";
+ cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;
+ mtd_dataflash@0 {
+ compatible = "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <13000000>;
+ reg = <0>;
+ };
+ };
+
+ usb2: gadget@fff78000 {
+ atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ rtc@fffffd20 {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+ status = "okay";
+ };
+
+ gpbr: syscon@fffffd60 {
+ status = "okay";
+ };
+
+ rtc@fffffdb0 {
+ status = "okay";
+ };
+ };
+
+ nand0: nand@40000000 {
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ status = "okay";
+ };
+
+ usb0: ohci@00700000 {
+ status = "okay";
+ num-ports = <2>;
+ atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW
+ &pioD 3 GPIO_ACTIVE_LOW>;
+ };
+
+ usb1: ehci@00800000 {
+ status = "okay";
+ };
+ };
+};
#if defined(CONFIG_SPL_MMC_SUPPORT)
/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
switch (spl_boot_device()) {
/* for MMC return either RAW or FAT mode */
--- /dev/null
+/*
+ * Copyright 2016 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+/* BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK \
+ .word 0xbabeface; \
+ .word _end - _start
+
+#endif /* __BOOT0_H */
}
ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
-#ifdef CONFIG_ARMV7_NONSEC
if (ret)
return ret;
+#ifdef CONFIG_ARMV7_NONSEC
ret = psci_update_dt(blob);
+ if (ret)
+ return ret;
#endif
- return ret;
+
+ return 0;
}
bool "Support corvus"
select CPU_ARM926EJS
select SUPPORT_SPL
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+ select DM_ETH
config TARGET_TAURUS
bool "Support taurus"
select CPU_ARM926EJS
select SUPPORT_SPL
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+ select DM_ETH
config TARGET_SMARTWEB
bool "Support smartweb"
select CPU_ARM926EJS
select SUPPORT_SPL
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+ select DM_ETH
config TARGET_VINCO
bool "Support VINCO"
#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30)
#elif defined(CONFIG_AT91SAM9263)
#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120)
-#elif defined(CONFIG_AT91SAM9G45)
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128)
#else
#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
#elif defined(CONFIG_AT91SAM9263)
#define AT91_MATRIX_MASTERS 9
#define AT91_MATRIX_SLAVES 7
-#elif defined(CONFIG_AT91SAM9G45)
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#define AT91_MATRIX_MASTERS 11
#define AT91_MATRIX_SLAVES 8
#else
u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
u32 mrcr; /* 0x100 Master Remap Control */
u32 reserve4[3];
-#if defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */
u32 womr; /* 0x1E4 Write Protect Mode */
u32 wpsr; /* 0x1E8 Write Protect Status */
/* Undefined Length Burst Type */
#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
- defined(CONFIG_AT91SAM9G45)
+ defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000
#define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001
#define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002
#define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003
#define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004
#endif
-#if defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005
#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006
#define AT91_MATRIX_MCFG_ULBT_128 0x00000007
#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000
/* Fixed Index of Default Master */
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) || \
+ defined(CONFIG_AT91SAM9M10G45)
#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18)
#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18)
#endif
/* Maximum Number of Allowed Cycles for a Burst */
-#if defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0)
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
defined(CONFIG_AT91SAM9263)
/* Master Remap Control Register */
#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
- defined(CONFIG_AT91SAM9G45)
+ defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_MRCR_RCB0 (1 << 0)
/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_MRCR_RCB1 (1 << 1)
#endif
-#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \
+ defined(CONFIG_AT91SAM9M10G45)
#define AT91_MATRIX_MRCR_RCB2 0x00000004
#define AT91_MATRIX_MRCR_RCB3 0x00000008
#define AT91_MATRIX_MRCR_RCB4 0x00000010
#define AT91_MATRIX_MRCR_RCB7 0x00000080
#define AT91_MATRIX_MRCR_RCB8 0x00000100
#endif
-#if defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#define AT91_MATRIX_MRCR_RCB9 0x00000200
#define AT91_MATRIX_MRCR_RCB10 0x00000400
#define AT91_MATRIX_MRCR_RCB11 0x00000800
#endif
/* TCM Configuration Register */
-#if defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
/* Size of ITCM enabled memory block */
#define AT91_MATRIX_TCMR_ITCM_0 0x00000000
#define AT91_MATRIX_TCMR_ITCM_32 0x00000040
#define AT91_MATRIX_TCMR_DTCM_64 0x00000070
#endif
-#if defined(CONFIG_AT91SAM9G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
/* Video Mode Configuration Register */
#define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000
#define AT91C_MATRIX_VDEC_SEL_ON 0x00000001
}
#endif
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
- switch (spl_boot_device()) {
+ switch (boot_device) {
#ifdef CONFIG_SYS_USE_MMC
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
preloader_console_init();
}
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
return MMCSD_MODE_RAW;
}
config SYS_MALLOC_F_LEN
default 0x1000
-source "board/hardkernel/odroid-c2/Kconfig"
+source "board/amlogic/odroid-c2/Kconfig"
endif
}
#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
return MMCSD_MODE_RAW;
}
return BOOT_DEVICE_MMC1;
}
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
return MMCSD_MODE_RAW;
}
}
#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
return MMCSD_MODE_FS;
}
/* No confirmation data available in SPL yet. Hardcode bootmode */
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
return MMCSD_MODE_RAW;
}
return mode;
}
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
struct mmc *mmc;
}
#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(void)
+u32 spl_boot_mode(const u32 boot_device)
{
return MMCSD_MODE_FS;
}
-if TARGET_KWB
+if TARGET_BRPPT1
config SYS_BOARD
- default "kwb"
+ default "brppt1"
config SYS_VENDOR
default "BuR"
default "am33xx"
config SYS_CONFIG_NAME
- default "kwb"
+ default "brppt1"
endif
--- /dev/null
+BRPPT1 BOARD
+M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S: Maintained
+F: board/BuR/brppt1/
+F: include/configs/brppt1.h
+F: configs/brppt1_mmc_defconfig
+F: configs/brppt1_nand_defconfig
+F: configs/brppt1_spi_defconfig
/*
* board.c
*
- * Board functions for B&R LEIT Board
+ * Board functions for B&R BRPPT1
*
* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
/*
* mux.c
*
- * Pinmux Setting for B&R LEIT Board(s)
+ * Pinmux Setting for B&R BRPPT1 Board(s)
*
* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
-if TARGET_TSERIES
+if TARGET_BRXRE1
config SYS_BOARD
- default "tseries"
+ default "brxre1"
config SYS_VENDOR
default "BuR"
default "am33xx"
config SYS_CONFIG_NAME
- default "tseries"
+ default "brxre1"
endif
--- /dev/null
+BRXRE1 BOARD
+M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S: Maintained
+F: board/BuR/brxre1/
+F: include/configs/brxre1.h
+F: configs/brxre1_defconfig
/*
* board.c
*
- * Board functions for B&R KWB Board
+ * Board functions for B&R BRXRE1 Board
*
* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
*/
u32 *const clk_domains[] = { 0 };
- u32 *const clk_modules_kwbspecific[] = {
+ u32 *const clk_modules_xre1specific[] = {
&cmwkup->wkup_adctscctrl,
&cmper->spi1clkctrl,
&cmper->dcan0clkctrl,
&cmper->lcdcclkstctrl,
0
};
- do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
+ do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
/* setup LCD-Pixel Clock */
writel(0x2, CM_DPLL + 0x34);
/* power-OFF LCD-Display */
+++ /dev/null
-KWB BOARD
-M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
-S: Maintained
-F: board/BuR/kwb/
-F: include/configs/kwb.h
-F: configs/kwb_defconfig
+++ /dev/null
-TSERIES BOARD
-M: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
-S: Maintained
-F: board/BuR/tseries/
-F: include/configs/tseries.h
-F: configs/tseries_mmc_defconfig
-F: configs/tseries_nand_defconfig
-F: configs/tseries_spi_defconfig
default "odroid-c2"
config SYS_VENDOR
- default "hardkernel"
+ default "amlogic"
config SYS_CONFIG_NAME
default "odroid-c2"
ODROID-C2
M: Beniamino Galvani <b.galvani@gmail.com>
S: Maintained
-F: board/hardkernel/odroid-c2/
+F: board/amlogic/odroid-c2/
F: include/configs/odroid-c2.h
F: configs/odroid-c2_defconfig
BCM11130 BOARD
-M: Steve Rae <srae@broadcom.com>
+M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcm28155_ap/
F: include/configs/bcm_ep_board.h
BCM11130_NAND BOARD
-M: Steve Rae <srae@broadcom.com>
+M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcm28155_ap/
F: include/configs/bcm_ep_board.h
BCM23550_W1D BOARD
-M: Steve Rae <srae@broadcom.com>
+M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcm23550_w1d/
F: include/configs/bcm23550_w1d.h
BCM28155_AP BOARD
-M: Tim Kryger <tim.kryger@linaro.org>
+M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcm28155_ap/
F: include/configs/bcm28155_ap.h
BCM28155_W1D BOARD
-M: Steve Rae <srae@broadcom.com>
+M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcm28155_ap/
F: include/configs/bcm28155_ap.h
BCM911360_ENTPHN-NS BOARD
-M: Steve Rae <srae@broadcom.com>
+M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcmcygnus/
F: include/configs/bcm_ep_board.h
BCM911360_ENTPHN BOARD
-M: Steve Rae <srae@broadcom.com>
+M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcmcygnus/
F: include/configs/bcm_ep_board.h
BCM911360K BOARD
-M: Steve Rae <srae@broadcom.com>
+M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcmcygnus/
F: include/configs/bcm_ep_board.h
BCM958300K-NS BOARD
-M: Steve Rae <srae@broadcom.com>
+M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcmcygnus/
F: include/configs/bcm_ep_board.h
BCM958300K BOARD
-M: Steve Rae <srae@broadcom.com>
+M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcmcygnus/
F: include/configs/bcm_ep_board.h
BCM958305K BOARD
-M: Steve Rae <srae@broadcom.com>
+M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcmcygnus/
F: include/configs/bcm_ep_board.h
BCM958622HR BOARD
-M: Steve Rae <srae@broadcom.com>
+M: Steve Rae <steve.rae@raedomain.com>
S: Maintained
F: board/broadcom/bcmnsp/
F: include/configs/bcm_ep_board.h
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
+#include <dm.h>
#include <asm/io.h>
#include <asm/arch/at91sam9g45_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_serial.h>
#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
#include <asm/arch/clk.h>
-#include <lcd.h>
-#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
+#ifndef CONFIG_DM_ETH
#include <netdev.h>
+#endif
#include <spi.h>
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
DECLARE_GLOBAL_DATA_PTR;
+static void corvus_request_gpio(void)
+{
+ gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
+ gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+ gpio_request(AT91_PIN_PD7, "d0");
+ gpio_request(AT91_PIN_PD8, "d1");
+ gpio_request(AT91_PIN_PA12, "d2");
+ gpio_request(AT91_PIN_PA13, "d3");
+ gpio_request(AT91_PIN_PA15, "d4");
+ gpio_request(AT91_PIN_PB7, "recovery button");
+ gpio_request(AT91_PIN_PD1, "USB0");
+ gpio_request(AT91_PIN_PD3, "USB1");
+ gpio_request(AT91_PIN_PB18, "SPICS1");
+ gpio_request(AT91_PIN_PB3, "SPICS0");
+ gpio_request(CONFIG_RED_LED, "red led");
+ gpio_request(CONFIG_GREEN_LED, "green led");
+}
+
static void corvus_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
void spl_board_init(void)
{
+ corvus_request_gpio();
/*
* For on the sam9m10g45ek board, the chip wm9711 stay in the test
* mode, so it need do some action to exit mode.
int board_early_init_f(void)
{
at91_seriald_hw_init();
+ corvus_request_gpio();
return 0;
}
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ /* we have to request the gpios again after relocation */
+ corvus_request_gpio();
#ifdef CONFIG_CMD_NAND
corvus_nand_hw_init();
#endif
return 0;
}
+#ifndef CONFIG_DM_ETH
int board_eth_init(bd_t *bis)
{
int rc = 0;
#endif
return rc;
}
+#endif
/* SPI chip select control */
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
break;
}
}
+
+static struct atmel_serial_platdata at91sam9260_serial_plat = {
+ .base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DEVICE(at91sam9260_serial) = {
+ .name = "serial_atmel",
+ .platdata = &at91sam9260_serial_plat,
+};
*/
#include <common.h>
+#include <dm.h>
#include <asm/io.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_serial.h>
#include <asm/arch/at91_spi.h>
#include <spi.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
#include <watchdog.h>
-#ifdef CONFIG_MACB
# include <net.h>
+#ifndef CONFIG_DM_ETH
# include <netdev.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
+static void smartweb_request_gpio(void)
+{
+ gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
+ gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+ gpio_request(AT91_PIN_PA26, "ena PHY");
+}
+
static void smartweb_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
-#ifdef CONFIG_MACB
static void smartweb_macb_hw_init(void)
{
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
/* Initialize EMAC=MACB hardware */
at91_macb_hw_init();
}
-#endif /* CONFIG_MACB */
#ifdef CONFIG_USB_GADGET_AT91
#include <linux/usb/at91_udc.h>
{
/* enable this here, as we have SPL without serial support */
at91_seriald_hw_init();
+ smartweb_request_gpio();
return 0;
}
int board_init(void)
{
+ smartweb_request_gpio();
/* power LED red */
at91_set_gpio_output(AT91_PIN_PC6, 0);
at91_set_gpio_output(AT91_PIN_PC7, 1);
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
smartweb_nand_hw_init();
-#ifdef CONFIG_MACB
smartweb_macb_hw_init();
-#endif
return 0;
}
return 0;
}
+#ifndef CONFIG_DM_ETH
#ifdef CONFIG_MACB
int board_eth_init(bd_t *bis)
{
return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
}
#endif /* CONFIG_MACB */
+#endif
#if defined(CONFIG_SPL_BUILD)
#include <spl.h>
&mat->scfg[3]);
}
-void spl_board_init(void)
+void at91_spl_board_init(void)
{
+ smartweb_request_gpio();
/* power LED orange */
at91_set_gpio_output(AT91_PIN_PC6, 1);
at91_set_gpio_output(AT91_PIN_PC7, 1);
sdramc_initialize(ATMEL_BASE_CS1, &setting);
}
#endif
+
+static struct atmel_serial_platdata at91sam9260_serial_plat = {
+ .base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DEVICE(at91sam9260_serial) = {
+ .name = "serial_atmel",
+ .platdata = &at91sam9260_serial_plat,
+};
#include <command.h>
#include <common.h>
+#include <dm.h>
#include <asm/io.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91sam9_sdramc.h>
+#include <asm/arch/atmel_serial.h>
#include <asm/arch/clk.h>
+#include <asm/gpio.h>
#include <linux/mtd/nand.h>
#include <atmel_mci.h>
#include <asm/arch/at91_spi.h>
#include <spi.h>
#include <net.h>
+#ifndef CONFIG_DM_ETH
#include <netdev.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
+static void taurus_request_gpio(void)
+{
+ gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
+ gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
+ gpio_request(AT91_PIN_PA25, "ena PHY");
+}
+
static void taurus_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
at91_periph_clk_enable(ATMEL_ID_PIOC);
at91_seriald_hw_init();
+ taurus_request_gpio();
return 0;
}
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ taurus_request_gpio();
#ifdef CONFIG_CMD_NAND
taurus_nand_hw_init();
#endif
return 0;
}
+#ifndef CONFIG_DM_ETH
int board_eth_init(bd_t *bis)
{
int rc = 0;
#endif
return rc;
}
+#endif
#if !defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_BOARD_AXM)
);
#endif
#endif
+
+static struct atmel_serial_platdata at91sam9260_serial_plat = {
+ .base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DEVICE(at91sam9260_serial) = {
+ .name = "serial_atmel",
+ .platdata = &at91sam9260_serial_plat,
+};
In practice this is seen as a NOR flash module connected to the
"memory cape" for the BeagleBone family.
-config NOR_BOOT
- bool "Support for booting from NOR flash"
- depends on NOR
- help
- Enabling this will make a U-Boot binary that is capable of being
- booted via NOR. In this case we will enable certain pinmux early
- as the ROM only partially sets up pinmux. We also default to using
- NOR for environment.
-
source "board/ti/common/Kconfig"
endif
* only HUSH can understand them.
*/
-#if !defined(CONFIG_SYS_HUSH_PARSER)
-#error CONFIG_CMD_HD44760 requires CONFIG_SYS_HUSH_PARSER
+#if !defined(CONFIG_HUSH_PARSER)
+#error CONFIG_CMD_HD44760 requires CONFIG_HUSH_PARSER
#endif
static int do_hd44780(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
config HUSH_PARSER
bool "Use hush shell"
- select SYS_HUSH_PARSER
depends on CMDLINE
help
This option enables the "hush" shell (from Busybox) as command line
If disabled, you get the old, much simpler behaviour with a somewhat
smaller memory footprint.
-config SYS_HUSH_PARSER
- bool
- help
- Backward compatibility.
-
config SYS_PROMPT
string "Shell prompt"
default "=> "
obj-$(CONFIG_CMD_EEPROM) += eeprom.o
obj-$(CONFIG_EFI_STUB) += efi.o
obj-$(CONFIG_CMD_ELF) += elf.o
-obj-$(CONFIG_SYS_HUSH_PARSER) += exit.o
+obj-$(CONFIG_HUSH_PARSER) += exit.o
obj-$(CONFIG_CMD_EXT4) += ext4.o
obj-$(CONFIG_CMD_EXT2) += ext2.o
obj-$(CONFIG_CMD_FAT) += fat.o
obj-$(CONFIG_CMD_TERMINAL) += terminal.o
obj-$(CONFIG_CMD_TIME) += time.o
obj-$(CONFIG_CMD_TRACE) += trace.o
-obj-$(CONFIG_SYS_HUSH_PARSER) += test.o
+obj-$(CONFIG_HUSH_PARSER) += test.o
obj-$(CONFIG_CMD_TPM) += tpm.o
obj-$(CONFIG_CMD_TPM_TEST) += tpm_test.o
obj-$(CONFIG_CMD_TSI148) += tsi148.o
U_BOOT_CMD(
bootefi, 3, 0, do_bootefi,
- "Boots an EFI payload from memory\n",
+ "Boots an EFI payload from memory",
bootefi_help_text
);
puts("OK\n");
return 0;
#endif
+#if defined(CONFIG_ANDROID_BOOT_IMAGE)
+ case IMAGE_FORMAT_ANDROID:
+ puts(" Android image found\n");
+ android_print_contents(hdr);
+ return 0;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
puts(" FIT image found\n");
endmenu
+menu "Boot media"
+
+config NOR_BOOT
+ bool "Support for booting from NOR flash"
+ depends on NOR
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via NOR. In this case we will enable certain pinmux early
+ as the ROM only partially sets up pinmux. We also default to using
+ NOR for environment.
+
+config NAND_BOOT
+ bool "Support for booting from NAND flash"
+ default n
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via NAND flash. This is not a must, some SoCs need this,
+ somes not.
+
+config ONENAND_BOOT
+ bool "Support for booting from ONENAND"
+ default n
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via ONENAND. This is not a must, some SoCs need this,
+ somes not.
+
+config QSPI_BOOT
+ bool "Support for booting from QSPI flash"
+ default n
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via QSPI flash. This is not a must, some SoCs need this,
+ somes not.
+
+config SATA_BOOT
+ bool "Support for booting from SATA"
+ default n
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via SATA. This is not a must, some SoCs need this,
+ somes not.
+
+config SD_BOOT
+ bool "Support for booting from SD/EMMC"
+ default n
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via SD/EMMC. This is not a must, some SoCs need this,
+ somes not.
+
+config SPI_BOOT
+ bool "Support for booting from SPI flash"
+ default n
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via SPI flash. This is not a must, some SoCs need this,
+ somes not.
+
+endmenu
+
config BOOTDELAY
int "delay in seconds before automatically booting"
default 2
obj-y += main.o
obj-y += exports.o
obj-y += hash.o
-ifdef CONFIG_SYS_HUSH_PARSER
-obj-y += cli_hush.o
-endif
-
+obj-$(CONFIG_HUSH_PARSER) += cli_hush.o
obj-$(CONFIG_AUTOBOOT) += autoboot.o
# This option is not just y/n - it can have a numeric value
*/
int run_command(const char *cmd, int flag)
{
-#ifndef CONFIG_SYS_HUSH_PARSER
+#ifndef CONFIG_HUSH_PARSER
/*
* cli_run_command can return 0 or 1 for success, so clean up
* its result.
*/
int run_command_repeatable(const char *cmd, int flag)
{
-#ifndef CONFIG_SYS_HUSH_PARSER
+#ifndef CONFIG_HUSH_PARSER
return cli_simple_run_command(cmd, flag);
#else
/*
if (len == -1) {
len = strlen(cmd);
-#ifdef CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_HUSH_PARSER
/* hush will never change our string */
need_buff = 0;
#else
memcpy(buff, cmd, len);
buff[len] = '\0';
}
-#ifdef CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_HUSH_PARSER
rcode = parse_string_outer(buff, FLAG_PARSE_SEMICOLON);
#else
/*
void cli_loop(void)
{
-#ifdef CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_HUSH_PARSER
parse_file_outer();
/* This point is never reached */
for (;;);
cli_simple_loop();
#else
printf("## U-Boot command line is disabled. Please enable CONFIG_CMDLINE\n");
-#endif /*CONFIG_SYS_HUSH_PARSER*/
+#endif /*CONFIG_HUSH_PARSER*/
}
void cli_init(void)
{
-#ifdef CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_HUSH_PARSER
u_boot_hush_start();
#endif
#include <environment.h>
#include <linux/stddef.h>
#include <malloc.h>
+#include <memalign.h>
#include <search.h>
#include <errno.h>
#include <ext4fs.h>
int saveenv(void)
{
env_t env_new;
- block_dev_desc_t *dev_desc = NULL;
+ struct blk_desc *dev_desc = NULL;
disk_partition_t info;
int dev, part;
int err;
if (err)
return err;
- part = get_device_and_partition(EXT4_ENV_INTERFACE,
+ part = blk_get_device_part_str(EXT4_ENV_INTERFACE,
EXT4_ENV_DEVICE_AND_PART,
&dev_desc, &info, 1);
if (part < 0)
return 1;
- dev = dev_desc->dev;
+ dev = dev_desc->devnum;
ext4fs_set_blk_dev(dev_desc, &info);
if (!ext4fs_mount(info.size)) {
void env_relocate_spec(void)
{
ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
- block_dev_desc_t *dev_desc = NULL;
+ struct blk_desc *dev_desc = NULL;
disk_partition_t info;
int dev, part;
int err;
+ loff_t off;
- part = get_device_and_partition(EXT4_ENV_INTERFACE,
+ part = blk_get_device_part_str(EXT4_ENV_INTERFACE,
EXT4_ENV_DEVICE_AND_PART,
&dev_desc, &info, 1);
if (part < 0)
goto err_env_relocate;
- dev = dev_desc->dev;
+ dev = dev_desc->devnum;
ext4fs_set_blk_dev(dev_desc, &info);
if (!ext4fs_mount(info.size)) {
goto err_env_relocate;
}
- err = ext4_read_file(EXT4_ENV_FILE, buf, 0, CONFIG_ENV_SIZE);
+ err = ext4_read_file(EXT4_ENV_FILE, buf, 0, CONFIG_ENV_SIZE, &off);
ext4fs_close();
if (err == -1) {
#include <config.h>
#include <common.h>
#include <blk.h>
-#include <errno.h>
#include <fastboot.h>
#include <fb_mmc.h>
#include <image-sparse.h>
#include <part.h>
-#include <sparse_format.h>
#include <mmc.h>
#include <div64.h>
#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME
#endif
-static char *response_str;
-
struct fb_mmc_sparse {
struct blk_desc *dev_desc;
};
return ret;
}
-
-static int fb_mmc_sparse_write(struct sparse_storage *storage,
- void *priv,
- unsigned int offset,
- unsigned int size,
- char *data)
+static lbaint_t fb_mmc_sparse_write(struct sparse_storage *info,
+ lbaint_t blk, lbaint_t blkcnt, const void *buffer)
{
- struct fb_mmc_sparse *sparse = priv;
+ struct fb_mmc_sparse *sparse = info->priv;
struct blk_desc *dev_desc = sparse->dev_desc;
- int ret;
- ret = blk_dwrite(dev_desc, offset, size, data);
- if (!ret)
- return -EIO;
+ return blk_dwrite(dev_desc, blk, blkcnt, buffer);
+}
- return ret;
+static lbaint_t fb_mmc_sparse_reserve(struct sparse_storage *info,
+ lbaint_t blk, lbaint_t blkcnt)
+{
+ return blkcnt;
}
static void write_raw_image(struct blk_desc *dev_desc, disk_partition_t *info,
if (blkcnt > info->size) {
error("too large for partition: '%s'\n", part_name);
- fastboot_fail(response_str, "too large for partition");
+ fastboot_fail("too large for partition");
return;
}
blks = blk_dwrite(dev_desc, info->start, blkcnt, buffer);
if (blks != blkcnt) {
error("failed writing to device %d\n", dev_desc->devnum);
- fastboot_fail(response_str, "failed writing to device");
+ fastboot_fail("failed writing to device");
return;
}
printf("........ wrote " LBAFU " bytes to '%s'\n", blkcnt * info->blksz,
part_name);
- fastboot_okay(response_str, "");
+ fastboot_okay("");
}
-void fb_mmc_flash_write(const char *cmd, unsigned int session_id,
- void *download_buffer, unsigned int download_bytes,
- char *response)
+void fb_mmc_flash_write(const char *cmd, void *download_buffer,
+ unsigned int download_bytes)
{
struct blk_desc *dev_desc;
disk_partition_t info;
- /* initialize the response buffer */
- response_str = response;
-
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
error("invalid mmc device\n");
- fastboot_fail(response_str, "invalid mmc device");
+ fastboot_fail("invalid mmc device");
return;
}
if (is_valid_gpt_buf(dev_desc, download_buffer)) {
printf("%s: invalid GPT - refusing to write to flash\n",
__func__);
- fastboot_fail(response_str, "invalid GPT partition");
+ fastboot_fail("invalid GPT partition");
return;
}
if (write_mbr_and_gpt_partitions(dev_desc, download_buffer)) {
printf("%s: writing GPT partitions failed\n", __func__);
- fastboot_fail(response_str,
+ fastboot_fail(
"writing GPT partitions failed");
return;
}
printf("........ success\n");
- fastboot_okay(response_str, "");
+ fastboot_okay("");
return;
} else if (part_get_info_efi_by_name_or_alias(dev_desc, cmd, &info)) {
error("cannot find partition: '%s'\n", cmd);
- fastboot_fail(response_str, "cannot find partition");
+ fastboot_fail("cannot find partition");
return;
}
if (is_sparse_image(download_buffer)) {
struct fb_mmc_sparse sparse_priv;
- sparse_storage_t sparse;
+ struct sparse_storage sparse;
sparse_priv.dev_desc = dev_desc;
- sparse.block_sz = info.blksz;
+ sparse.blksz = info.blksz;
sparse.start = info.start;
sparse.size = info.size;
- sparse.name = cmd;
sparse.write = fb_mmc_sparse_write;
+ sparse.reserve = fb_mmc_sparse_reserve;
printf("Flashing sparse image at offset " LBAFU "\n",
- info.start);
+ sparse.start);
- store_sparse_image(&sparse, &sparse_priv, session_id,
- download_buffer);
+ sparse.priv = &sparse_priv;
+ write_sparse_image(&sparse, cmd, download_buffer,
+ download_bytes);
} else {
write_raw_image(dev_desc, &info, cmd, download_buffer,
download_bytes);
}
-
- fastboot_okay(response_str, "");
}
-void fb_mmc_erase(const char *cmd, char *response)
+void fb_mmc_erase(const char *cmd)
{
int ret;
struct blk_desc *dev_desc;
if (mmc == NULL) {
error("invalid mmc device");
- fastboot_fail(response_str, "invalid mmc device");
+ fastboot_fail("invalid mmc device");
return;
}
- /* initialize the response buffer */
- response_str = response;
-
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
error("invalid mmc device");
- fastboot_fail(response_str, "invalid mmc device");
+ fastboot_fail("invalid mmc device");
return;
}
ret = part_get_info_efi_by_name_or_alias(dev_desc, cmd, &info);
if (ret) {
error("cannot find partition: '%s'", cmd);
- fastboot_fail(response_str, "cannot find partition");
+ fastboot_fail("cannot find partition");
return;
}
blks = dev_desc->block_erase(dev_desc, blks_start, blks_size);
if (blks != blks_size) {
error("failed erasing from device %d", dev_desc->devnum);
- fastboot_fail(response_str, "failed erasing from device");
+ fastboot_fail("failed erasing from device");
return;
}
printf("........ erased " LBAFU " bytes from '%s'\n",
blks_size * info.blksz, cmd);
- fastboot_okay(response_str, "");
+ fastboot_okay("");
}
#include <fastboot.h>
#include <image-sparse.h>
-#include <sparse_format.h>
#include <linux/mtd/mtd.h>
#include <jffs2/jffs2.h>
#include <nand.h>
-static char *response_str;
-
struct fb_nand_sparse {
- struct mtd_info *nand;
+ struct mtd_info *mtd;
struct part_info *part;
};
return 0;
}
-static int fb_nand_lookup(const char *partname, char *response,
+static int fb_nand_lookup(const char *partname,
struct mtd_info **mtd,
struct part_info **part)
{
ret = mtdparts_init();
if (ret) {
error("Cannot initialize MTD partitions\n");
- fastboot_fail(response_str, "cannot init mtdparts");
+ fastboot_fail("cannot init mtdparts");
return ret;
}
ret = find_dev_and_part(partname, &dev, &pnum, part);
if (ret) {
error("cannot find partition: '%s'", partname);
- fastboot_fail(response_str, "cannot find partition");
+ fastboot_fail("cannot find partition");
return ret;
}
if (dev->id->type != MTD_DEV_TYPE_NAND) {
error("partition '%s' is not stored on a NAND device",
partname);
- fastboot_fail(response_str, "not a NAND device");
+ fastboot_fail("not a NAND device");
return -EINVAL;
}
buffer, flags);
}
-static int fb_nand_sparse_write(struct sparse_storage *storage,
- void *priv,
- unsigned int offset,
- unsigned int size,
- char *data)
+static lbaint_t fb_nand_sparse_write(struct sparse_storage *info,
+ lbaint_t blk, lbaint_t blkcnt, const void *buffer)
{
- struct fb_nand_sparse *sparse = priv;
+ struct fb_nand_sparse *sparse = info->priv;
size_t written;
int ret;
- ret = _fb_nand_write(sparse->nand, sparse->part, data,
- offset * storage->block_sz,
- size * storage->block_sz, &written);
+ ret = _fb_nand_write(sparse->mtd, sparse->part, (void *)buffer,
+ blk * info->blksz,
+ blkcnt * info->blksz, &written);
if (ret < 0) {
printf("Failed to write sparse chunk\n");
return ret;
}
- return written / storage->block_sz;
+/* TODO - verify that the value "written" includes the "bad-blocks" ... */
+
+ /*
+ * the return value must be 'blkcnt' ("good-blocks") plus the
+ * number of "bad-blocks" encountered within this space...
+ */
+ return written / info->blksz;
+}
+
+static lbaint_t fb_nand_sparse_reserve(struct sparse_storage *info,
+ lbaint_t blk, lbaint_t blkcnt)
+{
+ int bad_blocks = 0;
+
+/*
+ * TODO - implement a function to determine the total number
+ * of blocks which must be used in order to reserve the specified
+ * number ("blkcnt") of "good-blocks", starting at "blk"...
+ * ( possibly something like the "check_skip_len()" function )
+ */
+
+ /*
+ * the return value must be 'blkcnt' ("good-blocks") plus the
+ * number of "bad-blocks" encountered within this space...
+ */
+ return blkcnt + bad_blocks;
}
-void fb_nand_flash_write(const char *partname, unsigned int session_id,
- void *download_buffer, unsigned int download_bytes,
- char *response)
+void fb_nand_flash_write(const char *cmd, void *download_buffer,
+ unsigned int download_bytes)
{
struct part_info *part;
struct mtd_info *mtd = NULL;
int ret;
- /* initialize the response buffer */
- response_str = response;
-
- ret = fb_nand_lookup(partname, response, &mtd, &part);
+ ret = fb_nand_lookup(cmd, &mtd, &part);
if (ret) {
error("invalid NAND device");
- fastboot_fail(response_str, "invalid NAND device");
+ fastboot_fail("invalid NAND device");
return;
}
if (is_sparse_image(download_buffer)) {
struct fb_nand_sparse sparse_priv;
- sparse_storage_t sparse;
+ struct sparse_storage sparse;
- sparse_priv.nand = mtd;
+ sparse_priv.mtd = mtd;
sparse_priv.part = part;
- sparse.block_sz = mtd->writesize;
- sparse.start = part->offset / sparse.block_sz;
- sparse.size = part->size / sparse.block_sz;
- sparse.name = part->name;
+ sparse.blksz = mtd->writesize;
+ sparse.start = part->offset / sparse.blksz;
+ sparse.size = part->size / sparse.blksz;
sparse.write = fb_nand_sparse_write;
+ sparse.reserve = fb_nand_sparse_reserve;
+
+ printf("Flashing sparse image at offset " LBAFU "\n",
+ sparse.start);
- ret = store_sparse_image(&sparse, &sparse_priv, session_id,
- download_buffer);
+ sparse.priv = &sparse_priv;
+ write_sparse_image(&sparse, cmd, download_buffer,
+ download_bytes);
} else {
printf("Flashing raw image at offset 0x%llx\n",
part->offset);
}
if (ret) {
- fastboot_fail(response_str, "error writing the image");
+ fastboot_fail("error writing the image");
return;
}
- fastboot_okay(response_str, "");
+ fastboot_okay("");
}
-void fb_nand_erase(const char *partname, char *response)
+void fb_nand_erase(const char *cmd)
{
struct part_info *part;
struct mtd_info *mtd = NULL;
int ret;
- /* initialize the response buffer */
- response_str = response;
-
- ret = fb_nand_lookup(partname, response, &mtd, &part);
+ ret = fb_nand_lookup(cmd, &mtd, &part);
if (ret) {
error("invalid NAND device");
- fastboot_fail(response_str, "invalid NAND device");
+ fastboot_fail("invalid NAND device");
return;
}
ret = _fb_nand_erase(mtd, part);
if (ret) {
error("failed erasing from device %s", mtd->name);
- fastboot_fail(response_str, "failed erasing from device");
+ fastboot_fail("failed erasing from device");
return;
}
- fastboot_okay(response_str, "");
+ fastboot_okay("");
}
*rd_len = hdr->ramdisk_size;
return 0;
}
+
+#if !defined(CONFIG_SPL_BUILD)
+/**
+ * android_print_contents - prints out the contents of the Android format image
+ * @hdr: pointer to the Android format image header
+ *
+ * android_print_contents() formats a multi line Android image contents
+ * description.
+ * The routine prints out Android image properties
+ *
+ * returns:
+ * no returned results
+ */
+void android_print_contents(const struct andr_img_hdr *hdr)
+{
+ const char * const p = IMAGE_INDENT_STRING;
+
+ printf("%skernel size: %x\n", p, hdr->kernel_size);
+ printf("%skernel address: %x\n", p, hdr->kernel_addr);
+ printf("%sramdisk size: %x\n", p, hdr->ramdisk_size);
+ printf("%sramdisk addrress: %x\n", p, hdr->ramdisk_addr);
+ printf("%ssecond size: %x\n", p, hdr->second_size);
+ printf("%ssecond address: %x\n", p, hdr->second_addr);
+ printf("%stags address: %x\n", p, hdr->tags_addr);
+ printf("%spage size: %x\n", p, hdr->page_size);
+ printf("%sname: %s\n", p, hdr->name);
+ printf("%scmdline: %s\n", p, hdr->cmdline);
+}
+#endif
#include <config.h>
#include <common.h>
-#include <div64.h>
-#include <errno.h>
#include <image-sparse.h>
+#include <div64.h>
#include <malloc.h>
#include <part.h>
#include <sparse_format.h>
+#include <fastboot.h>
#include <linux/math64.h>
-typedef struct sparse_buffer {
- void *data;
- u32 length;
- u32 repeat;
- u16 type;
-} sparse_buffer_t;
-
-static uint32_t last_offset;
-
-static unsigned int sparse_get_chunk_data_size(sparse_header_t *sparse,
- chunk_header_t *chunk)
-{
- return chunk->total_sz - sparse->chunk_hdr_sz;
-}
+#ifndef CONFIG_FASTBOOT_FLASH_FILLBUF_SIZE
+#define CONFIG_FASTBOOT_FLASH_FILLBUF_SIZE (1024 * 512)
+#endif
-static unsigned int sparse_block_size_to_storage(unsigned int size,
- sparse_storage_t *storage,
- sparse_header_t *sparse)
+void write_sparse_image(
+ struct sparse_storage *info, const char *part_name,
+ void *data, unsigned sz)
{
- return (unsigned int)lldiv((uint64_t)size * sparse->blk_sz,
- storage->block_sz);
-}
+ lbaint_t blk;
+ lbaint_t blkcnt;
+ lbaint_t blks;
+ uint32_t bytes_written = 0;
+ unsigned int chunk;
+ unsigned int offset;
+ unsigned int chunk_data_sz;
+ uint32_t *fill_buf = NULL;
+ uint32_t fill_val;
+ sparse_header_t *sparse_header;
+ chunk_header_t *chunk_header;
+ uint32_t total_blocks = 0;
+ int fill_buf_num_blks;
+ int i;
+ int j;
-static bool sparse_chunk_has_buffer(chunk_header_t *chunk)
-{
- switch (chunk->chunk_type) {
- case CHUNK_TYPE_RAW:
- case CHUNK_TYPE_FILL:
- return true;
+ fill_buf_num_blks = CONFIG_FASTBOOT_FLASH_FILLBUF_SIZE / info->blksz;
- default:
- return false;
- }
-}
-
-static sparse_header_t *sparse_parse_header(void **data)
-{
/* Read and skip over sparse image header */
- sparse_header_t *sparse_header = (sparse_header_t *) *data;
+ sparse_header = (sparse_header_t *)data;
- *data += sparse_header->file_hdr_sz;
+ data += sparse_header->file_hdr_sz;
+ if (sparse_header->file_hdr_sz > sizeof(sparse_header_t)) {
+ /*
+ * Skip the remaining bytes in a header that is longer than
+ * we expected.
+ */
+ data += (sparse_header->file_hdr_sz - sizeof(sparse_header_t));
+ }
debug("=== Sparse Image Header ===\n");
debug("magic: 0x%x\n", sparse_header->magic);
debug("total_blks: %d\n", sparse_header->total_blks);
debug("total_chunks: %d\n", sparse_header->total_chunks);
- return sparse_header;
-}
-
-static int sparse_parse_fill_chunk(sparse_header_t *sparse,
- chunk_header_t *chunk)
-{
- unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk);
-
- if (chunk_data_sz != sizeof(uint32_t))
- return -EINVAL;
-
- return 0;
-}
-
-static int sparse_parse_raw_chunk(sparse_header_t *sparse,
- chunk_header_t *chunk)
-{
- unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk);
-
- /* Check if the data size is a multiple of the main block size */
- if (chunk_data_sz % sparse->blk_sz)
- return -EINVAL;
-
- /* Check that the chunk size is consistent */
- if ((chunk_data_sz / sparse->blk_sz) != chunk->chunk_sz)
- return -EINVAL;
-
- return 0;
-}
-
-static chunk_header_t *sparse_parse_chunk(sparse_header_t *sparse,
- void **image)
-{
- chunk_header_t *chunk = (chunk_header_t *) *image;
- int ret;
-
- debug("=== Chunk Header ===\n");
- debug("chunk_type: 0x%x\n", chunk->chunk_type);
- debug("chunk_data_sz: 0x%x\n", chunk->chunk_sz);
- debug("total_size: 0x%x\n", chunk->total_sz);
-
- switch (chunk->chunk_type) {
- case CHUNK_TYPE_RAW:
- ret = sparse_parse_raw_chunk(sparse, chunk);
- if (ret)
- return NULL;
- break;
-
- case CHUNK_TYPE_FILL:
- ret = sparse_parse_fill_chunk(sparse, chunk);
- if (ret)
- return NULL;
- break;
-
- case CHUNK_TYPE_DONT_CARE:
- case CHUNK_TYPE_CRC32:
- debug("Ignoring chunk\n");
- break;
-
- default:
- printf("%s: Unknown chunk type: %x\n", __func__,
- chunk->chunk_type);
- return NULL;
- }
-
- *image += sparse->chunk_hdr_sz;
-
- return chunk;
-}
-
-static int sparse_get_fill_buffer(sparse_header_t *sparse,
- chunk_header_t *chunk,
- sparse_buffer_t *buffer,
- unsigned int blk_sz,
- void *data)
-{
- int i;
-
- buffer->type = CHUNK_TYPE_FILL;
-
- /*
- * We create a buffer of one block, and ask it to be
- * repeated as many times as needed.
- */
- buffer->length = blk_sz;
- buffer->repeat = (chunk->chunk_sz * sparse->blk_sz) / blk_sz;
-
- buffer->data = memalign(ARCH_DMA_MINALIGN,
- ROUNDUP(blk_sz,
- ARCH_DMA_MINALIGN));
- if (!buffer->data)
- return -ENOMEM;
-
- for (i = 0; i < (buffer->length / sizeof(uint32_t)); i++)
- ((uint32_t *)buffer->data)[i] = *(uint32_t *)(data);
-
- return 0;
-}
-
-static int sparse_get_raw_buffer(sparse_header_t *sparse,
- chunk_header_t *chunk,
- sparse_buffer_t *buffer,
- unsigned int blk_sz,
- void *data)
-{
- unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk);
-
- buffer->type = CHUNK_TYPE_RAW;
- buffer->length = chunk_data_sz;
- buffer->data = data;
- buffer->repeat = 1;
-
- return 0;
-}
-
-static sparse_buffer_t *sparse_get_data_buffer(sparse_header_t *sparse,
- chunk_header_t *chunk,
- unsigned int blk_sz,
- void **image)
-{
- unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk);
- sparse_buffer_t *buffer;
- void *data = *image;
- int ret;
-
- *image += chunk_data_sz;
-
- if (!sparse_chunk_has_buffer(chunk))
- return NULL;
-
- buffer = calloc(sizeof(sparse_buffer_t), 1);
- if (!buffer)
- return NULL;
-
- switch (chunk->chunk_type) {
- case CHUNK_TYPE_RAW:
- ret = sparse_get_raw_buffer(sparse, chunk, buffer, blk_sz,
- data);
- if (ret)
- return NULL;
- break;
-
- case CHUNK_TYPE_FILL:
- ret = sparse_get_fill_buffer(sparse, chunk, buffer, blk_sz,
- data);
- if (ret)
- return NULL;
- break;
-
- default:
- return NULL;
- }
-
- debug("=== Buffer ===\n");
- debug("length: 0x%x\n", buffer->length);
- debug("repeat: 0x%x\n", buffer->repeat);
- debug("type: 0x%x\n", buffer->type);
- debug("data: 0x%p\n", buffer->data);
-
- return buffer;
-}
-
-static void sparse_put_data_buffer(sparse_buffer_t *buffer)
-{
- if (buffer->type == CHUNK_TYPE_FILL)
- free(buffer->data);
-
- free(buffer);
-}
-
-int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
- unsigned int session_id, void *data)
-{
- unsigned int chunk, offset;
- sparse_header_t *sparse_header;
- chunk_header_t *chunk_header;
- sparse_buffer_t *buffer;
- uint32_t start;
- uint32_t total_blocks = 0;
- int i;
-
- debug("=== Storage ===\n");
- debug("name: %s\n", storage->name);
- debug("block_size: 0x%x\n", storage->block_sz);
- debug("start: 0x%x\n", storage->start);
- debug("size: 0x%x\n", storage->size);
- debug("write: 0x%p\n", storage->write);
- debug("priv: 0x%p\n", storage_priv);
-
- sparse_header = sparse_parse_header(&data);
- if (!sparse_header) {
- printf("sparse header issue\n");
- return -EINVAL;
- }
-
/*
* Verify that the sparse block size is a multiple of our
* storage backend block size
*/
- div_u64_rem(sparse_header->blk_sz, storage->block_sz, &offset);
+ div_u64_rem(sparse_header->blk_sz, info->blksz, &offset);
if (offset) {
printf("%s: Sparse image block size issue [%u]\n",
__func__, sparse_header->blk_sz);
- return -EINVAL;
+ fastboot_fail("sparse image block size issue");
+ return;
}
- /*
- * If it's a new flashing session, start at the beginning of
- * the partition. If not, then simply resume where we were.
- */
- if (session_id > 0)
- start = last_offset;
- else
- start = storage->start;
-
- printf("Flashing sparse image on partition %s at offset 0x%x (ID: %d)\n",
- storage->name, start * storage->block_sz, session_id);
+ puts("Flashing Sparse Image\n");
/* Start processing chunks */
+ blk = info->start;
for (chunk = 0; chunk < sparse_header->total_chunks; chunk++) {
- uint32_t blkcnt;
-
- chunk_header = sparse_parse_chunk(sparse_header, &data);
- if (!chunk_header) {
- printf("Unknown chunk type");
- return -EINVAL;
+ /* Read and skip over chunk header */
+ chunk_header = (chunk_header_t *)data;
+ data += sizeof(chunk_header_t);
+
+ if (chunk_header->chunk_type != CHUNK_TYPE_RAW) {
+ debug("=== Chunk Header ===\n");
+ debug("chunk_type: 0x%x\n", chunk_header->chunk_type);
+ debug("chunk_data_sz: 0x%x\n", chunk_header->chunk_sz);
+ debug("total_size: 0x%x\n", chunk_header->total_sz);
}
- /*
- * If we have a DONT_CARE type, just skip the blocks
- * and go on parsing the rest of the chunks
- */
- if (chunk_header->chunk_type == CHUNK_TYPE_DONT_CARE) {
- blkcnt = sparse_block_size_to_storage(chunk_header->chunk_sz,
- storage,
- sparse_header);
-#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
- total_blocks += blkcnt;
-#endif
- continue;
+ if (sparse_header->chunk_hdr_sz > sizeof(chunk_header_t)) {
+ /*
+ * Skip the remaining bytes in a header that is longer
+ * than we expected.
+ */
+ data += (sparse_header->chunk_hdr_sz -
+ sizeof(chunk_header_t));
}
- /* Retrieve the buffer we're going to write */
- buffer = sparse_get_data_buffer(sparse_header, chunk_header,
- storage->block_sz, &data);
- if (!buffer)
- continue;
-
- blkcnt = (buffer->length / storage->block_sz) * buffer->repeat;
+ chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz;
+ blkcnt = chunk_data_sz / info->blksz;
+ switch (chunk_header->chunk_type) {
+ case CHUNK_TYPE_RAW:
+ if (chunk_header->total_sz !=
+ (sparse_header->chunk_hdr_sz + chunk_data_sz)) {
+ fastboot_fail(
+ "Bogus chunk size for chunk type Raw");
+ return;
+ }
- if ((start + total_blocks + blkcnt) >
- (storage->start + storage->size)) {
- printf("%s: Request would exceed partition size!\n",
- __func__);
- return -EINVAL;
- }
+ if (blk + blkcnt > info->start + info->size) {
+ printf(
+ "%s: Request would exceed partition size!\n",
+ __func__);
+ fastboot_fail(
+ "Request would exceed partition size!");
+ return;
+ }
- for (i = 0; i < buffer->repeat; i++) {
- unsigned long buffer_blk_cnt;
- int ret;
+ blks = info->write(info, blk, blkcnt, data);
+ /* blks might be > blkcnt (eg. NAND bad-blocks) */
+ if (blks < blkcnt) {
+ printf("%s: %s" LBAFU " [" LBAFU "]\n",
+ __func__, "Write failed, block #",
+ blk, blks);
+ fastboot_fail(
+ "flash write failure");
+ return;
+ }
+ blk += blks;
+ bytes_written += blkcnt * info->blksz;
+ total_blocks += chunk_header->chunk_sz;
+ data += chunk_data_sz;
+ break;
+
+ case CHUNK_TYPE_FILL:
+ if (chunk_header->total_sz !=
+ (sparse_header->chunk_hdr_sz + sizeof(uint32_t))) {
+ fastboot_fail(
+ "Bogus chunk size for chunk type FILL");
+ return;
+ }
- buffer_blk_cnt = buffer->length / storage->block_sz;
+ fill_buf = (uint32_t *)
+ memalign(ARCH_DMA_MINALIGN,
+ ROUNDUP(
+ info->blksz * fill_buf_num_blks,
+ ARCH_DMA_MINALIGN));
+ if (!fill_buf) {
+ fastboot_fail(
+ "Malloc failed for: CHUNK_TYPE_FILL");
+ return;
+ }
- ret = storage->write(storage, storage_priv,
- start + total_blocks,
- buffer_blk_cnt,
- buffer->data);
- if (ret < 0) {
- printf("%s: Write %d failed %d\n",
- __func__, i, ret);
- return ret;
+ fill_val = *(uint32_t *)data;
+ data = (char *)data + sizeof(uint32_t);
+
+ for (i = 0;
+ i < (info->blksz * fill_buf_num_blks /
+ sizeof(fill_val));
+ i++)
+ fill_buf[i] = fill_val;
+
+ if (blk + blkcnt > info->start + info->size) {
+ printf(
+ "%s: Request would exceed partition size!\n",
+ __func__);
+ fastboot_fail(
+ "Request would exceed partition size!");
+ return;
}
- total_blocks += ret;
+ for (i = 0; i < blkcnt;) {
+ j = blkcnt - i;
+ if (j > fill_buf_num_blks)
+ j = fill_buf_num_blks;
+ blks = info->write(info, blk, j, fill_buf);
+ /* blks might be > j (eg. NAND bad-blocks) */
+ if (blks < j) {
+ printf("%s: %s " LBAFU " [%d]\n",
+ __func__,
+ "Write failed, block #",
+ blk, j);
+ fastboot_fail(
+ "flash write failure");
+ free(fill_buf);
+ return;
+ }
+ blk += blks;
+ i += j;
+ }
+ bytes_written += blkcnt * info->blksz;
+ total_blocks += chunk_data_sz / sparse_header->blk_sz;
+ free(fill_buf);
+ break;
+
+ case CHUNK_TYPE_DONT_CARE:
+ blk += info->reserve(info, blk, blkcnt);
+ total_blocks += chunk_header->chunk_sz;
+ break;
+
+ case CHUNK_TYPE_CRC32:
+ if (chunk_header->total_sz !=
+ sparse_header->chunk_hdr_sz) {
+ fastboot_fail(
+ "Bogus chunk size for chunk type Dont Care");
+ return;
+ }
+ total_blocks += chunk_header->chunk_sz;
+ data += chunk_data_sz;
+ break;
+
+ default:
+ printf("%s: Unknown chunk type: %x\n", __func__,
+ chunk_header->chunk_type);
+ fastboot_fail("Unknown chunk type");
+ return;
}
-
- sparse_put_data_buffer(buffer);
}
debug("Wrote %d blocks, expected to write %d blocks\n",
- total_blocks,
- sparse_block_size_to_storage(sparse_header->total_blks,
- storage, sparse_header));
- printf("........ wrote %d blocks to '%s'\n", total_blocks,
- storage->name);
+ total_blocks, sparse_header->total_blks);
+ printf("........ wrote %u bytes to '%s'\n", bytes_written, part_name);
- if (total_blocks !=
- sparse_block_size_to_storage(sparse_header->total_blks,
- storage, sparse_header)) {
- printf("sparse image write failure\n");
- return -EIO;
- }
-
- last_offset = start + total_blocks;
+ if (total_blocks != sparse_header->total_blks)
+ fastboot_fail("sparse image write failure");
+ else
+ fastboot_okay("");
- return 0;
+ return;
}
return err;
}
- boot_mode = spl_boot_mode();
+ boot_mode = spl_boot_mode(boot_device);
err = -EINVAL;
switch (boot_mode) {
case MMCSD_MODE_EMMCBOOT:
CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
+CONFIG_SPI_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
CONFIG_TARGET_AM43XX_EVM=y
CONFIG_ISW_ENTRY_ADDR=0x30000000
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_OF_LIBFDT=y
-CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_TAURUS=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
+CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USE_TINY_PRINTF=y
-CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_TARGET_BCM23550_W1D=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
CONFIG_G_DNL_VENDOR_NUM=0x18d1
CONFIG_ARM=y
-CONFIG_TARGET_TSERIES=y
+CONFIG_TARGET_BRPPT1=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
CONFIG_ARM=y
-CONFIG_TARGET_TSERIES=y
+CONFIG_TARGET_BRPPT1=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
CONFIG_ARM=y
-CONFIG_TARGET_TSERIES=y
+CONFIG_TARGET_BRPPT1=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
+CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=0
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_ARM=y
-CONFIG_TARGET_KWB=y
+CONFIG_TARGET_BRXRE1=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
CONFIG_BOOTDELAY=0
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_CORVUS=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
CONFIG_BOOTDELAY=3
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_G_DNL_VENDOR_NUM=0x0908
CONFIG_G_DNL_PRODUCT_NUM=0x02d2
CONFIG_OF_LIBFDT=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+# CONFIG_EFI_LOADER is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
+CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_ARM=y
CONFIG_TARGET_LS2080AQDS=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
-CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-CONFIG_DM=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
-CONFIG_CMD_SF=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
+CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_OF_LIBFDT=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_MESON_GXBB=y
CONFIG_TARGET_ODROID_C2=y
CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
+CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
CONFIG_TARGET_S32V234EVB=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/s32v234evb/s32v234evb.cfg"
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_SMARTWEB=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9260-smartweb"
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Siemens AG"
CONFIG_G_DNL_VENDOR_NUM=0x0908
CONFIG_G_DNL_PRODUCT_NUM=0x02d2
-CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_TARGET_TAURUS=y
+CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
+CONFIG_HUSH_PARSER=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
CONFIG_G_DNL_VENDOR_NUM=0x0908
CONFIG_G_DNL_PRODUCT_NUM=0x02d2
CONFIG_USE_TINY_PRINTF=y
-CONFIG_OF_LIBFDT=y
CONFIG_BOARD_TPLINK_WDR4300=y
CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
verification. Typically the file here is the device tree binary used by
CONFIG_OF_CONTROL in U-Boot.
+.TP
+.BI "\-p [" "external position" "]"
+Place external data at a static external position. See \-E. Instead of writing
+a 'data-offset' property defining the offset from the end of the FIT, \-p will
+use 'data-position' as the absolute position from the base of the FIT.
+
.TP
.BI "\-r
Specifies that keys used to sign the FIT are required. This means that they
aligned to a 4-byte boundary.
- data-size : size of the data in bytes
+The 'data-offset' property can be substituted with 'data-position', which
+defines an absolute position or address as the offset. This is helpful when
+booting U-Boot proper before performing relocation.
9) Examples
-----------
{
struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
- if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+ if (clk->id >= SANDBOX_CLK_ID_COUNT)
return -EINVAL;
return priv->rate[clk->id];
struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
ulong old_rate;
- if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+ if (clk->id >= SANDBOX_CLK_ID_COUNT)
return -EINVAL;
if (!rate)
{
struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
- if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+ if (clk->id >= SANDBOX_CLK_ID_COUNT)
return -EINVAL;
priv->enabled[clk->id] = true;
{
struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
- if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+ if (clk->id >= SANDBOX_CLK_ID_COUNT)
return -EINVAL;
priv->enabled[clk->id] = false;
if (host->fifo_mode && size) {
if (data->flags == MMC_DATA_READ) {
- if ((dwmci_readl(host, DWMCI_RINTSTS) &&
+ if ((dwmci_readl(host, DWMCI_RINTSTS) &
DWMCI_INTMSK_RXDR)) {
len = dwmci_readl(host, DWMCI_STATUS);
len = (len >> DWMCI_FIFO_SHIFT) &
DWMCI_INTMSK_RXDR);
}
} else {
- if ((dwmci_readl(host, DWMCI_RINTSTS) &&
+ if ((dwmci_readl(host, DWMCI_RINTSTS) &
DWMCI_INTMSK_TXDR)) {
len = dwmci_readl(host, DWMCI_STATUS);
len = fifo_depth - ((len >>
*/
static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
{
-
int status;
unsigned long timeo = 400;
}
static struct f_fastboot *fastboot_func;
-static unsigned int fastboot_flash_session_id;
static unsigned int download_size;
static unsigned int download_bytes;
static int strcmp_l1(const char *s1, const char *s2);
-void fastboot_fail(char *response, const char *reason)
+static char *fb_response_str;
+
+void fastboot_fail(const char *reason)
{
- strncpy(response, "FAIL\0", 5);
- strncat(response, reason, FASTBOOT_RESPONSE_LEN - 4 - 1);
+ strncpy(fb_response_str, "FAIL\0", 5);
+ strncat(fb_response_str, reason, FASTBOOT_RESPONSE_LEN - 4 - 1);
}
-void fastboot_okay(char *response, const char *reason)
+void fastboot_okay(const char *reason)
{
- strncpy(response, "OKAY\0", 5);
- strncat(response, reason, FASTBOOT_RESPONSE_LEN - 4 - 1);
+ strncpy(fb_response_str, "OKAY\0", 5);
+ strncat(fb_response_str, reason, FASTBOOT_RESPONSE_LEN - 4 - 1);
}
static void fastboot_complete(struct usb_ep *ep, struct usb_request *req)
sprintf(str_num, "0x%08x", CONFIG_FASTBOOT_BUF_SIZE);
strncat(response, str_num, chars_left);
-
- /*
- * This also indicates the start of a new flashing
- * "session", in which we could have 1-N buffers to
- * write to a partition.
- *
- * Reset our session counter.
- */
- fastboot_flash_session_id = 0;
} else if (!strcmp_l1("serialno", cmd)) {
s = getenv("serial#");
if (s)
return;
}
- strcpy(response, "FAILno flash device defined");
+ /* initialize the response buffer */
+ fb_response_str = response;
+
+ fastboot_fail("no flash device defined");
#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
- fb_mmc_flash_write(cmd, fastboot_flash_session_id,
- (void *)CONFIG_FASTBOOT_BUF_ADDR,
- download_bytes, response);
+ fb_mmc_flash_write(cmd, (void *)CONFIG_FASTBOOT_BUF_ADDR,
+ download_bytes);
#endif
#ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV
- fb_nand_flash_write(cmd, fastboot_flash_session_id,
+ fb_nand_flash_write(cmd,
(void *)CONFIG_FASTBOOT_BUF_ADDR,
- download_bytes, response);
+ download_bytes);
#endif
- fastboot_flash_session_id++;
fastboot_tx_write_str(response);
}
#endif
return;
}
- strcpy(response, "FAILno flash device defined");
+ /* initialize the response buffer */
+ fb_response_str = response;
+ fastboot_fail("no flash device defined");
#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
- fb_mmc_erase(cmd, response);
+ fb_mmc_erase(cmd);
#endif
#ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV
- fb_nand_erase(cmd, response);
+ fb_nand_erase(cmd);
#endif
fastboot_tx_write_str(response);
}
"${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; " \
"if fdt addr ${fdt_addr_r}; then " \
"bootefi ${kernel_addr_r} ${fdt_addr_r};" \
- "else" \
+ "else " \
"bootefi ${kernel_addr_r} ${fdtcontroladdr};" \
"fi\0" \
\
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_SDRAM_BASE
#undef CONFIG_USB_GADGET_VBUS_DRAW
#define CONFIG_USB_GADGET_VBUS_DRAW 0
-#define CONFIG_USB_GADGET_DWC2_PHY_8_BIT
#define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
#define CONFIG_USBID_ADDR 0x34052c46
/*
- * tseries.h
+ * brtpp1.h
*
* specific parts for B&R T-Series Motherboard
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_TSERIES_H__
-#define __CONFIG_TSERIES_H__
+#ifndef __CONFIG_BRPPT1_H__
+#define __CONFIG_BRPPT1_H__
#include <configs/bur_cfg_common.h>
#include <configs/bur_am335x_common.h>
#define CONFIG_EXT4_WRITE
#endif /* CONFIG_MMC, ... */
-#endif /* ! __CONFIG_TSERIES_H__ */
+#endif /* ! __CONFIG_BRPPT1_H__ */
/*
- * kwb.h
+ * brxre1.h
*
* specific parts for B&R KWB Motherboard
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_KWB_H__
-#define __CONFIG_KWB_H__
+#ifndef __CONFIG_BRXRE1_H__
+#define __CONFIG_BRXRE1_H__
#include <configs/bur_cfg_common.h>
#include <configs/bur_am335x_common.h>
#define CONFIG_FAT_WRITE
#endif /* CONFIG_MMC, ... */
-#endif /* __CONFIG_KWB_H__ */
+#endif /* __CONFIG_BRXRE1_H__ */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
--- /dev/null
+/*
+ * Configuration for Amlogic Meson GXBB SoCs
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MESON_GXBB_COMMON_CONFIG_H
+#define __MESON_GXBB_COMMON_CONFIG_H
+
+#define CONFIG_CPU_ARMV8
+#define CONFIG_REMAKE_ELF
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_TEXT_BASE 0x01000000
+#define CONFIG_SYS_INIT_SP_ADDR 0x20000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0xc4301000
+#define GICC_BASE 0xc4302000
+
+#define CONFIG_CMD_ENV
+
+/* Monitor Command Prompt */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+#include <config_distro_defaults.h>
+
+#endif /* __MESON_GXBB_COMMON_CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_CPU_ARMV8
-#define CONFIG_REMAKE_ELF
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_ENV_IS_NOWHERE 1
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_SYS_MAXARGS 32
-#define CONFIG_SYS_MALLOC_LEN (32 << 20)
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_SDRAM_BASE 0
-#define CONFIG_SYS_TEXT_BASE 0x01000000
-#define CONFIG_SYS_INIT_SP_ADDR 0x20000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
-
-/* Generic Interrupt Controller Definitions */
-#define GICD_BASE 0xc4301000
-#define GICC_BASE 0xc4302000
-
#define CONFIG_IDENT_STRING " odroid-c2"
/* Serial setup */
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200
-#define CONFIG_CMD_ENV
-
-/* Monitor Command Prompt */
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-
-#include <config_distro_defaults.h>
+#include <configs/meson-gxbb-common.h>
#endif /* __CONFIG_H */
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "=> "
#undef CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */
#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */
#define CONFIG_INITRD_TAG /* pass initrd param to kernel */
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* U-Boot is loaded by a bootloader */
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
#define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_USB_ETHER_MCS7830
-
/* USB DFU support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
/* U-Boot memory settings */
#define CONFIG_SYS_MALLOC_LEN (1 << 20)
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
#define CONFIG_AUTO_COMPLETE /* Command auto complete */
#define CONFIG_CMDLINE_EDITING /* Command history etc */
-#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* USB, USB storage, USB ethernet */
#endif
#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
"arch=" CONFIG_SYS_ARCH "\0"
+#ifdef CONFIG_SYS_CPU
"cpu=" CONFIG_SYS_CPU "\0"
+#endif
+#ifdef CONFIG_SYS_BOARD
"board=" CONFIG_SYS_BOARD "\0"
"board_name=" CONFIG_SYS_BOARD "\0"
+#endif
#ifdef CONFIG_SYS_VENDOR
"vendor=" CONFIG_SYS_VENDOR "\0"
#endif
/* The 64 defined bytes plus \0 */
#define FASTBOOT_RESPONSE_LEN (64 + 1)
-void fastboot_fail(char *response, const char *reason);
-void fastboot_okay(char *response, const char *reason);
+void fastboot_fail(const char *reason);
+void fastboot_okay(const char *reason);
#endif /* _FASTBOOT_H_ */
* SPDX-License-Identifier: GPL-2.0+
*/
-void fb_mmc_flash_write(const char *cmd, unsigned int session_id,
- void *download_buffer, unsigned int download_bytes,
- char *response);
-void fb_mmc_erase(const char *cmd, char *response);
+void fb_mmc_flash_write(const char *cmd, void *download_buffer,
+ unsigned int download_bytes);
+void fb_mmc_erase(const char *cmd);
* SPDX-License-Identifier: GPL-2.0+
*/
-void fb_nand_flash_write(const char *cmd, unsigned int session_id,
- void *download_buffer, unsigned int download_bytes,
- char *response);
-void fb_nand_erase(const char *cmd, char *response);
+void fb_nand_flash_write(const char *cmd, void *download_buffer,
+ unsigned int download_bytes);
+void fb_nand_erase(const char *cmd);
#define ROUNDUP(x, y) (((x) + ((y) - 1)) & ~((y) - 1))
-typedef struct sparse_storage {
- unsigned int block_sz;
- unsigned int start;
- unsigned int size;
- const char *name;
-
- int (*write)(struct sparse_storage *storage, void *priv,
- unsigned int offset, unsigned int size,
- char *data);
-} sparse_storage_t;
+struct sparse_storage {
+ lbaint_t blksz;
+ lbaint_t start;
+ lbaint_t size;
+ void *priv;
+
+ lbaint_t (*write)(struct sparse_storage *info,
+ lbaint_t blk,
+ lbaint_t blkcnt,
+ const void *buffer);
+
+ lbaint_t (*reserve)(struct sparse_storage *info,
+ lbaint_t blk,
+ lbaint_t blkcnt);
+};
static inline int is_sparse_image(void *buf)
{
return 0;
}
-int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
- unsigned int session_id, void *data);
+void write_sparse_image(struct sparse_storage *info, const char *part_name,
+ void *data, unsigned sz);
ulong *rd_data, ulong *rd_len);
ulong android_image_get_end(const struct andr_img_hdr *hdr);
ulong android_image_get_kload(const struct andr_img_hdr *hdr);
+void android_print_contents(const struct andr_img_hdr *hdr);
#endif /* CONFIG_ANDROID_BOOT_IMAGE */
/* SPL common functions */
void preloader_console_init(void);
u32 spl_boot_device(void);
-u32 spl_boot_mode(void);
+u32 spl_boot_mode(const u32 boot_device);
void spl_set_header_raw_uboot(void);
int spl_parse_image_header(const struct image_header *header);
void spl_board_prepare_for_linux(void);
if (dlen > remaining)
return LZO_E_OUTPUT_OVERRUN;
- /* decompress */
- tmp = dlen;
- r = lzo1x_decompress_safe((u8 *) src, slen, dst, &tmp);
+ /* When the input data is not compressed at all,
+ * lzo1x_decompress_safe will fail, so call memcpy()
+ * instead */
+ if (dlen == slen) {
+ memcpy(dst, src, slen);
+ } else {
+ /* decompress */
+ tmp = dlen;
+ r = lzo1x_decompress_safe((u8 *)src, slen, dst, &tmp);
+
+ if (r != LZO_E_OK) {
+ *dst_len = dst - start;
+ return r;
+ }
- if (r != LZO_E_OK) {
- *dst_len = dst - start;
- return r;
+ if (dlen != tmp)
+ return LZO_E_ERROR;
}
- if (dlen != tmp)
- return LZO_E_ERROR;
-
src += slen;
dst += dlen;
remaining -= dlen;
assert(run_command_list("false", -1, 0) == 1);
assert(run_command_list("echo", -1, 0) == 0);
-#ifdef CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_HUSH_PARSER
run_command("setenv foo 'setenv black 1\nsetenv adder 2'", 0);
run_command("run foo", 0);
assert(getenv("black") != NULL);
struct image_tool_params *params)
{
uint32_t checksum;
- char *source_date_epoch;
time_t time;
image_header_t * hdr = (image_header_t *)ptr;
sizeof(image_header_t)),
sbuf->st_size - sizeof(image_header_t));
- source_date_epoch = getenv("SOURCE_DATE_EPOCH");
- if (source_date_epoch != NULL) {
- time = (time_t) strtol(source_date_epoch, NULL, 10);
-
- if (gmtime(&time) == NULL) {
- fprintf(stderr, "%s: SOURCE_DATE_EPOCH is not valid\n",
- __func__);
- time = 0;
- }
- } else {
- time = sbuf->st_mtime;
- }
+ time = imagetool_get_source_date(params, sbuf->st_mtime);
/* Build new header */
image_set_magic(hdr, IH_MAGIC);
}
/* for first image creation, add a timestamp at offset 0 i.e., root */
- if (params->datafile)
- ret = fit_set_timestamp(ptr, 0, sbuf.st_mtime);
+ if (params->datafile) {
+ time_t time = imagetool_get_source_date(params, sbuf.st_mtime);
+ ret = fit_set_timestamp(ptr, 0, time);
+ }
if (!ret) {
ret = fit_add_verification_data(params->keydir, dest_blob, ptr,
ret = -EPERM;
goto err_munmap;
}
- fdt_setprop_u32(fdt, node, "data-offset", buf_ptr);
+ if (params->external_offset > 0) {
+ /* An external offset positions the data absolutely. */
+ fdt_setprop_u32(fdt, node, "data-position",
+ params->external_offset + buf_ptr);
+ } else {
+ fdt_setprop_u32(fdt, node, "data-offset", buf_ptr);
+ }
fdt_setprop_u32(fdt, node, "data-size", len);
buf_ptr += (len + 3) & ~3;
ret = -EIO;
goto err;
}
+
+ /* Check if an offset for the external data was set. */
+ if (params->external_offset > 0) {
+ if (params->external_offset < new_size) {
+ debug("External offset %x overlaps FIT length %x",
+ params->external_offset, new_size);
+ ret = -EINVAL;
+ goto err;
+ }
+ new_size = params->external_offset;
+ }
if (lseek(fd, new_size, SEEK_SET) < 0) {
debug("%s: Failed to seek to end of file: %s\n", __func__,
strerror(errno));
return sbuf.st_size;
}
+
+time_t imagetool_get_source_date(
+ struct image_tool_params *params,
+ time_t fallback)
+{
+ char *source_date_epoch = getenv("SOURCE_DATE_EPOCH");
+
+ if (source_date_epoch == NULL)
+ return fallback;
+
+ time_t time = (time_t) strtol(source_date_epoch, NULL, 10);
+
+ if (gmtime(&time) == NULL) {
+ fprintf(stderr, "%s: SOURCE_DATE_EPOCH is not valid\n",
+ params->cmdname);
+ time = 0;
+ }
+
+ return time;
+}
struct content_info *content_tail;
bool external_data; /* Store data outside the FIT */
bool quiet; /* Don't output text in normal operation */
+ unsigned int external_offset; /* Add padding to external data */
};
/*
*/
int imagetool_get_filesize(struct image_tool_params *params, const char *fname);
+/**
+ * imagetool_get_source_date() - Get timestamp for build output.
+ *
+ * Gets a timestamp for embedding it in a build output. If set
+ * SOURCE_DATE_EPOCH is used. Else the given fallback value is returned. Prints
+ * an error message if SOURCE_DATE_EPOCH contains an invalid value and returns
+ * 0.
+ *
+ * @params: mkimage parameters
+ * @fallback: timestamp to use if SOURCE_DATE_EPOCH isn't set
+ * @return timestamp based on SOURCE_DATE_EPOCH
+ */
+time_t imagetool_get_source_date(
+ struct image_tool_params *params,
+ time_t fallback);
+
/*
* There is a c file associated with supported image type low level code
* for ex. default_image.c, fit_image.c
" -f => input filename for FIT source\n");
#ifdef CONFIG_FIT_SIGNATURE
fprintf(stderr,
- "Signing / verified boot options: [-k keydir] [-K dtb] [ -c <comment>] [-r]\n"
+ "Signing / verified boot options: [-E] [-k keydir] [-K dtb] [ -c <comment>] [-p addr] [-r]\n"
+ " -E => place data outside of the FIT structure\n"
" -k => set directory containing private keys\n"
" -K => write public keys to this .dtb file\n"
" -c => add comment in signature node\n"
" -F => re-sign existing FIT image\n"
+ " -p => place external data at a static position\n"
" -r => mark keys used as 'required' in dtb\n");
#else
fprintf(stderr,
int opt;
while ((opt = getopt(argc, argv,
- "a:A:b:cC:d:D:e:Ef:Fk:K:ln:O:rR:qsT:vVx")) != -1) {
+ "a:A:b:cC:d:D:e:Ef:Fk:K:ln:p:O:rR:qsT:vVx")) != -1) {
switch (opt) {
case 'a':
params.addr = strtoull(optarg, &ptr, 16);
if (params.os < 0)
usage("Invalid operating system");
break;
+ case 'p':
+ params.external_offset = strtoull(optarg, &ptr, 16);
+ if (*ptr) {
+ fprintf(stderr, "%s: invalid offset size %s\n",
+ params.cmdname, optarg);
+ exit(EXIT_FAILURE);
+ }
case 'q':
params.quiet = 1;
break;
projects / thirdparty / u-boot.git / commitdiff
