struct intel_vblank_evade_ctx evade;
int scanline;
+ drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
+
intel_psr_lock(new_crtc_state);
if (new_crtc_state->do_async_flip) {
ktime_t end_vbl_time = ktime_get();
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ drm_WARN_ON(display->drm, new_crtc_state->use_dsb);
+
if (new_crtc_state->do_async_flip)
goto out;
intel_atomic_get_new_crtc_state(state, crtc);
bool modeset = intel_crtc_needs_modeset(new_crtc_state);
+ drm_WARN_ON(&dev_priv->drm, new_crtc_state->use_dsb);
+
/*
* During modesets pipe configuration was programmed as the
* CRTC was enabled.
*/
- if (!modeset && !new_crtc_state->use_dsb) {
+ if (!modeset) {
if (intel_crtc_needs_color_update(new_crtc_state))
intel_color_commit_arm(NULL, new_crtc_state);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ drm_WARN_ON(&dev_priv->drm, new_crtc_state->use_dsb);
+
/*
* Disable the scaler(s) after the plane(s) so that we don't
* get a catastrophic underrun even if the two operations