data->disp_negative = true;
}
- if (boot_cpu_data.x86 == 0x15 &&
+ data->is_zen = cpu_feature_enabled(X86_FEATURE_ZEN);
+ if (data->is_zen) {
+ data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
+ data->read_tempreg = read_tempreg_nb_zen;
+ } else if (boot_cpu_data.x86 == 0x15 &&
((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
(boot_cpu_data.x86_model & 0xf0) == 0x70)) {
data->read_htcreg = read_htcreg_nb_f15;
data->read_tempreg = read_tempreg_nb_f15;
- } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
- data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
- data->read_tempreg = read_tempreg_nb_zen;
- data->is_zen = true;
+ } else {
+ data->read_htcreg = read_htcreg_pci;
+ data->read_tempreg = read_tempreg_pci;
+ }
+ if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
switch (boot_cpu_data.x86_model) {
case 0x1: /* Zen */
case 0x8: /* Zen+ */
break;
}
} else if (boot_cpu_data.x86 == 0x19) {
- data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
- data->read_tempreg = read_tempreg_nb_zen;
- data->is_zen = true;
-
switch (boot_cpu_data.x86_model) {
case 0x0 ... 0x1: /* Zen3 SP3/TR */
case 0x8: /* Zen3 TR Chagall */
k10temp_get_ccd_support(data, 12);
break;
}
- } else if (boot_cpu_data.x86 == 0x1a) {
- data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
- data->read_tempreg = read_tempreg_nb_zen;
- data->is_zen = true;
- } else {
- data->read_htcreg = read_htcreg_pci;
- data->read_tempreg = read_tempreg_pci;
}
for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {