clk: renesas: r9a09g077: Add USB core and module clocks

Add module and core clocks used by USB.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250804202643.3967484-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
index c920d6a9707f1f4c79a3bbf3ad1465b6ff232516..704d14d31e871463b14cf1b3a7a61b96180a72c9 100644 (file)
--- a/drivers/clk/renesas/r9a09g077-cpg.c
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -67,7 +67,7 @@ enum rzt2h_clk_types {
 
 enum clk_ids {
        /* Core Clock Outputs exported to DT */
-       LAST_DT_CORE_CLK = R9A09G077_SDHI_CLKHS,
+       LAST_DT_CORE_CLK = R9A09G077_USB_CLK,
 
        /* External Input Clocks */
        CLK_EXTAL,
@@ -150,12 +150,14 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
        DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1),
        DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1),
        DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1),
+       DEF_FIXED("USB_CLK", R9A09G077_USB_CLK, CLK_PLL4D1, 48, 1),
 };
 
 static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
        DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC),
        DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
        DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
+       DEF_MOD("usb", 408, R9A09G077_CLK_PCLKAM),
        DEF_MOD("iic2", 601, R9A09G077_CLK_PCLKL),
        DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM),
        DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM),