Merge branch 'pci/controller/qcom'

- Drop endpoint redundant masking of global IRQ events (Manivannan
  Sadhasivam)

- Clarify unknown global IRQ message and only log it once to avoid a flood
  (Manivannan Sadhasivam)

- Add Manivannan Sadhasivam as maintainer of qcom endpoint driver
  (Manivannan Sadhasivam)

- Add 'linux,pci-domain' property to endpoint DT binding (Manivannan
  Sadhasivam)

- Assign PCI domain number for endpoint controllers (Manivannan Sadhasivam)

- Add 'qcom_pcie_ep' and the PCI domain number to IRQ names for endpoint
  controller (Manivannan Sadhasivam)

- Add global SPI interrupt for PCIe link events to DT binding (Manivannan
  Sadhasivam)

- Add global RC interrupt handler to handle 'Link up' events and
  automatically enumerate hot-added devices (Manivannan Sadhasivam)

- Avoid mirroring of DBI and iATU register space so it doesn't overlap BAR
  MMIO space (Prudhvi Yarlagadda)

- Enable controller resources like PHY only after PERST# is deasserted to
  partially avoid the problem that the endpoint SoC crashes when accessing
  things when Refclk is absent (Manivannan Sadhasivam)

- Rename dw_pcie.link_gen to max_link_speed to avoid ambiguity (Manivannan
  Sadhasivam)

- Cache maximum link speed value in dw_pcie.max_link_speed for use by
  vendor drivers (Manivannan Sadhasivam)

- Add 16.0 GT/s equalization and RX lane margining settings (Shashank Babu
  Chinta Venkata)

- Pass domain number to pci_bus_release_domain_nr() explicitly to avoid a
  NULL pointer dereference (Manivannan Sadhasivam)

* pci/controller/qcom:
  PCI: Pass domain number to pci_bus_release_domain_nr() explicitly
  PCI: qcom: Add RX lane margining settings for 16.0 GT/s
  PCI: qcom: Add equalization settings for 16.0 GT/s
  PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
  PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
  PCI: qcom-ep: Enable controller resources like PHY only after refclk is available
  PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region
  PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt
  dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt
  PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names
  PCI: endpoint: Assign PCI domain number for endpoint controllers
  dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property
  dt-bindings: PCI: pci-ep: Update Maintainers
  PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event
  PCI: qcom-ep: Drop the redundant masking of global IRQ events

diff --cc Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
Simple merge

diff --cc MAINTAINERS
Simple merge

diff --cc drivers/pci/controller/dwc/pci-imx6.c
index 5a40cd7f29d4afdfa54cea30c28f5ae952242454,ef12a4f31740bf83d374076a38e25543fd119cc4..808d1f10541733a26aa826be2ae2c76cad88f7f1
--- 1/drivers/pci/controller/dwc/pci-imx6.c
--- 2/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@@ -1403,46 -1366,46 +1403,46 @@@ static int imx_pcie_probe(struct platfo
  
        /* Grab PCIe PHY Tx Settings */
        if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
 -                               &imx6_pcie->tx_deemph_gen1))
 -              imx6_pcie->tx_deemph_gen1 = 0;
 +                               &imx_pcie->tx_deemph_gen1))
 +              imx_pcie->tx_deemph_gen1 = 0;
  
        if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
 -                               &imx6_pcie->tx_deemph_gen2_3p5db))
 -              imx6_pcie->tx_deemph_gen2_3p5db = 0;
 +                               &imx_pcie->tx_deemph_gen2_3p5db))
 +              imx_pcie->tx_deemph_gen2_3p5db = 0;
  
        if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
 -                               &imx6_pcie->tx_deemph_gen2_6db))
 -              imx6_pcie->tx_deemph_gen2_6db = 20;
 +                               &imx_pcie->tx_deemph_gen2_6db))
 +              imx_pcie->tx_deemph_gen2_6db = 20;
  
        if (of_property_read_u32(node, "fsl,tx-swing-full",
 -                               &imx6_pcie->tx_swing_full))
 -              imx6_pcie->tx_swing_full = 127;
 +                               &imx_pcie->tx_swing_full))
 +              imx_pcie->tx_swing_full = 127;
  
        if (of_property_read_u32(node, "fsl,tx-swing-low",
 -                               &imx6_pcie->tx_swing_low))
 -              imx6_pcie->tx_swing_low = 127;
 +                               &imx_pcie->tx_swing_low))
 +              imx_pcie->tx_swing_low = 127;
  
        /* Limit link speed */
-       pci->link_gen = 1;
-       of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
+       pci->max_link_speed = 1;
+       of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed);
  
 -      imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
 -      if (IS_ERR(imx6_pcie->vpcie)) {
 -              if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV)
 -                      return PTR_ERR(imx6_pcie->vpcie);
 -              imx6_pcie->vpcie = NULL;
 +      imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
 +      if (IS_ERR(imx_pcie->vpcie)) {
 +              if (PTR_ERR(imx_pcie->vpcie) != -ENODEV)
 +                      return PTR_ERR(imx_pcie->vpcie);
 +              imx_pcie->vpcie = NULL;
        }
  
 -      imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
 -      if (IS_ERR(imx6_pcie->vph)) {
 -              if (PTR_ERR(imx6_pcie->vph) != -ENODEV)
 -                      return PTR_ERR(imx6_pcie->vph);
 -              imx6_pcie->vph = NULL;
 +      imx_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
 +      if (IS_ERR(imx_pcie->vph)) {
 +              if (PTR_ERR(imx_pcie->vph) != -ENODEV)
 +                      return PTR_ERR(imx_pcie->vph);
 +              imx_pcie->vph = NULL;
        }
  
 -      platform_set_drvdata(pdev, imx6_pcie);
 +      platform_set_drvdata(pdev, imx_pcie);
  
 -      ret = imx6_pcie_attach_pd(dev);
 +      ret = imx_pcie_attach_pd(dev);
        if (ret)
                return ret;
  

diff --cc drivers/pci/controller/dwc/pcie-tegra194.c
index 886354342ef13c0e67115a0bcc545197038041fd,6e03e14151d64687c47d46615c736d90beeee47b..c1394f2ab63ff1e2a47e42f4946d6102c75d2899
--- 1/drivers/pci/controller/dwc/pcie-tegra194.c
--- 2/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@@ -177,17 -177,12 +177,12 @@@
  #define N_FTS_VAL                                     52
  #define FTS_VAL                                               52
  
- #define GEN3_EQ_CONTROL_OFF                   0x8a8
- #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT        8
- #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
- #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK      GENMASK(3, 0)
- 
  #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT        0x8D0
 -#define AMBA_ERROR_RESPONSE_CRS_SHIFT         3
 -#define AMBA_ERROR_RESPONSE_CRS_MASK          GENMASK(1, 0)
 -#define AMBA_ERROR_RESPONSE_CRS_OKAY          0
 -#define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF 1
 -#define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 2
 +#define AMBA_ERROR_RESPONSE_RRS_SHIFT         3
 +#define AMBA_ERROR_RESPONSE_RRS_MASK          GENMASK(1, 0)
 +#define AMBA_ERROR_RESPONSE_RRS_OKAY          0
 +#define AMBA_ERROR_RESPONSE_RRS_OKAY_FFFFFFFF 1
 +#define AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 2
  
  #define MSIX_ADDR_MATCH_LOW_OFF                       0x940
  #define MSIX_ADDR_MATCH_LOW_OFF_EN            BIT(0)

diff --cc drivers/pci/pci.c
Simple merge

diff --cc drivers/pci/probe.c
Simple merge

diff --cc drivers/pci/remove.c
Simple merge

diff --cc include/linux/pci-epc.h
Simple merge

diff --cc include/linux/pci.h
Simple merge