PCI: qcom: Prepare for the DWC ECAM enablement

To support the DWC ECAM mechanism, prepare the driver by performing below
configurations:

  1. Since the ELBI region will be covered by the ECAM 'config' space,
     override the 'elbi_base' with the address derived from 'dbi_base' and
     the offset from PARF_SLV_DBI_ELBI register.

  2. Block the transactions from the host bridge to devices other than Root
     Port on the root bus to return all F's. This is required when the 'CFG
     Shift Feature' of iATU is enabled.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
[mani: code split, reworded subject/description and comments]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20250923-controller-dwc-ecam-v10-3-e84390ba75fa@kernel.org

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index c48a20602d7fa4c50056ccf6502d3b5bf0a8287f..e6d2a6b0c087151781ddaf6bf7612f87e2445d17 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -55,6 +55,7 @@
 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2          0x1a8
 #define PARF_Q2A_FLUSH                         0x1ac
 #define PARF_LTSSM                             0x1b0
+#define PARF_SLV_DBI_ELBI                      0x1b4
 #define PARF_INT_ALL_STATUS                    0x224
 #define PARF_INT_ALL_CLEAR                     0x228
 #define PARF_INT_ALL_MASK                      0x22c
@@ -64,6 +65,16 @@
 #define PARF_DBI_BASE_ADDR_V2_HI               0x354
 #define PARF_SLV_ADDR_SPACE_SIZE_V2            0x358
 #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI         0x35c
+#define PARF_BLOCK_SLV_AXI_WR_BASE             0x360
+#define PARF_BLOCK_SLV_AXI_WR_BASE_HI          0x364
+#define PARF_BLOCK_SLV_AXI_WR_LIMIT            0x368
+#define PARF_BLOCK_SLV_AXI_WR_LIMIT_HI         0x36c
+#define PARF_BLOCK_SLV_AXI_RD_BASE             0x370
+#define PARF_BLOCK_SLV_AXI_RD_BASE_HI          0x374
+#define PARF_BLOCK_SLV_AXI_RD_LIMIT            0x378
+#define PARF_BLOCK_SLV_AXI_RD_LIMIT_HI         0x37c
+#define PARF_ECAM_BASE                         0x380
+#define PARF_ECAM_BASE_HI                      0x384
 #define PARF_NO_SNOOP_OVERRIDE                 0x3d4
 #define PARF_ATU_BASE_ADDR                     0x634
 #define PARF_ATU_BASE_ADDR_HI                  0x638
@@ -87,6 +98,7 @@
 
 /* PARF_SYS_CTRL register fields */
 #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN       BIT(29)
+#define PCIE_ECAM_BLOCKER_EN                   BIT(26)
 #define MST_WAKEUP_EN                          BIT(13)
 #define SLV_WAKEUP_EN                          BIT(12)
 #define MSTR_ACLK_CGC_DIS                      BIT(10)
@@ -134,6 +146,9 @@
 /* PARF_LTSSM register fields */
 #define LTSSM_EN                               BIT(8)
 
+/* PARF_SLV_DBI_ELBI */
+#define SLV_DBI_ELBI_ADDR_BASE                 GENMASK(11, 0)
+
 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
 #define PARF_INT_ALL_LINK_UP                   BIT(13)
 #define PARF_INT_MSI_DEV_0_7                   GENMASK(30, 23)
@@ -312,6 +327,47 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
        qcom_perst_assert(pcie, false);
 }
 
+static void qcom_pci_config_ecam(struct dw_pcie_rp *pp)
+{
+       struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+       struct qcom_pcie *pcie = to_qcom_pcie(pci);
+       u64 addr, addr_end;
+       u32 val;
+
+       writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE);
+       writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI);
+
+       /*
+        * The only device on the root bus is a single Root Port. If we try to
+        * access any devices other than Device/Function 00.0 on Bus 0, the TLP
+        * will go outside of the controller to the PCI bus. But with CFG Shift
+        * Feature (ECAM) enabled in iATU, there is no guarantee that the
+        * response is going to be all F's. Hence, to make sure that the
+        * requester gets all F's response for accesses other than the Root
+        * Port, configure iATU to block the transactions starting from
+        * function 1 of the root bus to the end of the root bus (i.e., from
+        * dbi_base + 4KB to dbi_base + 1MB).
+        */
+       addr = pci->dbi_phys_addr + SZ_4K;
+       writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE);
+       writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI);
+
+       writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE);
+       writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI);
+
+       addr_end = pci->dbi_phys_addr + SZ_1M - 1;
+
+       writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT);
+       writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI);
+
+       writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT);
+       writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI);
+
+       val = readl_relaxed(pcie->parf + PARF_SYS_CTRL);
+       val |= PCIE_ECAM_BLOCKER_EN;
+       writel_relaxed(val, pcie->parf + PARF_SYS_CTRL);
+}
+
 static int qcom_pcie_start_link(struct dw_pcie *pci)
 {
        struct qcom_pcie *pcie = to_qcom_pcie(pci);
@@ -1284,6 +1340,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
 {
        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
        struct qcom_pcie *pcie = to_qcom_pcie(pci);
+       u16 offset;
        int ret;
 
        qcom_ep_reset_assert(pcie);
@@ -1292,6 +1349,17 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
        if (ret)
                return ret;
 
+       if (pp->ecam_enabled) {
+               /*
+                * Override ELBI when ECAM is enabled, as when ECAM is enabled,
+                * ELBI moves under the 'config' space.
+                */
+               offset = FIELD_GET(SLV_DBI_ELBI_ADDR_BASE, readl(pcie->parf + PARF_SLV_DBI_ELBI));
+               pci->elbi_base = pci->dbi_base + offset;
+
+               qcom_pci_config_ecam(pp);
+       }
+
        ret = qcom_pcie_phy_power_on(pcie);
        if (ret)
                goto err_deinit;