drm/amd: Use the first non-dGPU PCI device for BW limits

When bandwidth limits are looked up using pcie_bandwidth_available()
virtual links such as USB4 are analyzed which might not represent the
real speed. Furthermore devices may change speeds autonomously which
may introduce conditional variation to the results reported in the
status registers.

Instead look at the capabilities of first PCI device outside of
dGPU to decide upper limits that the dGPU will work at.

For eGPU this effectively means that it will use the speed of the link
partner.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2925#note_2145860
Link: https://www.usb.org/document-library/usb4r-specification-v20
      USB4 V2 with Errata and ECN through June 2023
      Section 11.2.1
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 151f8b950b726f55988e566ed61d506915fa3dbd..ec3bf949ee2ff6fe1d2c3ccfaadd6ee6a714ca6d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5737,6 +5737,39 @@ recover_end:
        return r;
 }
 
+/**
+ * amdgpu_device_partner_bandwidth - find the bandwidth of appropriate partner
+ *
+ * @adev: amdgpu_device pointer
+ * @speed: pointer to the speed of the link
+ * @width: pointer to the width of the link
+ *
+ * Evaluate the hierarchy to find the speed and bandwidth capabilities of the
+ * first physical partner to an AMD dGPU.
+ * This will exclude any virtual switches and links.
+ */
+static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev,
+                                           enum pci_bus_speed *speed,
+                                           enum pcie_link_width *width)
+{
+       struct pci_dev *parent = adev->pdev;
+
+       if (!speed || !width)
+               return;
+
+       *speed = PCI_SPEED_UNKNOWN;
+       *width = PCIE_LNK_WIDTH_UNKNOWN;
+
+       while ((parent = pci_upstream_bridge(parent))) {
+               /* skip upstream/downstream switches internal to dGPU*/
+               if (parent->vendor == PCI_VENDOR_ID_ATI)
+                       continue;
+               *speed = pcie_get_speed_cap(parent);
+               *width = pcie_get_width_cap(parent);
+               break;
+       }
+}
+
 /**
  * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
  *
@@ -5770,8 +5803,8 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
        if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
                return;
 
-       pcie_bandwidth_available(adev->pdev, NULL,
-                                &platform_speed_cap, &platform_link_width);
+       amdgpu_device_partner_bandwidth(adev, &platform_speed_cap,
+                                       &platform_link_width);
 
        if (adev->pm.pcie_gen_mask == 0) {
                /* asic caps */