]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
Merge tag 'tpm-030822' of https://source.denx.de/u-boot/custodians/u-boot-tpm
authorTom Rini <trini@konsulko.com>
Fri, 5 Aug 2022 12:01:32 +0000 (08:01 -0400)
committerTom Rini <trini@konsulko.com>
Fri, 5 Aug 2022 12:01:32 +0000 (08:01 -0400)
EFI_RNG_PROTOCOL with a TPM

436 files changed:
README
arch/Kconfig.nxp
arch/arm/cpu/armv7/ls102xa/Kconfig
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
arch/arm/dts/nuvoton-common-npcm7xx.dtsi
arch/arm/dts/nuvoton-npcm750-evb.dts
arch/arm/dts/nuvoton-npcm750.dtsi
arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi [new file with mode: 0644]
arch/arm/include/asm/arch-fsl-layerscape/config.h
arch/arm/include/asm/arch-ls102xa/config.h
arch/arm/mach-imx/mx7ulp/Kconfig
arch/arm/mach-k3/Makefile
arch/arm/mach-k3/common.c
arch/arm/mach-k3/common.h
arch/arm/mach-k3/include/mach/hardware.h
arch/arm/mach-k3/security.c
arch/powerpc/Kconfig
arch/powerpc/cpu/mpc85xx/Kconfig
arch/powerpc/include/asm/config_mpc85xx.h
arch/sh/lib/bootm.c
board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
board/atmel/at91sam9263ek/at91sam9263ek.c
board/buffalo/lsxl/lsxl.c
board/cobra5272/flash.c
board/freescale/common/fsl_validate.c
board/freescale/m5253demo/Kconfig
board/freescale/m5253demo/flash.c
board/freescale/mpc837xerdb/mpc837xerdb.c
board/freescale/p1010rdb/ddr.c
board/gardena/smart-gateway-mt7688/board.c
board/gdsys/mpc8308/sdram.c
board/ids/ids8313/ids8313.c
board/imgtec/malta/lowlevel_init.S
board/imgtec/malta/malta.c
board/keymile/km83xx/km83xx.c
board/logicpd/omap3som/omap3logic.c
board/siemens/taurus/taurus.c
board/socrates/socrates.c
board/toradex/common/tdx-cfg-block.c
boot/Kconfig
cmd/adc.c
cmd/bootm.c
cmd/cls.c
cmd/cramfs.c
cmd/cros_ec.c
cmd/extension_board.c
cmd/flash.c
cmd/jffs2.c
cmd/load.c
cmd/mem.c
cmd/mvebu/bubt.c
cmd/sf.c
common/board_r.c
common/flash.c
common/spl/Kconfig.vpl
common/spl/spl_mmc.c
common/update.c
configs/10m50_defconfig
configs/M5208EVBE_defconfig
configs/M5235EVB_Flash32_defconfig
configs/M5235EVB_defconfig
configs/M5249EVB_defconfig
configs/M5253DEMO_defconfig
configs/M5272C3_defconfig
configs/M5275EVB_defconfig
configs/M5282EVB_defconfig
configs/M53017EVB_defconfig
configs/M5329AFEE_defconfig
configs/M5329BFEE_defconfig
configs/M5373EVB_defconfig
configs/MCR3000_defconfig
configs/MPC837XERDB_defconfig
configs/MPC8548CDS_36BIT_defconfig
configs/MPC8548CDS_defconfig
configs/MPC8548CDS_legacy_defconfig
configs/P1010RDB-PA_36BIT_NAND_defconfig
configs/P1010RDB-PA_36BIT_NOR_defconfig
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
configs/P1010RDB-PA_NAND_defconfig
configs/P1010RDB-PA_NOR_defconfig
configs/P1010RDB-PA_SDCARD_defconfig
configs/P1010RDB-PA_SPIFLASH_defconfig
configs/P1010RDB-PB_36BIT_NAND_defconfig
configs/P1010RDB-PB_36BIT_NOR_defconfig
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
configs/P1010RDB-PB_NAND_defconfig
configs/P1010RDB-PB_NOR_defconfig
configs/P1010RDB-PB_SDCARD_defconfig
configs/P1010RDB-PB_SPIFLASH_defconfig
configs/P1020RDB-PC_36BIT_NAND_defconfig
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
configs/P1020RDB-PC_36BIT_defconfig
configs/P1020RDB-PC_NAND_defconfig
configs/P1020RDB-PC_SDCARD_defconfig
configs/P1020RDB-PC_SPIFLASH_defconfig
configs/P1020RDB-PC_defconfig
configs/P1020RDB-PD_NAND_defconfig
configs/P1020RDB-PD_SDCARD_defconfig
configs/P1020RDB-PD_SPIFLASH_defconfig
configs/P1020RDB-PD_defconfig
configs/P2020RDB-PC_36BIT_NAND_defconfig
configs/P2020RDB-PC_36BIT_SDCARD_defconfig
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
configs/P2020RDB-PC_36BIT_defconfig
configs/P2020RDB-PC_NAND_defconfig
configs/P2020RDB-PC_SDCARD_defconfig
configs/P2020RDB-PC_SPIFLASH_defconfig
configs/P2020RDB-PC_defconfig
configs/P2041RDB_NAND_defconfig
configs/P2041RDB_SDCARD_defconfig
configs/P2041RDB_SPIFLASH_defconfig
configs/P2041RDB_defconfig
configs/P3041DS_NAND_defconfig
configs/P3041DS_SDCARD_defconfig
configs/P3041DS_SPIFLASH_defconfig
configs/P3041DS_defconfig
configs/P4080DS_SDCARD_defconfig
configs/P4080DS_SPIFLASH_defconfig
configs/P4080DS_defconfig
configs/P5040DS_NAND_defconfig
configs/P5040DS_SDCARD_defconfig
configs/P5040DS_SPIFLASH_defconfig
configs/P5040DS_defconfig
configs/T1024RDB_NAND_defconfig
configs/T1024RDB_SDCARD_defconfig
configs/T1024RDB_SPIFLASH_defconfig
configs/T1024RDB_defconfig
configs/T1042D4RDB_NAND_defconfig
configs/T1042D4RDB_SDCARD_defconfig
configs/T1042D4RDB_SPIFLASH_defconfig
configs/T1042D4RDB_defconfig
configs/T2080QDS_NAND_defconfig
configs/T2080QDS_SDCARD_defconfig
configs/T2080QDS_SECURE_BOOT_defconfig
configs/T2080QDS_SPIFLASH_defconfig
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
configs/T2080QDS_defconfig
configs/T2080RDB_NAND_defconfig
configs/T2080RDB_SDCARD_defconfig
configs/T2080RDB_SPIFLASH_defconfig
configs/T2080RDB_defconfig
configs/T2080RDB_revD_NAND_defconfig
configs/T2080RDB_revD_SDCARD_defconfig
configs/T2080RDB_revD_SPIFLASH_defconfig
configs/T2080RDB_revD_defconfig
configs/T4240RDB_SDCARD_defconfig
configs/T4240RDB_defconfig
configs/amcore_defconfig
configs/astro_mcf5373l_defconfig
configs/at91sam9263ek_norflash_boot_defconfig
configs/at91sam9263ek_norflash_defconfig
configs/blanche_defconfig
configs/boston32r2_defconfig
configs/boston32r2el_defconfig
configs/boston32r6_defconfig
configs/boston32r6el_defconfig
configs/boston64r2_defconfig
configs/boston64r2el_defconfig
configs/boston64r6_defconfig
configs/boston64r6el_defconfig
configs/cobra5272_defconfig
configs/comtrend_ct5361_ram_defconfig
configs/comtrend_wap5813n_ram_defconfig
configs/da850evm_direct_nor_defconfig
configs/devkit3250_defconfig
configs/eb_cpu5282_defconfig
configs/eb_cpu5282_internal_defconfig
configs/edminiv2_defconfig
configs/ethernut5_defconfig
configs/gazerbeam_defconfig
configs/huawei_hg556a_ram_defconfig
configs/ids8313_defconfig
configs/imx8mm_evk_fspi_defconfig
configs/imx8ulp_evk_defconfig
configs/imx93_11x11_evk_defconfig
configs/integratorap_cm720t_defconfig
configs/integratorap_cm920t_defconfig
configs/integratorap_cm926ejs_defconfig
configs/integratorap_cm946es_defconfig
configs/integratorcp_cm1136_defconfig
configs/integratorcp_cm920t_defconfig
configs/integratorcp_cm926ejs_defconfig
configs/integratorcp_cm946es_defconfig
configs/kmcent2_defconfig
configs/kzm9g_defconfig
configs/ls1021aqds_ddr4_nor_defconfig
configs/ls1021aqds_ddr4_nor_lpuart_defconfig
configs/ls1021aqds_nand_defconfig
configs/ls1021aqds_nor_SECURE_BOOT_defconfig
configs/ls1021aqds_nor_defconfig
configs/ls1021aqds_nor_lpuart_defconfig
configs/ls1021aqds_sdcard_ifc_defconfig
configs/ls1021atwr_nor_SECURE_BOOT_defconfig
configs/ls1021atwr_nor_defconfig
configs/ls1021atwr_nor_lpuart_defconfig
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
configs/ls1021atwr_sdcard_ifc_defconfig
configs/ls1043aqds_defconfig
configs/ls1043aqds_lpuart_defconfig
configs/ls1043aqds_nand_defconfig
configs/ls1043aqds_nor_ddr3_defconfig
configs/ls1043aqds_sdcard_ifc_defconfig
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
configs/ls1043aqds_tfa_defconfig
configs/ls1043ardb_SECURE_BOOT_defconfig
configs/ls1043ardb_defconfig
configs/ls1043ardb_nand_SECURE_BOOT_defconfig
configs/ls1043ardb_nand_defconfig
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
configs/ls1043ardb_sdcard_defconfig
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
configs/ls1043ardb_tfa_defconfig
configs/ls1046aqds_SECURE_BOOT_defconfig
configs/ls1046aqds_defconfig
configs/ls1046aqds_lpuart_defconfig
configs/ls1046aqds_nand_defconfig
configs/ls1046aqds_sdcard_ifc_defconfig
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
configs/ls1046aqds_tfa_defconfig
configs/ls1088aqds_defconfig
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
configs/ls1088aqds_qspi_defconfig
configs/ls1088aqds_sdcard_ifc_defconfig
configs/ls1088aqds_sdcard_qspi_defconfig
configs/ls1088aqds_tfa_defconfig
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
configs/ls1088ardb_qspi_defconfig
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
configs/ls1088ardb_sdcard_qspi_defconfig
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
configs/ls1088ardb_tfa_defconfig
configs/ls2080aqds_SECURE_BOOT_defconfig
configs/ls2080aqds_defconfig
configs/ls2080aqds_nand_defconfig
configs/ls2080aqds_qspi_defconfig
configs/ls2080aqds_sdcard_defconfig
configs/ls2080ardb_SECURE_BOOT_defconfig
configs/ls2080ardb_defconfig
configs/ls2080ardb_nand_defconfig
configs/ls2081ardb_defconfig
configs/ls2088aqds_tfa_defconfig
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
configs/ls2088ardb_qspi_defconfig
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
configs/ls2088ardb_tfa_defconfig
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
configs/lx2160aqds_tfa_defconfig
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
configs/lx2160ardb_tfa_defconfig
configs/lx2160ardb_tfa_stmm_defconfig
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
configs/lx2162aqds_tfa_defconfig
configs/lx2162aqds_tfa_verified_boot_defconfig
configs/malta64_defconfig
configs/malta64el_defconfig
configs/malta_defconfig
configs/maltael_defconfig
configs/mccmon6_nor_defconfig
configs/mccmon6_sd_defconfig
configs/microblaze-generic_defconfig
configs/octeon_ebb7304_defconfig
configs/omap35_logic_somlv_defconfig
configs/omap3_logic_somlv_defconfig
configs/pg_wcom_expu1_defconfig
configs/pg_wcom_expu1_update_defconfig
configs/pg_wcom_seli8_defconfig
configs/pg_wcom_seli8_update_defconfig
configs/pm9261_defconfig
configs/pm9263_defconfig
configs/qemu_arm64_defconfig
configs/qemu_arm_defconfig
configs/r2dplus_defconfig
configs/r8a77990_ebisu_defconfig
configs/r8a77995_draak_defconfig
configs/rcar3_salvator-x_defconfig
configs/rcar3_ulcb_defconfig
configs/sama5d3xek_mmc_defconfig
configs/sama5d3xek_nandflash_defconfig
configs/sama5d3xek_spiflash_defconfig
configs/sfr_nb4-ser_ram_defconfig
configs/socrates_defconfig
configs/stm32746g-eval_defconfig
configs/stm32746g-eval_spl_defconfig
configs/stm32f429-discovery_defconfig
configs/stm32f429-evaluation_defconfig
configs/stm32f469-discovery_defconfig
configs/stm32f746-disco_defconfig
configs/stm32f746-disco_spl_defconfig
configs/stm32f769-disco_defconfig
configs/stm32f769-disco_spl_defconfig
configs/ten64_tfa_defconfig
configs/total_compute_defconfig
configs/vexpress_aemv8a_juno_defconfig
configs/vexpress_aemv8a_semi_defconfig
configs/vexpress_ca9x4_defconfig
configs/xilinx_zynq_virt_defconfig
configs/xtfpga_defconfig
configs/zynq_cse_nor_defconfig
doc/arch/m68k.rst
drivers/ddr/fsl/Kconfig
drivers/dfu/dfu_sf.c
drivers/fastboot/fb_command.c
drivers/fastboot/fb_mmc.c
drivers/fastboot/fb_nand.c
drivers/gpio/Kconfig
drivers/misc/cros_ec.c
drivers/mtd/Kconfig
drivers/mtd/Makefile
drivers/mtd/pic32_flash.c [deleted file]
drivers/mtd/spi/sf_dataflash.c
drivers/mtd/spi/sf_mtd.c
drivers/mtd/spi/spi-nor-core.c
drivers/net/Kconfig
drivers/net/fm/Makefile
drivers/net/phy/Kconfig
drivers/pwm/Kconfig
drivers/xen/events.c
env/flash.c
env/sf.c
fs/cramfs/cramfs.c
fs/jffs2/jffs2_1pass.c
include/configs/10m50_devboard.h
include/configs/3c120_devboard.h
include/configs/M5208EVBE.h
include/configs/M5235EVB.h
include/configs/M5249EVB.h
include/configs/M5253DEMO.h
include/configs/M5272C3.h
include/configs/M5275EVB.h
include/configs/M5282EVB.h
include/configs/M53017EVB.h
include/configs/M5329EVB.h
include/configs/M5373EVB.h
include/configs/MCR3000.h
include/configs/MPC837XERDB.h
include/configs/MPC8548CDS.h
include/configs/P1010RDB.h
include/configs/P2041RDB.h
include/configs/T102xRDB.h
include/configs/T104xRDB.h
include/configs/T208xQDS.h
include/configs/T208xRDB.h
include/configs/T4240RDB.h
include/configs/am335x_evm.h
include/configs/am3517_evm.h
include/configs/amcore.h
include/configs/armadillo-800eva.h
include/configs/astro_mcf5373l.h
include/configs/at91sam9263ek.h
include/configs/ax25-ae350.h
include/configs/blanche.h
include/configs/bmips_bcm6338.h
include/configs/bmips_bcm6348.h
include/configs/bmips_bcm6358.h
include/configs/bmips_bcm6368.h
include/configs/boston.h
include/configs/brppt1.h
include/configs/chiliboard.h
include/configs/cm_t335.h
include/configs/cobra5272.h
include/configs/corenet_ds.h
include/configs/da850evm.h
include/configs/devkit3250.h
include/configs/dra7xx_evm.h
include/configs/draak.h
include/configs/eb_cpu5282.h
include/configs/ebisu.h
include/configs/edminiv2.h
include/configs/etamin.h
include/configs/ethernut5.h
include/configs/gazerbeam.h
include/configs/ids8313.h
include/configs/imx27lite-common.h
include/configs/integrator-common.h
include/configs/integratorap.h
include/configs/integratorcp.h
include/configs/km/km-mpc83xx.h
include/configs/km/km-powerpc.h
include/configs/km/km_arm.h
include/configs/km/pg-wcom-ls102xa.h
include/configs/kmcent2.h
include/configs/kzm9g.h
include/configs/ls1012aqds.h
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h
include/configs/ls1043a_common.h
include/configs/ls1043aqds.h
include/configs/ls1043ardb.h
include/configs/ls1046aqds.h
include/configs/ls1088aqds.h
include/configs/ls1088ardb.h
include/configs/ls2080a_common.h
include/configs/ls2080aqds.h
include/configs/ls2080ardb.h
include/configs/lsxl.h
include/configs/lx2160a_common.h
include/configs/malta.h
include/configs/mccmon6.h
include/configs/microblaze-generic.h
include/configs/mx6sabreauto.h
include/configs/octeon_ebb7304.h
include/configs/omap3_beagle.h
include/configs/omap3_evm.h
include/configs/omap3_logic.h
include/configs/p1_p2_rdb_pc.h
include/configs/pm9261.h
include/configs/pm9263.h
include/configs/qemu-arm.h
include/configs/qemu-ppce500.h
include/configs/r2dplus.h
include/configs/s5p4418_nanopi2.h
include/configs/salvator-x.h
include/configs/sama5d3xek.h
include/configs/siemens-am33x-common.h
include/configs/socrates.h
include/configs/stm32f429-discovery.h
include/configs/stm32f429-evaluation.h
include/configs/stm32f469-discovery.h
include/configs/stm32f746-disco.h
include/configs/total_compute.h
include/configs/ulcb.h
include/configs/vexpress_aemv8.h
include/configs/vexpress_common.h
include/configs/xtfpga.h
include/configs/zynq-common.h
include/flash.h
include/mtd/cfi_flash.h
net/nfs.c
net/tftp.c
post/drivers/flash.c
scripts/config_whitelist.txt
tools/Makefile
tools/sunxi_toc0.c

diff --git a/README b/README
index 623f35907217ff17881e1b1f71438238abf3965a..6b6f7227336a1fff884e755ed59cdebdec371881 100644 (file)
--- a/README
+++ b/README
@@ -396,12 +396,6 @@ The following options need to be configured:
                Board config to use DDR3L. It can be enabled for SoCs with
                DDR3L controllers.
 
-               CONFIG_SYS_FSL_IFC_BE
-               Defines the IFC controller register space as Big Endian
-
-               CONFIG_SYS_FSL_IFC_LE
-               Defines the IFC controller register space as Little Endian
-
                CONFIG_SYS_FSL_IFC_CLK_DIV
                Defines divider of platform clock(clock input to IFC controller).
 
@@ -419,11 +413,6 @@ The following options need to be configured:
                same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
                it could be different for ARM SoCs.
 
-               CONFIG_SYS_FSL_DDR_INTLV_256B
-               DDR controller interleaving on 256-byte. This is a special
-               interleaving mode, handled by Dickens for Freescale layerscape
-               SoCs with ARM core.
-
                CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
                Number of controllers used as main memory.
 
@@ -1728,38 +1717,10 @@ Configuration Settings:
                Enables allocating and saving a kernel copy of the bd_info in
                space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
 
-- CONFIG_SYS_MAX_FLASH_SECT:
-               Max number of sectors on a Flash chip
-
-- CONFIG_SYS_FLASH_ERASE_TOUT:
-               Timeout for Flash erase operations (in ms)
-
-- CONFIG_SYS_FLASH_WRITE_TOUT:
-               Timeout for Flash write operations (in ms)
-
-- CONFIG_SYS_FLASH_LOCK_TOUT
-               Timeout for Flash set sector lock bit operation (in ms)
-
-- CONFIG_SYS_FLASH_UNLOCK_TOUT
-               Timeout for Flash clear lock bits operation (in ms)
-
 - CONFIG_SYS_FLASH_PROTECTION
                If defined, hardware flash sectors protection is used
                instead of U-Boot software protection.
 
-- CONFIG_SYS_DIRECT_FLASH_TFTP:
-
-               Enable TFTP transfers directly to flash memory;
-               without this option such a download has to be
-               performed in two steps: (1) download to RAM, and (2)
-               copy from RAM to flash.
-
-               The two-step approach is usually more reliable, since
-               you can check if the download worked before you erase
-               the flash, but in some situations (when system RAM is
-               too limited to allow for a temporary copy of the
-               downloaded image) this option may be very useful.
-
 - CONFIG_SYS_FLASH_CFI:
                Define if the flash driver uses extra elements in the
                common flash structure for storing flash geometry.
@@ -1780,12 +1741,6 @@ Configuration Settings:
                s29ws-n MirrorBit flash has non-standard addresses for buffered
                write commands.
 
-- CONFIG_SYS_FLASH_QUIET_TEST
-               If this option is defined, the common CFI flash doesn't
-               print it's warning upon not recognized FLASH banks. This
-               is useful, if some of the configured banks are only
-               optionally available.
-
 - CONFIG_FLASH_SHOW_PROGRESS
                If defined (must be an integer), print out countdown
                digits and dots.  Recommended value: 45 (9..1) for 80
index d3ebbff43be18bee3c48c6d2b253d813297b8c89..a96245c37230cb4271f5294710b542805614fa37 100644 (file)
@@ -227,6 +227,12 @@ config VOL_MONITOR_ISL68233_SET
 
 endif
 
+config SYS_FSL_ESDHC_BE
+       bool
+
+config SYS_FSL_IFC_BE
+       bool
+
 config FSL_QIXIS
        bool "Enable QIXIS support"
        depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
index a901360fa7d8e6db0716288fd26f6be9b4c5a598..e75a895e0086c71ebe9a1dec09ff3d97e4051781 100644 (file)
@@ -3,6 +3,7 @@ config ARCH_LS1021A
        select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
        select SYS_FSL_DDR_BE if SYS_FSL_DDR
        select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
+       select SYS_FSL_IFC_BE
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A008407
        select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
@@ -12,6 +13,7 @@ config ARCH_LS1021A
        select SYS_FSL_ERRATUM_A009798 if USB
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
+       select SYS_FSL_ESDHC_BE
        select SYS_FSL_HAS_CCI400
        select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
        select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
index 602b624dca529fa5e4277ecd798a8080987d28e6..1f86070b8a2c2343050974bd425d74cb4056722f 100644 (file)
@@ -323,6 +323,11 @@ config ARCH_LX2160A
 config FSL_LSCH2
        bool
        select SKIP_LOWLEVEL_INIT
+       select SYS_FSL_CCSR_GUR_BE
+       select SYS_FSL_CCSR_SCFG_BE
+       select SYS_FSL_ESDHC_BE
+       select SYS_FSL_IFC_BE
+       select SYS_FSL_PEX_LUT_BE
        select SYS_FSL_HAS_CCI400
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
@@ -330,11 +335,40 @@ config FSL_LSCH2
 
 config FSL_LSCH3
        select ARCH_MISC_INIT
+       select SYS_FSL_CCSR_GUR_LE
+       select SYS_FSL_CCSR_SCFG_LE
+       select SYS_FSL_ESDHC_LE
+       select SYS_FSL_IFC_LE
+       select SYS_FSL_PEX_LUT_LE
        bool
 
 config NXP_LSCH3_2
        bool
 
+config SYS_FSL_CCSR_GUR_BE
+       bool
+
+config SYS_FSL_CCSR_SCFG_BE
+       bool
+
+config SYS_FSL_PEX_LUT_BE
+       bool
+
+config SYS_FSL_CCSR_GUR_LE
+       bool
+
+config SYS_FSL_CCSR_SCFG_LE
+       bool
+
+config SYS_FSL_ESDHC_LE
+       bool
+
+config SYS_FSL_IFC_LE
+       bool
+
+config SYS_FSL_PEX_LUT_LE
+       bool
+
 menu "Layerscape architecture"
        depends on FSL_LSCH2 || FSL_LSCH3
 
index 02ee4d78e25acbac23254cd39eac817b39c0b601..feb88872fc712efb9e30f99c957c808f5edb003d 100644 (file)
                #size-cells = <1>;
                compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd";
                ranges = <0 0xf0010000 0x8000>;
+               reg = <0xf0010000 0x8000>;
+               syscon-gcr = <&gcr>;
+               syscon-rst = <&rst>;
                gpio0: gpio@f0010000 {
                        gpio-controller;
                        #gpio-cells = <2>;
index 3e4abe661005075db49e5eb22806f10c9942d5ba..d4667a1df46f8fc401d3f3c065665f72683549f5 100644 (file)
@@ -12,8 +12,8 @@
        compatible = "nuvoton,npcm750-evb", "nuvoton,npcm750";
 
        aliases {
-               ethernet2 = &gmac0;
-               ethernet3 = &gmac1;
+               eth0 = &emc0;
+               eth1 = &gmac0;
                serial0 = &serial0;
                serial1 = &serial1;
                serial2 = &serial2;
                i2c13 = &i2c13;
                i2c14 = &i2c14;
                i2c15 = &i2c15;
-               spi0 = &spi0;
-               spi1 = &spi1;
-               fiu0 = &fiu0;
-               fiu1 = &fiu3;
-               fiu2 = &fiux;
+               spi0 = &fiu0;
+               spi1 = &fiu3;
+               spi2 = &fiux;
+               spi3 = &spi0;
+               spi4 = &spi1;
        };
 
        chosen {
        };
 };
 
-&gmac0 {
-       phy-mode = "rgmii-id";
+&udc0 {
        status = "okay";
+       phys = <&usbphy1 0>;
 };
 
-&gmac1 {
+&gmac0 {
        phy-mode = "rgmii-id";
+       snps,eee-force-disable;
        status = "okay";
 };
 
 &ehci1 {
        status = "okay";
+       phys = <&usbphy2 3>;
 };
 
 &fiu0 {
        spix-mode;
 };
 
-&watchdog1 {
+&watchdog0 {
        status = "okay";
 };
 
        status = "okay";
 };
 
+&sha {
+       status = "okay";
+};
+
+&aes {
+       status = "okay";
+};
+
 &serial0 {
        status = "okay";
        clock-frequency = <24000000>;
                        &pin255_input>;
 };
 
+&ehci1 {
+       status = "okay";
+       phys = <&usbphy2 3>;
+};
+
+&otp {
+       status = "okay";
+};
+
+&usbphy1 {
+       status = "okay";
+};
+
+&usbphy2 {
+       status = "okay";
+};
+
+&emc0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&r1_pins
+                               &r1err_pins>;
+       fixed-link {
+                       speed = <100>;
+                       full-dulpex;
+       };
+};
+
+&sdhci0 {
+       status = "okay";
+};
index 13eee0fe564201144a6c3b49c821ebfb7204bbe2..c286353832145399c3969b2fe8b1fafa6430fde9 100644 (file)
@@ -3,6 +3,7 @@
 // Copyright 2018 Google, Inc.
 
 #include "nuvoton-common-npcm7xx.dtsi"
+#include "nuvoton-npcm7xx-u-boot.dtsi"
 
 / {
        #address-cells = <1>;
diff --git a/arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi
new file mode 100644 (file)
index 0000000..c547e43
--- /dev/null
@@ -0,0 +1,287 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       interrupt-parent = <&gic>;
+
+       wdt-reboot {
+                compatible = "wdt-reboot";
+                wdt = <&watchdog0>;
+        };
+
+       ahb {
+               udc0:udc@f0830100 {
+                       compatible = "nuvoton,npcm750-udc";
+                       reg = <0xf0830100 0x200
+                              0xfffd0000 0x800>;
+                       interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+                       resets = <&rstc NPCM7XX_RESET_IPSRST3 NPCM7XX_RESET_UDC0>;
+                       status = "disabled";
+                       clocks = <&clk NPCM7XX_CLK_SU>;
+                       clock-names = "clk_usb_bridge";
+               };
+
+               udc1:udc@f0831100 {
+                       compatible = "nuvoton,npcm750-udc";
+                       reg = <0xf0831100 0x200
+                              0xfffd0800 0x800>;
+                       interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clocks = <&clk NPCM7XX_CLK_SU>;
+                       clock-names = "clk_usb_bridge";
+               };
+
+               udc2: udc@f0832100 {
+                       compatible = "nuvoton,npcm750-udc";
+                       reg = <0xf0832100 0x200
+                              0xfffd1000 0x800>;
+                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clocks = <&clk NPCM7XX_CLK_SU>;
+                       clock-names = "clk_usb_bridge";
+               };
+
+               udc3: udc@f0833100 {
+                       compatible = "nuvoton,npcm750-udc";
+                       reg = <0xf0833100 0x200
+                              0xfffd1800 0x800>;
+                       interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clocks = <&clk NPCM7XX_CLK_SU>;
+                       clock-names = "clk_usb_bridge";
+               };
+
+               udc4: udc@f0834100 {
+                       compatible = "nuvoton,npcm750-udc";
+                       reg = <0xf0834100 0x200
+                              0xfffd2000 0x800>;
+                       interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clocks = <&clk NPCM7XX_CLK_SU>;
+                       clock-names = "clk_usb_bridge";
+               };
+
+               udc5: udc@f0835100 {
+                       compatible = "nuvoton,npcm750-udc";
+                       reg = <0xf0835100 0x200
+                              0xfffd2800 0x800>;
+                       interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clocks = <&clk NPCM7XX_CLK_SU>;
+                       clock-names = "clk_usb_bridge";
+               };
+
+               udc6: udc@f0836100 {
+                       compatible = "nuvoton,npcm750-udc";
+                       reg = <0xf0836100 0x200
+                              0xfffd3000 0x800>;
+                       interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clocks = <&clk NPCM7XX_CLK_SU>;
+                       clock-names = "clk_usb_bridge";
+               };
+
+               udc7: udc@f0837100 {
+                       compatible = "nuvoton,npcm750-udc";
+                       reg = <0xf0837100 0x200
+                              0xfffd3800 0x800>;
+                       interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clocks = <&clk NPCM7XX_CLK_SU>;
+                       clock-names = "clk_usb_bridge";
+               };
+
+               udc8: udc@f0838100 {
+                       compatible = "nuvoton,npcm750-udc";
+                       reg = <0xf0838100 0x200
+                              0xfffd4000 0x800>;
+                       interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clocks = <&clk NPCM7XX_CLK_SU>;
+                       clock-names = "clk_usb_bridge";
+               };
+
+               udc9: udc@f0839100 {
+                       compatible = "nuvoton,npcm750-udc";
+                       reg = <0xf0839100 0x200
+                              0xfffd4800 0x800>;
+                       interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       clocks = <&clk NPCM7XX_CLK_SU>;
+                       clock-names = "clk_usb_bridge";
+               };
+
+               emc0: eth@f0825000 {
+                       device_type = "network";
+                       compatible = "nuvoton,npcm750-emc";
+                       reg = <0xf0825000 0x1000>;
+                       phy-mode = "rmii";
+                       id = <0>;
+                       syscon-gcr = <&gcr>;
+                       interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk NPCM7XX_CLK_AHB>;
+                       clock-names = "clk_emc";
+                       resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_EMC1>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&r1_pins
+                                       &r1md_pins>;
+                       status = "disabled";
+               };
+
+               ohci1: ohci@f0807000 {
+                       compatible = "nuvoton,npcm750-ohci";
+                       reg = <0xf0807000 0x1000>;
+                       interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                       resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_USB_HOST>;
+                       status = "disabled";
+               };
+
+               usbphy {
+                       compatible = "simple-bus", "nuvoton,npcm750-usb-phy";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       syscon = <&gcr>;
+                       usbphy1: usbphy1 {
+                               compatible = "nuvoton,npcm750-usb-phy";
+                               #phy-cells = <1>;
+                               reg = <1>;
+                               resets = <&rstc NPCM7XX_RESET_IPSRST3 NPCM7XX_RESET_USB_PHY_1>;
+                               status = "disabled";
+                       };
+                       usbphy2: usbphy2 {
+                               compatible = "nuvoton,npcm750-usb-phy";
+                               #phy-cells = <1>;
+                               reg = <2>;
+                               resets =<&rstc NPCM7XX_RESET_IPSRST3 NPCM7XX_RESET_USB_PHY_2>;
+                               status = "disabled";
+                       };
+               };
+
+               sdhci0: sdhci0@f0842000 {
+                       compatible = "nuvoton,npcm750-sdhci";
+                       reg = <0xf0842000 0x200>;
+                       index = <0x0>;
+                       bus-width = <0x8>;
+                       cap-mmc-highspeed;
+                       interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk NPCM7XX_CLK_SDHC>;
+                       clock-frequency = <50000000>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&mmc_pins
+                               &mmc8_pins>;
+                       status = "disabled";
+               };
+
+               sdhci1: sdhci1@f0840000 {
+                       compatible = "nuvoton,npcm750-sdhci";
+                       reg = <0xf0840000 0x2000>;
+                       index = <0x1>;
+                       bus-width = <0x4>;
+                       cap-mmc-highspeed;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&sd1_pins>;
+                       status = "disabled";
+               };
+
+               aes: aes@f0858000 {
+                       compatible = "nuvoton,npcm750-aes";
+                       reg = <0xf0858000 0x1000>;
+                       clocks = <&clk NPCM7XX_CLK_AHB>;
+                       clock-names = "clk_ahb";
+                       status = "disabled";
+               };
+
+               sha: sha@f085a000 {
+                       compatible = "nuvoton,npcm750-sha";
+                       reg = <0xf085a000 0x1000>;
+                       clocks = <&clk NPCM7XX_CLK_AHB>;
+                       clock-names = "clk_ahb";
+                       status = "disabled";
+               };
+
+               //ehci1
+               usb@f0806000 {
+                       resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_USB_HOST>;
+               };
+
+               apb {
+                       otp:otp@189000 {
+                               compatible = "nuvoton,npcm750-otp";
+                               reg = <0x189000 0x1000
+                                          0x18a000 0x1000>;
+                               status = "disabled";
+                               clocks = <&clk NPCM7XX_CLK_APB4>;
+                               clock-names = "clk_apb4";
+                       };
+
+                       rng@b000 {
+                               clocks = <&clk NPCM7XX_CLK_APB1>;
+                       };
+                       gpio_0: gpio0@10000 {
+                                compatible = "nuvoton,npcm-gpio";
+                                reg = <0x10000 0xB0>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                gpio-bank-name = "gpio0";
+                        };
+
+                        gpio_1: gpio1@11000 {
+                                compatible = "nuvoton,npcm-gpio";
+                                reg = <0x11000 0xB0>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                gpio-bank-name = "gpio1";
+                        };
+
+                        gpio_2: gpio2@12000 {
+                                compatible = "nuvoton,npcm-gpio";
+                                reg = <0x12000 0xB0>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                gpio-bank-name = "gpio2";
+                        };
+                       gpio_3: gpio3@13000 {
+                                compatible = "nuvoton,npcm-gpio";
+                                reg = <0x13000 0xB0>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                gpio-bank-name = "gpio3";
+                        };
+
+                        gpio_4: gpio4@14000 {
+                                compatible = "nuvoton,npcm-gpio";
+                                reg = <0x14000 0xB0>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                gpio-bank-name = "gpio4";
+                        };
+
+                        gpio_5: gpio5@15000 {
+                                compatible = "nuvoton,npcm-gpio";
+                                reg = <0x15000 0xB0>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                gpio-bank-name = "gpio5";
+                        };
+
+                        gpio_6: gpio6@16000 {
+                                compatible = "nuvoton,npcm-gpio";
+                                reg = <0x16000 0xB0>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                gpio-bank-name = "gpio6";
+                        };
+                       gpio_7: gpio7@17000 {
+                                compatible = "nuvoton,npcm-gpio";
+                                reg = <0x17000 0xB0>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                gpio-bank-name = "gpio7";
+                        };
+
+               };
+       };
+};
+
index cd795d6919ac49607e306a7e36e3634776860e2f..1791b978704de7bb4b93f74f6e1524206a9b164d 100644 (file)
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
-#define CONFIG_SYS_FSL_CCSR_SCFG_LE
-#define CONFIG_SYS_FSL_ESDHC_LE
-#define CONFIG_SYS_FSL_IFC_LE
-#define CONFIG_SYS_FSL_PEX_LUT_LE
-
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE                      0x06000000
 #define GICR_BASE                      0x06100000
@@ -55,9 +47,6 @@
 /* SMMU Defintions */
 #define SMMU_BASE                      0x05000000 /* GR0 Base */
 
-/* DCFG - GUR */
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
-
 /* Cache Coherent Interconnect */
 #define CCI_MN_BASE                    0x04000000
 #define CCI_MN_RNF_NODEID_LIST         0x180
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
-#define CONFIG_SYS_FSL_CCSR_SCFG_LE
-#define CONFIG_SYS_FSL_ESDHC_LE
-#define CONFIG_SYS_FSL_IFC_LE
-#define CONFIG_SYS_FSL_PEX_LUT_LE
-
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
 /* DCFG - GUR */
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
 #define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE       0x00200000 /* 2M space */
 #define L1_CACHE_SHIFT         6
 #define L1_CACHE_BYTES         BIT(L1_CACHE_SHIFT)
 #endif
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER       2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1, 1, 1, 4, 4, 4, 4 }
 #define CONFIG_SYS_FSL_NUM_CC_PLLS             4
 
 #define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
-#define CONFIG_SYS_FSL_CCSR_SCFG_LE
-#define CONFIG_SYS_FSL_ESDHC_LE
-#define CONFIG_SYS_FSL_PEX_LUT_LE
-
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE                              0x06000000
 #define GICR_BASE                              0x06200000
 #define SMMU_BASE                              0x05000000 /* GR0 Base */
 
 /* DCFG - GUR */
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
-#define CONFIG_SYS_FSL_CCSR_SCFG_LE
-#define CONFIG_SYS_FSL_ESDHC_LE
-#define CONFIG_SYS_FSL_PEX_LUT_LE
-
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
 /* SEC */
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 
 /* DCFG - GUR */
-#define CONFIG_SYS_FSL_CCSR_GUR_LE
 
 #elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
 #define DCSR_DCFG_SBEESR2                      0x20140534
 #define DCSR_DCFG_MBEESR2                      0x20140544
 
-#define CONFIG_SYS_FSL_CCSR_SCFG_BE
-#define CONFIG_SYS_FSL_ESDHC_BE
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
-#define CONFIG_SYS_FSL_CCSR_GUR_BE
-#define CONFIG_SYS_FSL_PEX_LUT_BE
 
 /* SoC related */
 #ifdef CONFIG_ARCH_LS1043A
-#define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FSL_QMAN_V3
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               7
 #define MAX_QE_RISC            1
 #define QE_NUM_OF_SNUM         28
 
-#define CONFIG_SYS_FSL_IFC_BE
-
 /* SMMU Defintions */
 #define SMMU_BASE              0x09000000
 
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
 #elif defined(CONFIG_ARCH_LS1046A)
-#define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FSL_QMAN_V3
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               8
 #define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
 
-#define CONFIG_SYS_FSL_IFC_BE
-
 /* SMMU Defintions */
 #define SMMU_BASE              0x09000000
 
index e5f61ea4a6ee65cc3b014834a828cb7a501647d5..868456f1f139f1adb1705a017ccf193c85b60bb9 100644 (file)
@@ -79,8 +79,6 @@
 #define CONFIG_MAX_MEM_MAPPED                  ((phys_size_t)2 << 30)
 #endif
 
-#define CONFIG_SYS_FSL_IFC_BE
-#define CONFIG_SYS_FSL_ESDHC_BE
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
 
index 615d75bdd0bf6b3d452ce4782f3e1430083c17ee..632c4bf6fa5e78091ecfdace72247a71cecc89bd 100644 (file)
@@ -24,16 +24,16 @@ config TARGET_MX7ULP_COM
        select MX7ULP
        select SYS_ARCH_TIMER
        select SPL_DM if SPL
-       select SPL_GPIO_SUPPORT if SPL
+       select SPL_GPIO if SPL
        select SPL_LIBCOMMON_SUPPORT if SPL
        select SPL_LIBDISK_SUPPORT if SPL
        select SPL_LIBGENERIC_SUPPORT if SPL
-       select SPL_MMC_SUPPORT if SPL
+       select SPL_MMC if SPL
        select SPL_OF_CONTROL if SPL
        select SPL_OF_LIBFDT if SPL
        select SPL_PINCTRL if SPL
        select SPL_SEPARATE_BSS if SPL
-       select SPL_SERIAL_SUPPORT if SPL
+       select SPL_SERIAL if SPL
        select SUPPORT_SPL
 
 config TARGET_MX7ULP_EVK
index 0dce8802dbbf15bc488e1cd23a083b4b59f01833..6ac2b61c3d7ba4c2ad7ec16704088995aaf93022 100644 (file)
@@ -8,7 +8,6 @@ obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
 obj-$(CONFIG_SOC_K3_AM625) += am62x/
 obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
-obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
 obj-$(CONFIG_ARM64) += cache.o
 ifeq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_SOC_K3_AM654) += am654_init.o
@@ -18,4 +17,4 @@ obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
 obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
 obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
 endif
-obj-y += common.o
+obj-y += common.o security.o
index 70f6444e7988cd45a02ae521df576e7eef81b80d..3962f2800f9c4e01075677d064c377b9a82700b4 100644 (file)
@@ -290,9 +290,7 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image,
        }
 #endif
 
-#if IS_ENABLED(CONFIG_TI_SECURE_DEVICE)
        ti_secure_image_post_process(p_image, p_size);
-#endif
 }
 #endif
 
@@ -396,7 +394,54 @@ void reset_cpu(void)
 }
 #endif
 
+enum k3_device_type get_device_type(void)
+{
+       u32 sys_status = readl(K3_SEC_MGR_SYS_STATUS);
+
+       u32 sys_dev_type = (sys_status & SYS_STATUS_DEV_TYPE_MASK) >>
+                       SYS_STATUS_DEV_TYPE_SHIFT;
+
+       u32 sys_sub_type = (sys_status & SYS_STATUS_SUB_TYPE_MASK) >>
+                       SYS_STATUS_SUB_TYPE_SHIFT;
+
+       switch (sys_dev_type) {
+       case SYS_STATUS_DEV_TYPE_GP:
+               return K3_DEVICE_TYPE_GP;
+       case SYS_STATUS_DEV_TYPE_TEST:
+               return K3_DEVICE_TYPE_TEST;
+       case SYS_STATUS_DEV_TYPE_EMU:
+               return K3_DEVICE_TYPE_EMU;
+       case SYS_STATUS_DEV_TYPE_HS:
+               if (sys_sub_type == SYS_STATUS_SUB_TYPE_VAL_FS)
+                       return K3_DEVICE_TYPE_HS_FS;
+               else
+                       return K3_DEVICE_TYPE_HS_SE;
+       default:
+               return K3_DEVICE_TYPE_BAD;
+       }
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
+static const char *get_device_type_name(void)
+{
+       enum k3_device_type type = get_device_type();
+
+       switch (type) {
+       case K3_DEVICE_TYPE_GP:
+               return "GP";
+       case K3_DEVICE_TYPE_TEST:
+               return "TEST";
+       case K3_DEVICE_TYPE_EMU:
+               return "EMU";
+       case K3_DEVICE_TYPE_HS_FS:
+               return "HS-FS";
+       case K3_DEVICE_TYPE_HS_SE:
+               return "HS-SE";
+       default:
+               return "BAD";
+       }
+}
+
 int print_cpuinfo(void)
 {
        struct udevice *soc;
@@ -418,9 +463,11 @@ int print_cpuinfo(void)
 
        ret = soc_get_revision(soc, name, 64);
        if (!ret) {
-               printf("%s\n", name);
+               printf("%s ", name);
        }
 
+       printf("%s\n", get_device_type_name());
+
        return 0;
 }
 #endif
index e81b70d7c36824804e1495430c0eb0d5cc491986..8f38fcef7f01033cf4941ace8b6e15a0d9316e84 100644 (file)
@@ -18,6 +18,15 @@ struct fwl_data {
        u16 regions;
 };
 
+enum k3_device_type {
+       K3_DEVICE_TYPE_BAD,
+       K3_DEVICE_TYPE_GP,
+       K3_DEVICE_TYPE_TEST,
+       K3_DEVICE_TYPE_EMU,
+       K3_DEVICE_TYPE_HS_FS,
+       K3_DEVICE_TYPE_HS_SE,
+};
+
 void setup_k3_mpu_regions(void);
 int early_console_init(void);
 void disable_linefill_optimization(void);
@@ -27,4 +36,5 @@ void k3_sysfw_print_ver(void);
 void spl_enable_dcache(void);
 void mmr_unlock(phys_addr_t base, u32 partition);
 bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
+enum k3_device_type get_device_type(void);
 void ti_secure_image_post_process(void **p_image, size_t *p_size);
index 7bbd5c22c980c39c1c7a59ed1f7a15a4f118e6b2..028482b3b6d33eb71f610d86fcdd53492fb5ae1e 100644 (file)
 #define JTAG_ID_VARIANT_MASK   (0xf << 28)
 #define JTAG_ID_PARTNO_SHIFT   12
 #define JTAG_ID_PARTNO_MASK    (0xffff << 12)
+#define K3_SEC_MGR_SYS_STATUS          0x44234100
+#define SYS_STATUS_DEV_TYPE_SHIFT      0
+#define SYS_STATUS_DEV_TYPE_MASK       (0xf)
+#define SYS_STATUS_DEV_TYPE_GP         0x3
+#define SYS_STATUS_DEV_TYPE_TEST       0x5
+#define SYS_STATUS_DEV_TYPE_EMU                0x9
+#define SYS_STATUS_DEV_TYPE_HS         0xa
+#define SYS_STATUS_SUB_TYPE_SHIFT      8
+#define SYS_STATUS_SUB_TYPE_MASK       (0xf << 8)
+#define SYS_STATUS_SUB_TYPE_VAL_FS     0xa
 
 #define K3_ROM_BOOT_HEADER_MAGIC       "EXTBOOT"
 
index 8de9739a40121f028493f63b394d04012ac5cdf2..d8d41ec5154afc423ed1f4f7ad05fae64ee12961 100644 (file)
@@ -2,10 +2,11 @@
 /*
  * K3: Security functions
  *
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - http://www.ti.com/
  *     Andrew F. Davis <afd@ti.com>
  */
 
+#include <asm/io.h>
 #include <common.h>
 #include <cpu_func.h>
 #include <dm.h>
 #include <spl.h>
 #include <asm/arch/sys_proto.h>
 
+#include "common.h"
+
+static bool ti_secure_cert_detected(void *p_image)
+{
+       /* Primitive certificate detection, check for DER starting with
+        * two 4-Octet SEQUENCE tags
+        */
+       return (((u8 *)p_image)[0] == 0x30 && ((u8 *)p_image)[1] == 0x82 &&
+               ((u8 *)p_image)[4] == 0x30 && ((u8 *)p_image)[5] == 0x82);
+}
+
+/* Primitive certificate length, assumes one 2-Octet sized SEQUENCE */
+static size_t ti_secure_cert_length(void *p_image)
+{
+       size_t seq_length = be16_to_cpu(readw_relaxed(p_image + 2));
+       /* Add 4 for the SEQUENCE tag length */
+       return seq_length + 4;
+}
+
 void ti_secure_image_post_process(void **p_image, size_t *p_size)
 {
        struct ti_sci_handle *ti_sci = get_ti_sci_handle();
        struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
+       size_t cert_length;
        u64 image_addr;
        u32 image_size;
        int ret;
@@ -29,6 +50,36 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size)
        image_addr = (uintptr_t)*p_image;
        image_size = *p_size;
 
+       if (!image_size)
+               return;
+
+       if (get_device_type() == K3_DEVICE_TYPE_GP) {
+               if (ti_secure_cert_detected(*p_image)) {
+                       printf("Warning: Detected image signing certificate on GP device. "
+                              "Skipping certificate to prevent boot failure. "
+                              "This will fail if the image was also encrypted\n");
+
+                       cert_length = ti_secure_cert_length(*p_image);
+                       if (cert_length > *p_size) {
+                               printf("Invalid signing certificate size\n");
+                               return;
+                       }
+
+                       *p_image += cert_length;
+                       *p_size -= cert_length;
+               }
+
+               return;
+       }
+
+       if (get_device_type() != K3_DEVICE_TYPE_HS_SE &&
+           !ti_secure_cert_detected(*p_image)) {
+               printf("Warning: Did not detect image signing certificate. "
+                      "Skipping authentication to prevent boot failure. "
+                      "This will fail on Security Enforcing(HS-SE) devices\n");
+               return;
+       }
+
        debug("Authenticating image at address 0x%016llx\n", image_addr);
        debug("Authenticating image of size %d bytes\n", image_size);
 
index 737bdd8edb41c06a6625ebe90fff154e54547801..2cb5dae736570ac840a21c64271aefc9aea48c95 100644 (file)
@@ -20,6 +20,7 @@ config MPC85xx
        select CREATE_ARCH_SYMLINK
        select SYS_FSL_DDR
        select SYS_FSL_DDR_BE
+       select SYS_FSL_IFC_BE
        select BINMAN if OF_SEPARATE
        imply CMD_HASH
        imply CMD_IRQ
index 12dc03cfd0f059e83243d4b2a974abd84cf5fb56..18ef718db3b3458982c4b501188ce694484c9df1 100644 (file)
@@ -154,6 +154,7 @@ config TARGET_P2041RDB
        bool "Support P2041RDB"
        select ARCH_P2041
        select BOARD_LATE_INIT if CHAIN_OF_TRUST
+       select FSL_CORENET
        select PHYS_64BIT
        imply CMD_SATA
        imply FSL_SATA
@@ -233,6 +234,7 @@ config TARGET_KMP204X
 config TARGET_KMCENT2
        bool "Support kmcent2"
        select VENDOR_KM
+       select FSL_CORENET
 
 endchoice
 
@@ -240,6 +242,7 @@ config ARCH_B4420
        bool
        select E500MC
        select E6500
+       select FSL_CORENET
        select FSL_LAW
        select HETROGENOUS_CLUSTERS
        select SYS_FSL_DDR_VER_47
@@ -268,6 +271,7 @@ config ARCH_B4860
        bool
        select E500MC
        select E6500
+       select FSL_CORENET
        select FSL_LAW
        select HETROGENOUS_CLUSTERS
        select SYS_FSL_DDR_VER_47
@@ -607,6 +611,7 @@ config ARCH_P3041
        bool
        select BACKSIDE_L2_CACHE
        select E500MC
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_44
@@ -638,6 +643,7 @@ config ARCH_P4080
        bool
        select BACKSIDE_L2_CACHE
        select E500MC
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_44
@@ -678,6 +684,7 @@ config ARCH_P5040
        bool
        select BACKSIDE_L2_CACHE
        select E500MC
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_44
@@ -710,6 +717,7 @@ config ARCH_T1024
        select BACKSIDE_L2_CACHE
        select E500MC
        select E5500
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_50
@@ -735,6 +743,7 @@ config ARCH_T1040
        select BACKSIDE_L2_CACHE
        select E500MC
        select E5500
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_50
@@ -760,6 +769,7 @@ config ARCH_T1042
        select BACKSIDE_L2_CACHE
        select E500MC
        select E5500
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_50
@@ -784,6 +794,7 @@ config ARCH_T2080
        bool
        select E500MC
        select E6500
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_47
@@ -814,6 +825,7 @@ config ARCH_T4240
        bool
        select E500MC
        select E6500
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_47
@@ -1161,8 +1173,16 @@ config SYS_FSL_NUM_LAWS
                Number of local access windows. This is fixed per SoC.
                If not sure, do not change.
 
+config SYS_FSL_CORES_PER_CLUSTER
+       int
+       depends on SYS_FSL_QORIQ_CHASSIS2
+       default 4 if ARCH_B4860 || ARCH_T2080 || ARCH_T4240
+       default 2 if ARCH_B4420
+       default 1 if ARCH_T1024 || ARCH_T1040 || ARCH_T1042
+
 config SYS_FSL_THREADS_PER_CORE
        int
+       depends on SYS_FSL_QORIQ_CHASSIS2
        default 2 if E6500
        default 1
 
@@ -1274,6 +1294,10 @@ config SYS_BOOK3E_HV
        bool "Category E.HV is supported"
        depends on BOOKE
 
+config FSL_CORENET
+       bool
+       select SYS_FSL_CPC
+
 config SYS_CPC_REINIT_F
        bool
        help
@@ -1281,7 +1305,7 @@ config SYS_CPC_REINIT_F
          required to be re-initialized.
 
 config SYS_FSL_CPC
-       bool "Corenet Platform Cache support"
+       bool
 
 config SYS_CACHE_STASHING
        bool "Enable cache stashing"
index a43e6e5e538b3195c3d68f5a98d42c76467293ed..458c0a8d365369368907bbf0306083fb247ecac0 100644 (file)
@@ -16,9 +16,6 @@
 
 #include <fsl_ddrc_version.h>
 
-/* IP endianness */
-#define CONFIG_SYS_FSL_IFC_BE
-
 #if defined(CONFIG_ARCH_MPC8548)
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  1
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
@@ -74,7 +71,6 @@
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 
 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
@@ -91,7 +87,6 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_P3041)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     4
 #define CONFIG_SYS_NUM_FMAN            2
 #define CONFIG_SYS_NUM_FM1_DTSEC       4
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
 
 #elif defined(CONFIG_ARCH_P5040)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     3
 #define CONFIG_SYS_NUM_FMAN            2
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 
 #elif defined(CONFIG_ARCH_T4240)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #ifdef CONFIG_ARCH_T4240
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 4 }
 #define CONFIG_SYS_NUM_FMAN            2
 #define CONFIG_SYS_PME_CLK             0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
-#define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM1_CLK             3
 #define CONFIG_SYS_FM2_CLK             3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_FM1_CLK             0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
-#define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 
 #ifdef CONFIG_ARCH_B4860
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_MAX_DSP_CPUS            12
 #define CONFIG_NUM_DSP_CPUS            6
 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS   2
 #else
 #define CONFIG_MAX_DSP_CPUS            2
 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS   1
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC       4
 #define CONFIG_SYS_NUM_FM1_10GEC       0
 #endif
 
 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
 #define CONFIG_PME_PLAT_CLK_DIV                2
 #define CONFIG_SYS_PME_CLK             CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
-#define CONFIG_SYS_FMAN_V3
 #define CONFIG_FM_PLAT_CLK_DIV 1
 #define CONFIG_SYS_FM1_CLK             CONFIG_FM_PLAT_CLK_DIV
 #define CONFIG_SYS_FM_MURAM_SIZE       0x30000
 #define QE_NUM_OF_SNUM                 28
 
 #elif defined(CONFIG_ARCH_T1024)
-#define CONFIG_FSL_CORENET          /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3  /* QMAN version 3 */
-#define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FSL_NUM_CC_PLL      2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
 #define CONFIG_SYS_FSL_SRDS_1
 #define QE_NUM_OF_SNUM                 28
 
 #elif defined(CONFIG_ARCH_T2080)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_FSL_QMAN_V3
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_PME_CLK             CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FM1_CLK             0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
-#define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v3.0"
index 9b71424dfe60a009db9b86bc78ace8ae13dd3def..7ea04442b87695222de973ff5942477ad3f9af08 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_SYS_DEBUG
-static void hexdump(unsigned char *buf, int len)
-{
-       int i;
-
-       for (i = 0; i < len; i++) {
-               if ((i % 16) == 0)
-                       printf("%s%08x: ", i ? "\n" : "",
-                                                       (unsigned int)&buf[i]);
-               printf("%02x ", buf[i]);
-       }
-       printf("\n");
-}
-#endif
-
 #ifdef CONFIG_SH_SDRAM_OFFSET
 #define GET_INITRD_START(initrd, linux) (initrd - linux + CONFIG_SH_SDRAM_OFFSET)
 #else
index 0a1b2c94161904a9f93e12704e6c771636f86168..aa9687f7a9d991f0da340c98e021a2152474bba5 100644 (file)
@@ -206,7 +206,7 @@ int board_late_init(void)
        return 0;
 }
 
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_MMC
 #define UBOOT_RAW_SECTOR_OFFSET 0x40
 unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
 {
@@ -219,4 +219,4 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
                return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
        }
 }
-#endif /* CONFIG_SPL_MMC_SUPPORT */
+#endif /* CONFIG_SPL_MMC */
index c3e1734dda0cbfeaac34efc0baec8fa6b8d6b200..86b4050c4c1712351ae4df29aa3643a9c7e1f31d 100644 (file)
@@ -7,7 +7,6 @@
 
 #include <common.h>
 #include <debug_uart.h>
-#include <flash.h>
 #include <init.h>
 #include <net.h>
 #include <vsprintf.h>
@@ -140,7 +139,7 @@ static void at91sam9263ek_lcd_hw_init(void)
 #include <version.h>
 
 #ifdef CONFIG_MTD_NOR_FLASH
-extern flash_info_t flash_info[];
+#include <flash.h>
 #endif
 
 void lcd_show_board_info(void)
index 738b6bc25cea5b4a1b4c88aaa11c6fe125cf7f81..31d532b75294a56c1fa1afb001ebac3cb3b33839 100644 (file)
@@ -12,7 +12,6 @@
 #include <command.h>
 #include <env.h>
 #include <env_internal.h>
-#include <flash.h>
 #include <init.h>
 #include <net.h>
 #include <malloc.h>
index 4337f4879de77306c6d5da4076791d7b93d72d09..5d15ed4e691dad5a51c618dfdeb773e82c7e7b90 100644 (file)
@@ -200,8 +200,8 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
                        do {
                                result = *addr;
 
-                               /* check timeout */
-                               if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+                               /* check timeout, 1000ms */
+                               if (get_timer(start) > 1000) {
                                        MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
                                        chip1 = TMO;
                                        break;
@@ -289,8 +289,8 @@ static int write_word(flash_info_t *info, ulong dest, ulong data)
        do {
                result = *addr;
 
-               /* check timeout */
-               if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+               /* check timeout, 1000ms */
+               if (get_timer(start) > 1000) {
                        chip1 = ERR | TMO;
                        break;
                }
index f1a0b0cfc34ca25e735248c5a88c976afc58a048..f56e4e857af1d18351eaa41b71d1793bfe6d2d4a 100644 (file)
@@ -6,7 +6,6 @@
 
 #include <common.h>
 #include <dm.h>
-#include <flash.h>
 #include <fsl_validate.h>
 #include <fsl_secboot_err.h>
 #include <fsl_sfp.h>
@@ -79,6 +78,8 @@ static u32 check_ie(struct fsl_secboot_img_priv *img)
  * address
  */
 #if defined(CONFIG_MPC85xx)
+#include <flash.h>
+
 int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
 {
        struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
index 303d29bc23a2fe7955cb0b4f061060cfade2f11c..0ecce875d149c61303c38caf88ca6aef954db249 100644 (file)
@@ -1,5 +1,9 @@
 if TARGET_M5253DEMO
 
+config FLASH_CFI_LEGACY
+       depends on SYS_FLASH_CFI
+       def_bool y
+
 config SYS_CPU
        default "mcf52x2"
 
index 31974217816845e6da9201312d781543e827af31..bff1ac5fb113f4662b427620098e818cff161bb7 100644 (file)
@@ -242,7 +242,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
                                        count = 0;
                                }
 
-                               if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+                               /* check timeout, 1000ms */
+                               if (get_timer(start) > 1000) {
                                        printf("Timeout\n");
                                        *addr = 0x00F0; /* reset to read mode */
 
@@ -294,8 +295,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
                                                enable_interrupts();
 
                                        while ((*addr & 0x0080) != 0x0080) {
-                                               if (get_timer(start) >
-                                                   CONFIG_SYS_FLASH_ERASE_TOUT) {
+                                               /* check timeout, 1000ms */
+                                               if (get_timer(start) > 1000) {
                                                        printf("Timeout\n");
                                                        *addr = 0x00F0; /* reset to read mode */
 
@@ -430,7 +431,8 @@ int write_word(flash_info_t * info, FPWV * dest, u16 data)
        /* data polling for D7 */
        while (res == 0
               && (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) {
-               if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+               /* check timeout, 500ms */
+               if (get_timer(start) > 500) {
                        *dest = (u8) 0x00F000F0;        /* reset bank */
                        res = 1;
                }
index 84671f63c60bd6b0e329f6d2d9bcd61263d07027..2650d300e3843f35f2af25a992d788c16e5d248a 100644 (file)
@@ -97,7 +97,7 @@ int dram_init(void)
 int fixed_sdram(void)
 {
        immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-       u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+       u32 msize = CONFIG_SYS_SDRAM_SIZE;
        u32 msize_log2 = __ilog2(msize);
 
        im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
@@ -127,7 +127,7 @@ int fixed_sdram(void)
 
        im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
        udelay(2000);
-       return CONFIG_SYS_DDR_SIZE;
+       return CONFIG_SYS_SDRAM_SIZE >> 20;
 }
 #endif /*!CONFIG_SYS_SPD_EEPROM */
 
index 2625195f81b146fab325d4455655fe93db7fb24f..b423ec8e218a5f9eba40c02533c16c6807c4d66e 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_DRAM_SIZE   1024
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
-       .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
-       .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
-       .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-       .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
-       .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
-       .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
-       .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
-       .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
-       .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
-       .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
-       .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
-       .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
-       .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
-       .ddr_data_init = CONFIG_MEM_INIT_VALUE,
-       .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
-       .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
-       .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
-       .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
-       .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
-       .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
-       .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
-       .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
-       .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
-       .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
-       .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
-       .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
-       .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-       .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
-       .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
-       .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
-       .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
-       .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
-       .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
-       .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
-       .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
-       .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
-       .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
-       .ddr_data_init = CONFIG_MEM_INIT_VALUE,
-       .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
-       .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
-       .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
-       .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
-       .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
-       .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
-       .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667,
-       .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
-       .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
-       .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
-       {750, 850, &ddr_cfg_regs_800},
-       {607, 749, &ddr_cfg_regs_667},
-       {0, 0, NULL}
-};
-
-unsigned long get_sdram_size(void)
-{
-       struct cpu_type *cpu;
-       phys_size_t ddr_size;
-
-       cpu = gd->arch.cpu;
-       /* P1014 and it's derivatives support max 16it DDR width */
-       if (cpu->soc_ver == SVR_P1014)
-               ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
-       else
-               ddr_size = CONFIG_SYS_DRAM_SIZE;
-
-       return ddr_size;
-}
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t fixed_sdram(void)
-{
-       int i;
-       char buf[32];
-       fsl_ddr_cfg_regs_t ddr_cfg_regs;
-       phys_size_t ddr_size;
-       ulong ddr_freq, ddr_freq_mhz;
-       struct cpu_type *cpu;
-
-#if defined(CONFIG_SYS_RAMBOOT)
-       return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-#endif
-
-       ddr_freq = get_ddr_freq(0);
-       ddr_freq_mhz = ddr_freq / 1000000;
-
-       printf("Configuring DDR for %s MT/s data rate\n",
-                               strmhz(buf, ddr_freq));
-
-       for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
-               if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
-                  (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
-                       memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
-                                                       sizeof(ddr_cfg_regs));
-                       break;
-               }
-       }
-
-       if (fixed_ddr_parm_0[i].max_freq == 0)
-               panic("Unsupported DDR data rate %s MT/s data rate\n",
-                                       strmhz(buf, ddr_freq));
-
-       cpu = gd->arch.cpu;
-       /* P1014 and it's derivatives support max 16bit DDR width */
-       if (cpu->soc_ver == SVR_P1014) {
-               ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
-               ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
-               /* divide SA and EA by two and then mask the rest so we don't
-                * write to reserved fields */
-               ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff;
-       }
-
-       ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-       fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
-       if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
-                                       LAW_TRGT_IF_DDR_1) < 0) {
-               printf("ERROR setting Local Access Windows for DDR\n");
-               return 0;
-       }
-
-       return ddr_size;
-}
-
-#else /* CONFIG_SYS_DDR_RAW_TIMING */
 /*
  * Samsung K4B2G0846C-HCF8
  * The following timing are for "downshift"
@@ -232,5 +96,3 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
        }
 }
-
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
index aa833a030fd96095eba2eabb58b7161c4346330f..0cfde91c94c62f153322c4696c436d891ac7454c 100644 (file)
@@ -7,7 +7,6 @@
 #include <command.h>
 #include <env.h>
 #include <env_internal.h>
-#include <flash.h>
 #include <init.h>
 #include <led.h>
 #include <log.h>
index bfd55f54e4e1a62c2f79d24f3f372369a4d76b40..47b880435210da5576baeeeada5c181020e67fd6 100644 (file)
@@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static long fixed_sdram(void)
 {
        immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-       u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+       u32 msize = CONFIG_SYS_SDRAM_SIZE;
        u32 msize_log2 = __ilog2(msize);
 
        out_be32(&im->sysconf.ddrlaw[0].bar,
index 45c77a249a9b89fb349c892c9f4b3a7b0428ac52..48aea71be637af0a71042590a37959b577350907 100644 (file)
@@ -56,7 +56,7 @@ int checkboard(void)
 int fixed_sdram(unsigned long config)
 {
        immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-       u32 msize = CONFIG_SYS_DDR_SIZE << 20;
+       u32 msize = CONFIG_SYS_SDRAM_SIZE;
 
 #ifndef CONFIG_SYS_RAMBOOT
        u32 msize_log2 = __ilog2(msize);
@@ -109,7 +109,7 @@ int fixed_sdram(unsigned long config)
 
 static int setup_sdram(void)
 {
-       u32 msize = CONFIG_SYS_DDR_SIZE << 20;
+       u32 msize = CONFIG_SYS_SDRAM_SIZE;
        long int size_01, size_02;
 
        size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
index ecb4424fd92afdb8b8f3b77cd59ae3195ebd97c0..bed24972f7a85901d8677f51dc3f883ec3af6634 100644 (file)
@@ -118,7 +118,7 @@ _msc01:
        /* setup basic address decode */
        PTR_LI  t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
        li      t1, 0x0
-       li      t2, -CONFIG_SYS_MEM_SIZE
+       li      t2, -CONFIG_SYS_SDRAM_SIZE
        sw      t1, MSC01_BIU_MCBAS1L_OFS(t0)
        sw      t2, MSC01_BIU_MCMSK1L_OFS(t0)
        sw      t1, MSC01_BIU_MCBAS2L_OFS(t0)
@@ -168,7 +168,7 @@ _msc01:
        sw      t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
 
        /* setup PCI_BAR0 memory window */
-       li      t1, -CONFIG_SYS_MEM_SIZE
+       li      t1, -CONFIG_SYS_SDRAM_SIZE
        sw      t1, MSC01_PCI_BAR0_OFS(t0)
 
        /* setup PCI to SysCon/CPU translation */
index d2e2e4ae2093c563e961325a8916fd71bab81d0c..9853a0ba82f6f90515c0150fb2737ba7351fbdab 100644 (file)
@@ -94,7 +94,7 @@ static enum sys_con malta_sys_con(void)
 
 int dram_init(void)
 {
-       gd->ram_size = CONFIG_SYS_MEM_SIZE;
+       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
        return 0;
 }
index 8a0b1758566358fdd588e27cea8b6aff0a701bec..6a7b848161454080cc144cfc572682a01cf3017d 100644 (file)
@@ -141,12 +141,11 @@ static int fixed_sdram(void)
        udelay(200);
        setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
 
-       msize = CONFIG_SYS_DDR_SIZE << 20;
        disable_addr_trans();
-       msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
+       msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
        enable_addr_trans();
        msize /= (1024 * 1024);
-       if (CONFIG_SYS_DDR_SIZE != msize) {
+       if (CONFIG_SYS_SDRAM_SIZE >> 20 != msize) {
                for (ddr_size = msize << 20, ddr_size_log2 = 0;
                        (ddr_size > 1);
                        ddr_size = ddr_size >> 1, ddr_size_log2++)
index 2379b521904a84b55f1204ef52d20fe58b6f6135..559192e9001eb94e47b1c4284dc9a0a4a9e06e6f 100644 (file)
@@ -15,7 +15,6 @@
 #include <init.h>
 #include <net.h>
 #include <ns16550.h>
-#include <flash.h>
 #include <nand.h>
 #include <i2c.h>
 #include <serial.h>
index dae064d4654af388db09fa11276abfd03be98964..6c44afb44875063a490ff4a2a96bf9034e74c3d4 100644 (file)
@@ -15,7 +15,6 @@
 #include <common.h>
 #include <dm.h>
 #include <env.h>
-#include <flash.h>
 #include <init.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
index 27aad4eaae3a6643ad76e1b19c2a29dd7fc4698b..f9e1bc6316489219f258a20f59b2be9b7f8b0810 100644 (file)
@@ -30,8 +30,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[];      /* FLASH chips info */
-
 void local_bus_init (void);
 ulong flash_get_size (ulong base, int banknum);
 
index 7cf2dfae9746e06c8093d5fbc89089f8e3c34712..22c67c6e3887bdab4a51399a751464af4435fc12 100644 (file)
@@ -14,7 +14,9 @@
 #include <cli.h>
 #include <console.h>
 #include <env.h>
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_NOR
 #include <flash.h>
+#endif
 #include <malloc.h>
 #include <mmc.h>
 #include <nand.h>
index 59d0c65c944d5b3123cdf33ffd79db94703b2ec7..150373947d51ffa5e2f886aaa7f8273b8b681511 100644 (file)
@@ -486,7 +486,7 @@ config SYS_TEXT_BASE
 config HAVE_SYS_MONITOR_BASE
        bool
        depends on ARC || MIPS || M68K || NIOS2 || PPC || XTENSA || X86 \
-               || FLASH_PIC32 || ENV_IS_IN_FLASH || MTD_NOR_FLASH
+               || ENV_IS_IN_FLASH || MTD_NOR_FLASH
        depends on !EFI_APP
        default y
 
index 195efa8661c6772c4a93fa3932d8e66f6ee2480c..1c5d3e10a395a6be37917a8556f7b159c1e4f4ed 100644 (file)
--- a/cmd/adc.c
+++ b/cmd/adc.c
@@ -71,6 +71,7 @@ static int do_adc_info(struct cmd_tbl *cmdtp, int flag, int argc,
 static int do_adc_single(struct cmd_tbl *cmdtp, int flag, int argc,
                         char *const argv[])
 {
+       char *varname = NULL;
        struct udevice *dev;
        unsigned int data;
        int ret, uV, val;
@@ -78,6 +79,9 @@ static int do_adc_single(struct cmd_tbl *cmdtp, int flag, int argc,
        if (argc < 3)
                return CMD_RET_USAGE;
 
+       if (argc >= 4)
+               varname = argv[3];
+
        ret = adc_channel_single_shot(argv[1], simple_strtol(argv[2], NULL, 0),
                                      &data);
        if (ret) {
@@ -95,7 +99,8 @@ static int do_adc_single(struct cmd_tbl *cmdtp, int flag, int argc,
                printf("%u\n", data);
        }
 
-       env_set_ulong(argv[2], val);
+       if (varname)
+               env_set_ulong(varname, val);
 
        return CMD_RET_SUCCESS;
 }
@@ -160,5 +165,5 @@ static char adc_help_text[] =
 U_BOOT_CMD_WITH_SUBCMDS(adc, "ADC sub-system", adc_help_text,
        U_BOOT_SUBCMD_MKENT(list, 1, 1, do_adc_list),
        U_BOOT_SUBCMD_MKENT(info, 2, 1, do_adc_info),
-       U_BOOT_SUBCMD_MKENT(single, 3, 1, do_adc_single),
+       U_BOOT_SUBCMD_MKENT(single, 4, 1, do_adc_single),
        U_BOOT_SUBCMD_MKENT(scan, 3, 1, do_adc_scan));
index 1f70ee9e911bb6f4987791d0e7f1f9e1033cc5a3..9fe8ce4a27cfca493874d3639ceacb619361d713 100644 (file)
@@ -31,7 +31,6 @@ static int image_info(unsigned long addr);
 #if defined(CONFIG_CMD_IMLS)
 #include <flash.h>
 #include <mtd/cfi_flash.h>
-extern flash_info_t flash_info[]; /* info for FLASH chips */
 #endif
 
 #if defined(CONFIG_CMD_IMLS) || defined(CONFIG_CMD_IMLS_NAND)
index 502d5ed697a78dae35cb26865216ab756ad69ee4..ba36220d9e1f9ebf814524b2ddeb1e38d725dd6f 100644 (file)
--- a/cmd/cls.c
+++ b/cmd/cls.c
@@ -8,7 +8,6 @@
 #include <common.h>
 #include <command.h>
 #include <dm.h>
-#include <lcd.h>
 #include <video.h>
 
 #define CSI "\x1b["
@@ -20,19 +19,12 @@ static int do_video_clear(struct cmd_tbl *cmdtp, int flag, int argc,
 
        /*  Send clear screen and home */
        printf(CSI "2J" CSI "1;1H");
-#if defined(CONFIG_DM_VIDEO)
-#if !defined(CONFIG_VIDEO_ANSI)
-       if (uclass_first_device_err(UCLASS_VIDEO, &dev))
-               return CMD_RET_FAILURE;
-
-       if (video_clear(dev))
-               return CMD_RET_FAILURE;
-#endif
-#elif defined(CONFIG_LCD)
-       lcd_clear();
-#else
-       return CMD_RET_FAILURE;
-#endif
+       if (CONFIG_IS_ENABLED(DM_VIDEO) && !CONFIG_IS_ENABLED(VIDEO_ANSI)) {
+               if (uclass_first_device_err(UCLASS_VIDEO, &dev))
+                       return CMD_RET_FAILURE;
+               if (video_clear(dev))
+                       return CMD_RET_FAILURE;
+       }
        return CMD_RET_SUCCESS;
 }
 
index 2aad50c6724cce48fd335dd2251265ad53ddc43b..57e2afa2472bed29a1b786418b829dcaae0cbdce 100644 (file)
 # define DEBUGF(fmt, args...)
 #endif
 
-#include <flash.h>
 
 #ifndef CONFIG_MTD_NOR_FLASH
 # define OFFSET_ADJUSTMENT     0
 #else
+#include <flash.h>
 # define OFFSET_ADJUSTMENT     (flash_info[id.num].start[0])
 #endif
 
index ad49905d67bb176e59c667c0379a07258f1fd929..90921cecf602f93637e02ba2eb75c0c0b3f9d573 100644 (file)
@@ -10,7 +10,6 @@
 #include <command.h>
 #include <cros_ec.h>
 #include <dm.h>
-#include <flash.h>
 #include <log.h>
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>
index bbb4812ff81d6f4f56a9b1b1e78a57c64bb9d3e3..f94abd612d5e87677927779374d83dbd10a106c3 100644 (file)
@@ -111,6 +111,7 @@ static int do_extension_apply(struct cmd_tbl *cmdtp, int flag,
                return CMD_RET_USAGE;
 
        if (strcmp(argv[1], "all") == 0) {
+               ret = CMD_RET_FAILURE;
                list_for_each_entry(extension, &extension_list, list) {
                        ret = extension_apply(extension);
                        if (ret != CMD_RET_SUCCESS)
index db4bb2529c6a60df3829811cbd2e8129af4c0d42..f4f85ecc7a8e0613c63e55406098a60726b879ef 100644 (file)
@@ -25,7 +25,6 @@ int find_dev_and_part(const char *id, struct mtd_device **dev,
 #ifdef CONFIG_MTD_NOR_FLASH
 #include <flash.h>
 #include <mtd/cfi_flash.h>
-extern flash_info_t flash_info[];      /* info for FLASH chips */
 
 /*
  * The user interface starts numbering for Flash banks with 1
index 914a7beeed95fa3e7151520a36eda1bd3ea0c1a2..e00fcc2022665024c7399d97224da15861566bc8 100644 (file)
@@ -73,7 +73,9 @@
 #include <common.h>
 #include <command.h>
 #include <env.h>
+#if defined(CONFIG_CMD_FLASH)
 #include <flash.h>
+#endif
 #include <image.h>
 #include <malloc.h>
 #include <jffs2/jffs2.h>
@@ -156,7 +158,6 @@ static int mtd_device_validate(u8 type, u8 num, u32 *size)
        if (type == MTD_DEV_TYPE_NOR) {
 #if defined(CONFIG_CMD_FLASH)
                if (num < CONFIG_SYS_MAX_FLASH_BANKS) {
-                       extern flash_info_t flash_info[];
                        *size = flash_info[num].size;
 
                        return 0;
@@ -260,8 +261,6 @@ static inline u32 get_part_sector_size_nand(struct mtdids *id)
 static inline u32 get_part_sector_size_nor(struct mtdids *id, struct part_info *part)
 {
 #if defined(CONFIG_CMD_FLASH)
-       extern flash_info_t flash_info[];
-
        u32 end_phys, start_phys, sector_size = 0, size = 0;
        int i;
        flash_info_t *flash;
index 1224a7f85bb37b52126aed10098cb9adec87e920..e44ae0d56b750c4311ff006fbcf8cd864ac77edc 100644 (file)
@@ -14,7 +14,9 @@
 #include <efi_loader.h>
 #include <env.h>
 #include <exports.h>
+#ifdef CONFIG_MTD_NOR_FLASH
 #include <flash.h>
+#endif
 #include <image.h>
 #include <lmb.h>
 #include <mapmem.h>
index b7511382d3ac91327ff23871415945f9f9529a8e..1f4e3fcdede19c6723bc1e58337bd6494b9413c6 100644 (file)
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -16,7 +16,9 @@
 #include <cli.h>
 #include <command.h>
 #include <console.h>
+#ifdef CONFIG_MTD_NOR_FLASH
 #include <flash.h>
+#endif
 #include <hash.h>
 #include <log.h>
 #include <mapmem.h>
index ffa05bc20181331794a64f1fd59c96dee2fc9726..2136af64163c0fa13c491d620bdaf2804dd29c24 100644 (file)
@@ -8,7 +8,6 @@
 #include <common.h>
 #include <command.h>
 #include <env.h>
-#include <flash.h>
 #include <image.h>
 #include <net.h>
 #include <vsprintf.h>
index cd50b38081c2e5959dad9fae5d7caeaf73ff3830..058635cb2f83cba90de9f37f1fd02b6c3434fefb 100644 (file)
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -9,7 +9,6 @@
 #include <command.h>
 #include <div64.h>
 #include <dm.h>
-#include <flash.h>
 #include <log.h>
 #include <malloc.h>
 #include <mapmem.h>
index ed29069d2de6d2638e855e5908700c7a84dd8408..e702f0234ee7d7cd3caaeb95d53c952fa4e50193 100644 (file)
@@ -14,7 +14,9 @@
 #include <bootstage.h>
 #include <cpu_func.h>
 #include <exports.h>
+#ifdef CONFIG_MTD_NOR_FLASH
 #include <flash.h>
+#endif
 #include <hang.h>
 #include <image.h>
 #include <irq_func.h>
index f939c2f9e9545250e18e11f23509a95db162b98b..848f44e59dfdb349dec436e1f1176b5303633814 100644 (file)
@@ -13,8 +13,6 @@
 
 #include <mtd/cfi_flash.h>
 
-extern flash_info_t  flash_info[]; /* info for FLASH chips */
-
 /*-----------------------------------------------------------------------
  * Functions
  */
index ba4b2e4f99e9c1aaedac1bf2c3f33f05f4d9e248..f33162276d92ebf45cae8d563b22653c50fd103d 100644 (file)
@@ -166,7 +166,7 @@ config VPL_SERIAL
        select VPL_PRINTF
        select VPL_STRTO
        help
-         Enable support for serial in VPL. See SPL_SERIAL_SUPPORT for
+         Enable support for serial in VPL. See SPL_SERIAL for
          details.
 
 config VPL_SIZE_LIMIT
index f66147477e77bf25d5bd4f81239a57152efe3514..23a395e63d4ef74d4a92655090a673c4a7150f4d 100644 (file)
@@ -398,6 +398,17 @@ int __weak spl_mmc_emmc_boot_partition(struct mmc *mmc)
        return default_spl_mmc_emmc_boot_partition(mmc);
 }
 
+static int spl_mmc_get_mmc_devnum(struct mmc *mmc)
+{
+       struct blk_desc *block_dev;
+#if !CONFIG_IS_ENABLED(BLK)
+       block_dev = &mmc->block_dev;
+#else
+       block_dev = dev_get_uclass_plat(mmc->dev);
+#endif
+       return block_dev->devnum;
+}
+
 int spl_mmc_load(struct spl_image_info *spl_image,
                 struct spl_boot_device *bootdev,
                 const char *filename,
@@ -408,9 +419,11 @@ int spl_mmc_load(struct spl_image_info *spl_image,
        u32 boot_mode;
        int err = 0;
        __maybe_unused int part = 0;
+       int mmc_dev;
 
-       /* Perform peripheral init only once */
-       if (!mmc) {
+       /* Perform peripheral init only once for an mmc device */
+       mmc_dev = spl_mmc_get_device_index(bootdev->boot_device);
+       if (!mmc || spl_mmc_get_mmc_devnum(mmc) != mmc_dev) {
                err = spl_mmc_find_device(&mmc, bootdev->boot_device);
                if (err)
                        return err;
index b9ad475d9d44b5753ab01b9fdb8efc5620d79739..80f16af6535817ebb018a9754e4548881e9305fc 100644 (file)
 
 #include <command.h>
 #include <env.h>
-#include <flash.h>
 #include <net.h>
 #include <net/tftp.h>
 #include <malloc.h>
 #include <mapmem.h>
 #include <dfu.h>
 #include <errno.h>
-#include <mtd/cfi_flash.h>
 
 #if defined(CONFIG_DFU_TFTP) || defined(CONFIG_UPDATE_TFTP)
 /* env variable holding the location of the update file */
@@ -49,7 +47,8 @@
 extern ulong tftp_timeout_ms;
 extern int tftp_timeout_count_max;
 #ifdef CONFIG_MTD_NOR_FLASH
-extern flash_info_t flash_info[];
+#include <flash.h>
+#include <mtd/cfi_flash.h>
 static uchar *saved_prot_info;
 #endif
 static int update_load(char *filename, ulong msec_max, int cnt_max, ulong addr)
index 6c56cdc3286d27c128f4e3bcf2a43bb680eb147e..5083545a069cc7aa4e6e33cdd54af269fbf8ad31 100644 (file)
@@ -40,6 +40,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_ALTERA_QSPI=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_PHY_MARVELL=y
 CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
index 858fc5bbfd2eaddbf8774b0b3893e8a207970ea0..e294d1315cbcf59cfda3436ee77befcf1022b275 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=254
 CONFIG_DM_ETH=y
 CONFIG_MCFFEC=y
 CONFIG_MII=y
index c7fd5a07a7c5e5d84f893cb349e0ae557cc52d70..571b653b718ab0d3dcd03c829861c5cae9fad06e 100644 (file)
@@ -45,6 +45,7 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=137
 CONFIG_DM_ETH=y
 CONFIG_MCFFEC=y
 CONFIG_MII=y
index a14bf427ad0a871579148b84d0ebbe26b0b5cf14..7f7d92ba019f11b5d2dcedf1adb15bc0c458efa4 100644 (file)
@@ -45,6 +45,7 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=137
 CONFIG_DM_ETH=y
 CONFIG_MCFFEC=y
 CONFIG_MII=y
index f99375b535ed460994beb815d880361a919242a2..e4fb7ab96a830ed9f3a7ebf6059bc82c471e951a 100644 (file)
@@ -28,4 +28,6 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_CHECKSUM=y
+CONFIG_SYS_MAX_FLASH_SECT=137
 CONFIG_MCFUART=y
index 3ed703a7a79349b42d616ec99aed8c786d2438ec..79382eb0fe43da3edbf4ca70ce874d3c51526942 100644 (file)
@@ -39,6 +39,7 @@ CONFIG_SYS_FSL_I2C_OFFSET=0x280
 CONFIG_SYS_I2C_SLAVE=0x7F
 CONFIG_SYS_I2C_SPEED=80000
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_SYS_MAX_FLASH_SECT=2048
 CONFIG_USE_SYS_MAX_FLASH_BANKS=y
 CONFIG_DRIVER_DM9000=y
 CONFIG_MCFUART=y
index e3f736bf6308b71fc6a9a81d60fa960392c7e6f0..7dc87a2b2736cf2bf5d7612d861fce612790fe9c 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=137
 CONFIG_DM_ETH=y
 CONFIG_MCFFEC=y
 CONFIG_MII=y
index fe6ffca43c9f4116bbbce45322a06fc80669ec20..9e2cc332505a8c91c1b6e462f3a1593eda13a15a 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_SYS_I2C_SPEED=80000
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=11
 CONFIG_DM_ETH=y
 CONFIG_MCFFEC=y
 CONFIG_MII=y
index 42940e1000a4c05954dbae2882aa6a6293787d99..751d805002559c3155333b00d629ad4b7d35c1d9 100644 (file)
@@ -33,6 +33,8 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_CHECKSUM=y
+CONFIG_SYS_MAX_FLASH_SECT=137
 CONFIG_DM_ETH=y
 CONFIG_MCFFEC=y
 CONFIG_MII=y
index 28d51eaa9deb71400449ca1e03635648339e5b11..103289193613f9b50599aa19d3f28ab666db896e 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=137
 CONFIG_DM_ETH=y
 CONFIG_MCFFEC=y
 CONFIG_SYS_UNIFY_CACHE=y
index c59359b820c7f53f7d5cd1f23ac6837e41c435df..152a0be28ead4f13bb3ed70a03c4f1aafb6e323c 100644 (file)
@@ -40,6 +40,7 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=137
 CONFIG_DM_ETH=y
 CONFIG_MCFFEC=y
 CONFIG_SYS_UNIFY_CACHE=y
index ae4add504b1c3150ab333a00213a17f9147ff7ab..0bb86c158fa03ada1bba5fac34c0f0bc190ae1cc 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=137
 CONFIG_MTD_RAW_NAND=y
 CONFIG_DM_ETH=y
 CONFIG_MCFFEC=y
index aead0f45bd30adde4d12dfa53d60cc436823f0e5..27f72562d7a398d6243622141c3eeb47bf6aa5b4 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=137
 CONFIG_MTD_RAW_NAND=y
 CONFIG_DM_ETH=y
 CONFIG_MCFFEC=y
index 6adba431ef0964768c4366cc7a1e81973c0db8c0..086507e60165da6dbccbe6f0704c04fd6b93992d 100644 (file)
@@ -83,6 +83,7 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=35
 CONFIG_MTD_RAW_NAND=y
 CONFIG_MPC8XX_FEC=y
 # CONFIG_PCI is not set
index efdddf7c2b3d5f1298d7ef785c8b01ad2b86aa92..9a421096e7a887a97783ddfaae434ab8d29adf38 100644 (file)
@@ -194,8 +194,10 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_ETH_PHY=y
index 6fa89aad36a78293568f428269ca62cfd763ac33..def5d6fdf44b2bc0602d30af7dd366ff4440f1f3 100644 (file)
@@ -61,7 +61,9 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
index 82776497a592103968bcdac1e2669529ed267cde..881fca912b9b2f3a557ad36b0e56f2d60e0b0458 100644 (file)
@@ -60,7 +60,9 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
index c21ed57dc37561f33e454a98bc8825a9f5b79d9a..99a63300af9080a29c567c21454a933cfcf7e2e4 100644 (file)
@@ -60,7 +60,9 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
index caa965274f84d8f98092fa51700c96a6d270fd60..2ec67d761761f3c67ead547527af4034a32f58a1 100644 (file)
@@ -99,7 +99,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
index 5030afd098e78737b45994193325c24937232725..a3df3ddb360f29dfec922fbb464149d1edb41386 100644 (file)
@@ -67,7 +67,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index dd04cff4a448b08a0d7b4d82f068034a826d4d38..955e9d8cb459369bdf60e51f2310f276f416baa2 100644 (file)
@@ -88,7 +88,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 46613cce3b59206a632fd62ce7dc7a450c3188a7..25f6c81d9ae10715a27563e484ee1879fe4230bb 100644 (file)
@@ -90,7 +90,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 684922174fea1fd57780c3c2ac231a7eeab71d41..158e182fee239bc7a8891c3c146fb61cd7221789 100644 (file)
@@ -98,7 +98,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
index 89fccd6fc324c96331bf366b51bfa6e2d4965890..4015e3e324ef1f4db00dbca34b3ca7304ec67c46 100644 (file)
@@ -66,7 +66,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index a2786616c8de3d4649adc907fae3c01d121caf57..9d67ed1b26b88711f6b89f4304c858459df9eeb1 100644 (file)
@@ -87,7 +87,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 17daecd2ece9d3064f8804deed45f330dd4da82d..82317319588cd21a4298700bdbce0693f90d6308 100644 (file)
@@ -89,7 +89,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index ba17b431ef9bf0035f39056b9f4e2712a986ff10..78fd3442e26b124159ee1f8e78f4683602dd2488 100644 (file)
@@ -101,7 +101,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 7a5e057a2c22c20cb14879d1d26e9f2461030f40..c74d22a230ff583fadf7a5adf5f3a39f9a9be730 100644 (file)
@@ -69,7 +69,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index ef85d48719c88fbba1a9da16df0e0eb16a7d8f80..885f720a6120f8a0d59513b39ee3e6bea6f8a660 100644 (file)
@@ -90,7 +90,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index bda32ccbf342ff4e3c7853dc8759bea3aa7c6842..ef37991be7d15075160982e9f51113f0a6ac8b99 100644 (file)
@@ -92,7 +92,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index d3fe64037de98bea8256a32f05b4f9ab35dafcd4..116fff6e1729d39ebeb2f990a9f88732962e5ba1 100644 (file)
@@ -100,7 +100,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index c13369efe7087519d082fea5b8d12d5455970d81..52ec404f07d2d7a06e0537b047943c7dc3df531c 100644 (file)
@@ -68,7 +68,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 691d6e33dac4d6060e434c2189c4ec0073974c99..2461f53b1c006e63fc7d0a0f0496f3ec08c03140 100644 (file)
@@ -89,7 +89,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index a630e961ee2424e074d26a3c8a80d958fb0a1863..151720c18938884fde1eb8299080ff6c01971eca 100644 (file)
@@ -91,7 +91,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index e12299798fc14dbfa1fccefb0c246f99c61ab810..48e2f84659c16e0343dde71e29d54c1005374878 100644 (file)
@@ -110,7 +110,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_ELBC=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
index b581cb109b169cb7bf450e9b74cc13db65cc2fce..28f0758f122efdb99529723584034f4f9bcbcd4f 100644 (file)
@@ -97,7 +97,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index e8543c6461a15bb09dac4da16d96307a0391738c..1786b9496b24a403c9facc0afdb56b25a861a761 100644 (file)
@@ -99,7 +99,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 2b9fcb034c9cf4c54b8f9a7af4e529f06fde5ef1..ce3f88dac43d1e3d327af11cfc7dca757611175a 100644 (file)
@@ -77,7 +77,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 90106d7236b6be0206e0aa9f314201386b94dd26..0945f4fc511634e31a598871d60b8586ec9ce197 100644 (file)
@@ -109,7 +109,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_ELBC=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
index 7489ad3459f427d588bb35dfed49ae5d13565ba0..4298eac8460cdb090b0b2e6d30a6b2e2dfe5825f 100644 (file)
@@ -96,7 +96,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 728592f6c3c81c9e0f9acc998ff1caea56af7a60..ae5724678b6b559ef0ca31ca1b8980360c75fe39 100644 (file)
@@ -98,7 +98,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index ada7e2d59a746b251d7d73a2484e2e2dc203489b..c5988e78d820eb33bf433a5f29ddf95ee6fe55c9 100644 (file)
@@ -76,7 +76,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 4dddea3e7f08f727581c4bdab6619502806e3f69..6e8caa2b9041046728e9f3768482320c579954fd 100644 (file)
@@ -112,8 +112,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_ELBC=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
index ddd9e335e6425d17783ae64b8089da3f479ec2c0..43ab26d185bda770dcf84e0b8355c866112ba0d9 100644 (file)
@@ -99,8 +99,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 88365bff62b9dcf6f327cbcc229e8577e1680010..60a62e532c4e6bbdf0a6e5af52102456cee4c698 100644 (file)
@@ -101,8 +101,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index ef31e0970ace27fbb1ef86d9acee27f1c7fe8621..4e73f079d6327ae8c26a89359e2135f8cff521a5 100644 (file)
@@ -79,8 +79,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index b5f5bb9b3de330a9f9855db1439a37a0e67ba80e..49a412996820e8813c98a1b2ed1abfe0435afca6 100644 (file)
@@ -114,8 +114,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_ELBC=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
index 856a78fdd13762134ccec5367271658bedf0e78c..e046b76f11c07f752adbee73886bb8d644d3beb0 100644 (file)
@@ -101,8 +101,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index b03c17c7e7b84102e8fa765f7d1ae133e0457191..f001a1be49245efa8a557ba6036bd57787f3ba2a 100644 (file)
@@ -103,8 +103,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index c1a5ef9d30c5fa20b509549b8fb3af4f3e1f5d27..4c9ca9e63b96679202b483156487163d9d556f3f 100644 (file)
@@ -81,8 +81,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index caa62115012935d5779df870077cf6ee9cdd459a..40cc420623b009d14b365aec5e702267eaad0adf 100644 (file)
@@ -113,8 +113,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_ELBC=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
index 29cc14700aebe83277ba431fb44bb88506e11d46..f0f5f482653da8b2f1a256f7854b14253f09498d 100644 (file)
@@ -100,8 +100,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 3ee43f8da61783ac78a49a03afa604315be89b83..e845058deab4974d419613272c9bf5a8ef725b2d 100644 (file)
@@ -102,8 +102,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 7af0244078ac22857c0110e033c3d22f7553a0e8..cf106dc43e8f56dc5910670305ec9a5f27e86845 100644 (file)
@@ -80,8 +80,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 30bf78be1e6ea169ffe239061b0fcf3d75071ba2..da15a1cdb56e5ee1455f239751b783789e87f9c1 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -74,7 +73,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_ELBC=y
 CONFIG_DM_SPI_FLASH=y
index d5ad60981a2a418335aded57af9b1e7384e79f7e..96be038967d8428d48aa6f9be910fac6be3aafe8 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -71,7 +70,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 97b01b498bf1ecb34f6ef1a147517a1fba3d708a..91f0ac56981b21828fe0798a275ca4415dfc42c1 100644 (file)
@@ -10,7 +10,6 @@ CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -73,7 +72,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index c1eb08053299c766b59242e7862f23d280d95629..78398207e5bab4a661ec222b56a0e1a79cb211fd 100644 (file)
@@ -10,7 +10,6 @@ CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -68,7 +67,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
index 1df522a7449a35a4a8a855bc6aa346f9cf773f68..dd399466728a47d6d761a32afd5f565367ff5a7d 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -79,7 +78,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_ELBC=y
index 2380cfc7710c95de9fc492c601ab5f90290745b2..bff11680216aee0a20d5bddfb6fbed90faf0eabf 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -76,7 +75,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index 8a2464df91dd824191d5f245b84e0e540796c6c9..a0b55b0bb95d721257ed747f2abeea1ceeaab5ed 100644 (file)
@@ -10,7 +10,6 @@ CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -78,7 +77,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index 0abf6e1631dafc8ed3bf4a5d79b878de023a5d4f..2eb1f7f951b317ca3baf0bf4ce0bc34a454a713f 100644 (file)
@@ -10,7 +10,6 @@ CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -73,7 +72,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index 66769e03c77d5c4eaf04b1ec4fb42a07f93d481a..35945812a7c8e8f407c3bfcc905afe0d4eb0bf4f 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -73,7 +72,10 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index 8b5b81448a5dff24c7c5bf79703dbd0991004f0a..0d27e49c8ddbb861dd35996a42860dca82c77e64 100644 (file)
@@ -10,7 +10,6 @@ CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -75,7 +74,10 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index a0b12d049ef3ff338e05260e14fa02edf81ea9fb..ef75108eb9771b88c56adbc1d806cff7f48f65b4 100644 (file)
@@ -10,7 +10,6 @@ CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -70,7 +69,10 @@ CONFIG_FSL_ESDHC=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index f48b0f92f72d8e0253aa150a7727b4b5bc118820..cf2d5de9547ce29db2285247096c18dba7dbae4e 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -79,7 +78,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_ELBC=y
index bf7287417e9674791e7fee88d29e19fa77944f08..81f04aecf22ab771f1f90e82f5ccaca8eab3cb55 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -75,7 +74,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index c3a5f630a9741a6a427f16c40342a1abc8a10038..fd28f3d8c77538c855198ab9cf6ca09490ab7a06 100644 (file)
@@ -10,7 +10,6 @@ CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -77,7 +76,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index 9dac9e94c64b978a440cb6c95d17e35f32093a02..5933485c65b11be3911327b70869bf0a945b5a38 100644 (file)
@@ -10,7 +10,6 @@ CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -72,7 +71,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index de2b09c18fe95277084501ff9bac4d35947af615..1140bc0aecbfcaab12bc694bf703d4888694a10a 100644 (file)
@@ -14,7 +14,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -102,8 +101,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 3a3cff873b2dde9b3a673ac4856f2bf2cc32fd38..05c43311b1d863aebc6b0275a7918fec50bf8591 100644 (file)
@@ -15,7 +15,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
@@ -101,8 +100,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
index 9499f585f1a669a547b1a633b78eb562225b20b7..8c82ee8afa22c7c0ab397b8f8296c4aa7e483a52 100644 (file)
@@ -17,7 +17,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
@@ -104,8 +103,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
index da28ef143f8426fb6cab35c08942a38525cfa1f4..700bbd98af992f02f87e33731bb916b55bc92d68 100644 (file)
@@ -10,7 +10,6 @@ CONFIG_TARGET_T1024RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -76,8 +75,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
index e51e363cfdd7a12eec2aa98ed8ac442ed409d6c4..200536a7fb0d54702eb483f6d9771912e11404d5 100644 (file)
@@ -13,7 +13,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -98,8 +97,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index e86f0fa99a66e5a106607ae6bc8f5728cb14caa0..281cc7169b9c5ca42d263dfae3e2e59a0bc2ba64 100644 (file)
@@ -14,7 +14,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
@@ -97,8 +96,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index c8d8857ccbc9ef5f350fa8c9a70f0ddbfa864c6c..c7b337a668130ad7142e128ba4e8b49ac713d70d 100644 (file)
@@ -16,7 +16,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
@@ -100,8 +99,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index 1f3d6f6985fd5f83acfc98d3614808199c2bd302..4983a522318350d919cf97f122fc17c21da14c43 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_TARGET_T1042D4RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -72,8 +71,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index f9475619603caf68359273ac6d518471db635f30..30669d88e84ced2a8d5df3a9b6a161b318808a35 100644 (file)
@@ -13,7 +13,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -105,8 +104,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index d83d365423767292868c2475f75388db78b737bf..17629f13498bd44012d894c0b2c10db26aaa2bb7 100644 (file)
@@ -14,7 +14,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
@@ -104,8 +103,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index a18ea5651665ec78208d508ac6a7bde2d62366b6..4c62d9316d21544a962daa382807098e25835d33 100644 (file)
@@ -7,7 +7,6 @@ CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_NXP_ESBC=y
 CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000
@@ -78,8 +77,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index 160e697159fb5a69bac38c56ab9f66af67c5d49e..f68c87411e7b19c3b34ea60325c6d3c41c034207 100644 (file)
@@ -16,7 +16,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
@@ -107,8 +106,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index 16563ea8afce0a6464f3571f6e8ee483bd89f400..ef29f474c94fb6e28e56495aa866b36b993ae89c 100644 (file)
@@ -8,7 +8,6 @@ CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SRIO_PCIE_BOOT_SLAVE=y
 CONFIG_PCIE1=y
index e7775dac0b808916ad26c8c75845336c63790b76..62263b2fd4da3707b374304c3b1dba96c212b982 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -79,8 +78,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index 472e5779af644aa1e1b31c5c1d4deb6d03aab09d..a1db4a4bf8fa7943356b0b4227e13e118987903e 100644 (file)
@@ -13,7 +13,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -107,8 +106,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 6882baf164afcd1f937930f8e9b022505dc0d13c..6e9c7082222124453f6fa9a7221fbca9fee502f4 100644 (file)
@@ -14,7 +14,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
@@ -106,8 +105,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
index 5b1824ddb9bdea29194e70cb72a6c99924ea379e..719f022e8b07181fb789bda11178e6b93bc99c3e 100644 (file)
@@ -16,7 +16,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
@@ -109,8 +108,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
index 6c6835eee316c11b4edf0b3bf5e3e261dc1b5c56..1117c015eeac692b12cca66399e05b001198add3 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_TARGET_T2080RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -81,8 +80,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
index a34c7caec7eada2bf0a3a5e47aa3e1814cabeb27..10991e196469068d850e4c24b9212d4bc42f3d8d 100644 (file)
@@ -13,7 +13,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
@@ -108,8 +107,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 0f503a889cc1dc8dd4042f5076f696cfe893d320..0aa715dcac363d2a678d4c4198333bf41a0e7139 100644 (file)
@@ -14,7 +14,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_T2080RDB_REV_D=y
@@ -107,8 +106,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
index d5845febd8d8af285b224e05a62134e3534aae47..07114a07c20bc3d88ded28552390d0bc8c2977e7 100644 (file)
@@ -16,7 +16,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_T2080RDB_REV_D=y
@@ -110,8 +109,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
index e599c4e640e80f263bd9ce9d1c30e983a752b57c..99b9c7931772bd930fe41e4de6dff8b9d3029bf6 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_TARGET_T2080RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_T2080RDB_REV_D=y
 CONFIG_PCIE1=y
@@ -82,8 +81,11 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
index bd467ac7cfb5cb0217f3c3660887ae48072611de..df3b5f3bc6fb617875cacbab0c036acc5d441983 100644 (file)
@@ -14,7 +14,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y
@@ -93,7 +92,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index 5b7849ea6ba867cc3e5d0884559c08a6973d439c..dc73dcdc1df648ce405c92d6b8a2d002045707bc 100644 (file)
@@ -9,7 +9,6 @@ CONFIG_TARGET_T4240RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
@@ -68,7 +67,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=10000000
index ad549c02c1528794176983094e5f9c1598a2487f..71ee97969d9905fd081f4d2d8391faf25082bd54 100644 (file)
@@ -35,4 +35,5 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MCFUART=y
index 9f5cb8702c6d301ede17a4dc52a1d5634bb774fa..b62e21c93368439b15e01be8575168c2034378b8 100644 (file)
@@ -44,6 +44,7 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=259
 CONFIG_MCFRTC=y
 CONFIG_SYS_MCFRTC_BASE=0xFC0A8000
 CONFIG_MCFUART=y
index 7b975813928c11e6db84516cbd3ef80e2ef63ceb..bd74eeae74ab890baef9a49e69cbba0cbb9ce794 100644 (file)
@@ -51,6 +51,7 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
index 2c354f3b5b513216ff06ed996adf1a66f92f03a2..c33fedb5497205736c8583b6c705062f319a23f7 100644 (file)
@@ -52,6 +52,7 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
index 42f3dc4b6f4790b6fd481750fbc537c284901ee9..8167dd17aad179406323b1fcc2619aa680b36b03 100644 (file)
@@ -60,6 +60,7 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SMC911X=y
index 2be57d2d1ed9e6271b956554f7418df70efe9284..16c7a401dbc1619091eba51855b0fdc52a256126 100644 (file)
@@ -45,6 +45,7 @@ CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
index 524564355f444157980d8731b3df6b99bedbaf18..cc73d3b156fe3f93a1bdb08ef32534e53b6434e7 100644 (file)
@@ -46,6 +46,7 @@ CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
index 7bb4e692d6b7c4a33a0f8fb2b78553937d934a9b..dab4a9f3af59a96831ab6cd5c5e4a41a4bad3c31 100644 (file)
@@ -46,6 +46,7 @@ CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
index 8ae2f235b1a7de5e3b602870efcb50ab293fa649..0ded7cfcdf9a4194726ae51f355c9bcf8b710e44 100644 (file)
@@ -47,6 +47,7 @@ CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
index 4a41e6b5cc64ac13bad37e8a6fc8161677f54fc2..e5c370699dbcb4e8785c426f6dc24ac1003bdc8e 100644 (file)
@@ -46,6 +46,7 @@ CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
index 0670ffabbbb2c13f9acc232dcbb78c43273e5cb5..4c141f45fb581ffff07afe17de6e8ecc100c93a8 100644 (file)
@@ -47,6 +47,7 @@ CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
index bf7f709524b93fa93e4c8afbaa87086bda23f06f..7b8b9b82df3bb1569ea79de9ddf375f3a989566d 100644 (file)
@@ -46,6 +46,7 @@ CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
index e1d46d30606af0d534576fdb18572491b306dcda..f657cb872b39f4a7d19fa362bf435b89643abfde 100644 (file)
@@ -47,6 +47,7 @@ CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_ETH=y
 CONFIG_PCH_GBE=y
index 42f6087d83c911022122134b1c27978e7e3ae7d9..e8301c6301a54d10d42496682b7e47dda9716e8b 100644 (file)
@@ -50,6 +50,7 @@ CONFIG_SYS_BR7_PRELIM_BOOL=y
 CONFIG_SYS_BR7_PRELIM=0x701
 CONFIG_SYS_OR7_PRELIM=0xFF00007C
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_SYS_MAX_FLASH_SECT=11
 CONFIG_USE_SYS_MAX_FLASH_BANKS=y
 CONFIG_DM_ETH=y
 CONFIG_MCFFEC=y
index cb2caf454350b0adbb7828fc7b852c3ffcf57b76..4ad1d56cab4ff7f67f5cda208909750908035385 100644 (file)
@@ -51,6 +51,7 @@ CONFIG_LED_GPIO=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
index b7174ff5ee34850fa85ea7a87249a31ff904c275..dc0f7cee4efcf3621ae69914a8915af399b88ea5 100644 (file)
@@ -51,6 +51,7 @@ CONFIG_LED_GPIO=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
index 8f6b8b9702f41fd1c4a559c890ed67a22afcf8ae..00ba7d7687ac35939881c7166b895454e1b5ef11 100644 (file)
@@ -69,6 +69,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=67
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
index eae073d76ea6d6e6a0c4aa13d8e4559b42872fed..744ffbd94333b530dfa5cb679868f2000b10c3a2 100644 (file)
@@ -66,6 +66,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=71
 CONFIG_MTD_RAW_NAND=y
 CONFIG_SYS_NAND_USE_FLASH_BBT=y
 CONFIG_NAND_LPC32XX_SLC=y
index 4cf03abc61e4a85822a9c836b4d2c69d22b789d7..378de4bd8c29663d844074d758cd88e5e18988f2 100644 (file)
@@ -48,6 +48,7 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_ETH=y
 CONFIG_MCFFEC=y
 CONFIG_MII=y
index 1178515846933c351084f7d0ccb7651a8ff2c0c5..ef0512c8f708b0cf76e5ca7b4e9e7cec75d9aebd 100644 (file)
@@ -46,6 +46,7 @@ CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_DM_ETH=y
 CONFIG_MCFFEC=y
 CONFIG_MII=y
index 6b7cdbe4b119991bf33c005125eec1e92a3cbf3b..1cd0ac020b2a3a0068e22b57efb63c62458442df 100644 (file)
@@ -65,6 +65,7 @@ CONFIG_SYS_I2C_SLAVE=0x0
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=11
 CONFIG_MVGBE=y
 CONFIG_MII=y
 CONFIG_SYS_NS16550=y
index 796b71793a7f090891a11e59414715f744ece4f9..6725e3aa6813a565778c8f5bfc15623dd530f60d 100644 (file)
@@ -71,6 +71,7 @@ CONFIG_SYS_I2C_SOFT_SLAVE=0
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_SYS_MAX_FLASH_SECT=32
 CONFIG_MTD_RAW_NAND=y
 # CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
index a81aa00f2dba481b22816f8296713a41ee1e3b35..cabe2897707ac3fd72235aff7b1418ff9d818508 100644 (file)
@@ -191,6 +191,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=135
 CONFIG_PHYLIB_10G=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
index 2b5a58714102eb341e644ab5ec292ace35c17b5f..daa6ba0f865e59283ad37f06c321162c2a64a0f1 100644 (file)
@@ -51,6 +51,7 @@ CONFIG_LED_GPIO=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
index 74dfc6680420e882c15d601f1716c0fd30003a8c..1f0a864697023a5486ed79d890677e4d947665f2 100644 (file)
@@ -194,6 +194,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_ELBC=y
 CONFIG_PHY_ATHEROS=y
index 86a3bd994a4de4470c08dca662ed7dc7f2d4d29b..a283407a95de70e218a0adcf021e83ffff5562c8 100644 (file)
@@ -7,13 +7,12 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ENV_SIZE=0x1000
 CONFIG_ENV_OFFSET=0x400000
+CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg"
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
 CONFIG_SPL_TEXT_BASE=0x7E2000
 CONFIG_TARGET_IMX8MM_EVK=y
-CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg"
 CONFIG_SPL_MMC=y
-CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
@@ -39,6 +38,7 @@ CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
 CONFIG_SPL_I2C=y
+CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_POWER=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_PROMPT="u-boot=> "
@@ -78,6 +78,11 @@ CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_ES_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
@@ -96,28 +101,14 @@ CONFIG_DM_PWM=y
 CONFIG_PWM_IMX=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
 CONFIG_IMX_WATCHDOG=y
-CONFIG_NXP_FSPI=y
-CONFIG_SPI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SF_DEFAULT_BUS=0
-CONFIG_SF_DEFAULT_CS=0
-CONFIG_SF_DEFAULT_SPEED=40000000
-CONFIG_SF_DEFAULT_MODE=0
 CONFIG_FSPI_CONF_HEADER=y
 CONFIG_FSPI_CONF_FILE="fspi_header.bin"
-CONFIG_READ_CLK_SOURCE=0x00
-CONFIG_DEVICE_TYPE=0x01
-CONFIG_FLASH_PAD_TYPE=0x01
-CONFIG_SERIAL_CLK_FREQUENCY=0x02
-CONFIG_LUT_CUSTOM_SEQUENCE=0x00
-CONFIG_LUT_SEQUENCE="0x0b, 0x04, 0x18, 0x08, 0x08, 0x30, 0x04, 0x24"
index d885206a472ac8e26e324fb464ec2df8792716a1..55269f3ab9bd91c79b7dc367089df47eb2715a56 100644 (file)
@@ -66,7 +66,6 @@ CONFIG_IMX_RGPIO2P=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_IMX_LPI2C=y
-CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_FSL_USDHC=y
index 1f59f7e365d3a27f291d24fe4496f7bcb9b7ccf9..a7212795eebcb6d069cdee2542068945287d8387 100644 (file)
@@ -75,6 +75,8 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth0"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_REGMAP=y
@@ -83,7 +85,6 @@ CONFIG_IMX_RGPIO2P=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_IMX_LPI2C=y
-CONFIG_SYS_I2C_SPEED=100000
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
@@ -113,5 +114,3 @@ CONFIG_FSL_LPUART=y
 CONFIG_ULP_WATCHDOG=y
 CONFIG_LZO=y
 CONFIG_BZIP2=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eth0"
index 5f4ec5ff8f0e3f7af2b46743421032a4bb3bd308..644876e0b2445691dd85b442948ae5dd02470dcc 100644 (file)
@@ -30,7 +30,9 @@ CONFIG_SYS_RX_ETH_BUFFER=8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_BAUDRATE=38400
 CONFIG_OF_LIBFDT=y
index fb86b7cf2996e27787cdb7575e854dbe7e655532..9cc8070faaa807711a1dd24b5b0a7000aa9f7d96 100644 (file)
@@ -30,7 +30,9 @@ CONFIG_SYS_RX_ETH_BUFFER=8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_BAUDRATE=38400
 CONFIG_OF_LIBFDT=y
index 6bf08cd13aefd3a3a52883efb3a19822e8ae3c03..9f7371f17e6d805263535210305b27d1962a83f1 100644 (file)
@@ -30,7 +30,9 @@ CONFIG_SYS_RX_ETH_BUFFER=8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_BAUDRATE=38400
 CONFIG_OF_LIBFDT=y
index 97c44f3695544d01306c48f0b5daf56ea0c0b9c2..3f7f3e49882f3dcf97b87f40edf55a48091626a9 100644 (file)
@@ -30,7 +30,9 @@ CONFIG_SYS_RX_ETH_BUFFER=8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_BAUDRATE=38400
 CONFIG_OF_LIBFDT=y
index 89cfa9b9a6f7e5493afc03cba819eb9ce55baf40..95d82b578dbabaee94df259eb9f159d50101d455 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_BOOTFILE="uImage"
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=64
 CONFIG_BAUDRATE=38400
 CONFIG_OF_LIBFDT=y
index d895ba4629204d538ef0493466da619a36371aeb..61191e2b53be3174d5af2954dd4263234a6759c1 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_BOOTFILE="uImage"
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=64
 CONFIG_BAUDRATE=38400
 CONFIG_OF_LIBFDT=y
index 9cf449cb4c8186254e32784bfcc5a10fc5af37a7..b8b27da23b8a21cdb7ed044e300622a86ede2d0c 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_BOOTFILE="uImage"
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=64
 CONFIG_BAUDRATE=38400
 CONFIG_OF_LIBFDT=y
index bcbcde2112858baef25499616ba0a005c1cf82b2..60e0979ee42a4883e6de4c71450428311d8871d9 100644 (file)
@@ -33,7 +33,9 @@ CONFIG_BOOTFILE="uImage"
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=64
 CONFIG_BAUDRATE=38400
 CONFIG_OF_LIBFDT=y
index a0c92441cea018834b2c282f74c878a0a7a576df..dcc0b2987d1b0b1e9b9d04656acd7008631bdfbe 100644 (file)
@@ -12,7 +12,6 @@ CONFIG_TARGET_KMCENT2=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 # CONFIG_DEEP_SLEEP is not set
 CONFIG_PCIE1=y
@@ -73,8 +72,10 @@ CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 9a944cad39c26b6f6d36a4a201830fca861ff96b..58191c114c54678d975a537f41e7cfb25f65aba2 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SMC911X=y
 CONFIG_SMC911X_BASE=0x10000000
index 92fa4f000ed3f442301d6eaaadbd353e925d5df8..778f22ac911a32956e75708b8e702058cf904ce9 100644 (file)
@@ -79,7 +79,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index fcbaf9b685e02904dacb5ac69575f99cfa2cd07a..bf6ddb6cf012fff35ba45370ab92533d345dd7f5 100644 (file)
@@ -79,7 +79,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index 19a21f4a04757d6076f0c0dd05a39929ac9f6aa5..da92ac13a102e44d87c6c0198324298b1b016c36 100644 (file)
@@ -111,7 +111,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 727475f622645323585c4755b77f3ef9cf571560..ee2c6b82edce44ee274cf0cb0f7e49bd01d838f1 100644 (file)
@@ -78,7 +78,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index 82c6a1bdc3bc28d691ffde1869eea930dc452653..484ff026ba756e6ee29fc2d7f99f214ee5ef58e0 100644 (file)
@@ -81,7 +81,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index 438a8ecf0ae64565f3c61473edf50f813dfea8fe..c19fd26dd6dc919a9f04fc3bef1badd8dcdc7365 100644 (file)
@@ -81,7 +81,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index cbb7c55944f946cdce62be4f19b429341823d740..66cee0b3d6eb8f2e49e0cacbcc83f8ffcd41f4a2 100644 (file)
@@ -109,7 +109,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index b86a60fd32643dfe3041f037c236b806d6e4cf31..7356b3d6e147645d818a7568808d0bc8bf2d97ac 100644 (file)
@@ -65,7 +65,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
index 0410249b316b974e04799a52adfca3a4e606a819..fdf66f662bf156258b414751bbea828c7f1c865c 100644 (file)
@@ -68,7 +68,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
index 82e3b39a522e73c51996b1c28c58c19d21441feb..55b30d39003e2c8cf9a6ae27c86aa933bb54d8c0 100644 (file)
@@ -68,7 +68,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
index d247d114f393e6c68b32981385a1b718e3caae88..118a085ec3f20e847738beaaa07c7669acaccaf3 100644 (file)
@@ -96,7 +96,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
index 855657ca37a09dc97b9db44d957a7f2e1af8b554..c87581d18efef17fcf14d05e578149a8b45a7a1f 100644 (file)
@@ -96,7 +96,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
index 364a34751fcf4624cfb395ae9af3ae6c2b2f4b8c..d7ff7e2970fb72df42215069680032f9f7230e3a 100644 (file)
@@ -79,7 +79,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 7b083b32fba13c45eb8a5d4fb670fdd8d13ee9b0..462fad1cd48fb76711cd747984b2d26514d337b5 100644 (file)
@@ -79,7 +79,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 7446f01272e0eaab2d54a8c80e221a0f207c28a7..63287ca533b3f6f7fbaeaaaa50a52ceb22531543 100644 (file)
@@ -108,7 +108,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
index 6dd797c652b9bbafdd37bb14b09bdbaaff039f4f..fc72f4cdaf649c96778beae40b5f4caa74f02e75 100644 (file)
@@ -80,7 +80,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 53f19a376ee8425cb0422ffb727fcf573a55f65b..172ab723c61b6cf98297ae000f5ce89d5c224da8 100644 (file)
@@ -106,7 +106,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 1ebe893b43d41b179ac7a3261c65d37ce3c3b154..b414d400e6a1e8d0fcefe4d816fd2fd8ffa668f1 100644 (file)
@@ -76,7 +76,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index d04d1d918b72eddc1d06953cc40089a667ca10fe..9bac24a27b30ee66ad75a9bd55741ea48a5e9e30 100644 (file)
@@ -85,7 +85,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 787c8f96bd56a1a25177a0f4ef25df95dbcf99bb..0a40bf0f9f994eed039e90e308e0182a94f17a77 100644 (file)
@@ -62,7 +62,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 341fb0f926983713d80bab504620bbe73dfbf7ca..f27eadf3921140d5447c2455c8841b22080e179d 100644 (file)
@@ -65,7 +65,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 305734d748228db6f0429afeee96ad384a485558..da23382940f8694c52f909c02ada4b8ca23c7f24 100644 (file)
@@ -85,7 +85,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
index 56cdef82216da60e73641ccdda96581f4fdb7395..2be08bbb7b354baefa640c65d8b293045920332d 100644 (file)
@@ -92,7 +92,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
index bf2805db9e94f7719662377ed57eaa7183aefa06..d9b841df1a4eca7fd1555d21cce926fe697f2dea 100644 (file)
@@ -86,7 +86,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index f1370b5104b6db41b1387cb27c82177f3f3a2082..79feb55dfb15f18b40afeafa88b54ba8094de7dd 100644 (file)
@@ -90,7 +90,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 12ccb78b9210e312a300b2703bd5ad935c15965c..3aafd103df3841a4dbd797004c214d7366096a27 100644 (file)
@@ -61,7 +61,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index db5229487216cfd091d25fc54f31faadc8949d65..f9cb304ba1cc51d5cdc395a985ef2a1c7a64f2a3 100644 (file)
@@ -67,7 +67,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index fdeedca476787e64d8166f89f6d12726bc840f8b..3a71185b865ae114f5956d68b82f39a0ffa7c8b7 100644 (file)
@@ -76,7 +76,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index a66099c815dd4535dedffd6cc908e250bdb4c82c..35abfb323f653b028487b3f67507467cea6cc999 100644 (file)
@@ -79,7 +79,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index 835159deefbb2bfe5c3c65b73f8a6404a3625b9a..5316c80c83d2a9bfbf31fda5800c8b456c3dd1f8 100644 (file)
@@ -79,7 +79,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index 2a70d660ed66f37ed6470f65fe55b66151324175..8550190d22952ef2ffa33057fe1feb0d89bd9be8 100644 (file)
@@ -106,7 +106,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 11554a831d5a0977cf08986b10c053952cb14cf8..6cdc78da3f0f2ef56b980a6d1bb0d25f60b21b2f 100644 (file)
@@ -107,7 +107,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index 7fd24122f041cb3014e99ff0d416b6f6d7fdc4c3..7efa5cbebd0724a407d05585471c954d5efb5533 100644 (file)
@@ -76,7 +76,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index 52d3d302d94266db83cefef7f6a952eca1f2dc5a..3846b95e71d57f0aa96699dd4d6b8f84173aeb93 100644 (file)
@@ -85,7 +85,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
index 64d87ae9b4f3cf7cb6261a082cb5b3821b537987..aca271aa9f5f9fa77b6e3bad5b74e2b39c1bbaa7 100644 (file)
@@ -75,7 +75,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
@@ -86,6 +89,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 3af10a0e0627bb01d5c21d25bf9bc941f34b287a..9bed029a349fcc5df358ee7ab0fe0258f9e0b80f 100644 (file)
@@ -81,6 +81,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 55a5389272a4d15fdfd948b7adb88badcfd49e25..4a56e43e2bf5f6c700a8d5a9fc96416ccdbe21ab 100644 (file)
@@ -84,6 +84,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index d3b068483968c242d97ada4e45c78039d57ccfed..d203fb9b13d179653b5f976474b54fb2200cb87c 100644 (file)
@@ -95,7 +95,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
@@ -105,6 +108,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index fa1f71d77c1f111d97e412fc319f632fb4750d57..1bd83af1018964c4245bae02b6ed30c7dba1eea6 100644 (file)
@@ -103,6 +103,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index af5ecadec9d376b871af795cbf4076a34892786b..c59de47ab63c0c8088f4b5e59119234512890443 100644 (file)
@@ -83,7 +83,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
@@ -100,6 +103,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index b4cae480e17549b4684609fc225eb1c6a6850547..aa9bc8a46c364d5a928d3fdb31fdad6791f48e8e 100644 (file)
@@ -78,6 +78,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index 452ee839b87b42127ab19d928544a4501a202d8c..2459212c36f58d06403901452bf7e644ed4e5ba8 100644 (file)
@@ -81,6 +81,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index e36512e62d5502d3137199a93c0b0988ee6292db..fc222b5dd2c3c844cf638d6898932cada735a71d 100644 (file)
@@ -100,6 +100,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index 2f81a1343c171eccbb1a6a90f4c26731a1fffad6..eba206dd7bba3a06b358a9e9fc87f485891344e0 100644 (file)
@@ -100,6 +100,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index b5f556dc2035ef0d7d94a51cffca8a5f75c1f537..347cc604105d21a58b227d6a79ea60f33f5a7694 100644 (file)
@@ -77,6 +77,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index 3af7828887cdd605e4071638a2d41783fd661960..362b4bea2b531de46a26ac08bc2f90a25c6692ef 100644 (file)
@@ -83,6 +83,8 @@ CONFIG_SPI_FLASH_SPANSION=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
index 91cb2df6ee1a01ab48e1b53d8df828088713d199..afb4e48e7e85032213178f01321377878b00bf29 100644 (file)
@@ -56,6 +56,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
@@ -64,7 +65,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
@@ -78,6 +82,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 8aef83af820fb7044238ed44b5646fcc279c55bc..15dadeb4e42027aaaff0bb4aeea2f7af53d912cf 100644 (file)
@@ -59,6 +59,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
@@ -67,7 +68,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
@@ -81,6 +85,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 1d841af6b0c6f8197a0a0cd141856b4162e6486f..9fc1801c15da01e420e69afb79df302b9a39e7e9 100644 (file)
@@ -79,6 +79,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
@@ -97,6 +98,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 302de323988890bb74c7f3acaa682569de5d82db..d2dd95ea792d327165395b419c57bbe9b3a81172 100644 (file)
@@ -60,6 +60,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
@@ -77,6 +78,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index e97284222dcd820d3290803a4688b724b8515685..e2e4cfdd936480482723e2fbf3e1052dc18dc481 100644 (file)
@@ -74,6 +74,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
@@ -91,6 +92,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
index 4fab4fb3b1508915389bb88597e442c7996a2cc8..5378876f11b9a319c958a907a36a4d0f18d428c3 100644 (file)
@@ -60,6 +60,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
@@ -67,7 +68,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
@@ -77,6 +81,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x580980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
index c3327cd0b7cc8f8ff9c421e797930735cf1f7075..6570a466e0c5670a55eb737c2e9fe156972057de 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
@@ -70,7 +71,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
@@ -80,6 +84,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x580980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
index 6c7b49b71c2cf9f0a310cb8202418e3ca6da6777..7c87f890c2c2f145c2daedebf90fcb6a2c7952a9 100644 (file)
@@ -83,6 +83,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
@@ -90,7 +91,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
@@ -99,6 +103,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
index fb7faa46d2cb14e24be3b8d2d4bb6343f331ff56..a426d6d48fb148f6509ae51e76052c9d46ab7f51 100644 (file)
@@ -61,6 +61,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EARLY_INIT=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
@@ -72,6 +73,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_E1000=y
 CONFIG_MII=y
 CONFIG_NVME_PCI=y
index dc0f6f886bdf645c65cf340b907936929ad82784..f082fa52bcc5f6df7c063a39caa5f59d50a81a97 100644 (file)
@@ -66,6 +66,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -78,7 +79,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
@@ -92,6 +96,8 @@ CONFIG_PHYLIB_10G=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TERANETICS=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index b86f8164f0b85a5a42fc94195747bcace6462391..1972fc908f54536d049cdadb61af14bccc58d0a3 100644 (file)
@@ -56,6 +56,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EARLY_INIT=y
@@ -71,6 +72,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index 9e08552fb375d41006eb580344da6def57eac24f..dedc191edc0657e8e98653bb245654aae2b24ad5 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_EARLY_INIT=y
@@ -78,6 +79,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_CORTINA_FW_ADDR=0x980000
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index 8d970cce429d3d3f7a56055ac8a2a6c95fc14fff..1674a2ce0916904ccc016dc88a5e848af7a0968e 100644 (file)
@@ -61,6 +61,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -72,7 +73,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
@@ -83,6 +87,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index d70d3cbf90b35b4e900e0dbe1973d9bf3d9b5b4e..071db6b1d2e4814444d3217b5a7393e425d43c49 100644 (file)
@@ -68,6 +68,7 @@ CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -79,7 +80,10 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=1024
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
@@ -91,6 +95,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index b2bc71afa8ef60c56feca83bb35cbdb86f9c9885..84aea7fb17cf8f9b834b63e1a49963407656bfa9 100644 (file)
@@ -61,6 +61,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -82,6 +83,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index 32e47c326e8f2166a210fabc2c7d8e68075167e5..7fce30b3311e594e98535c6fdbeb92ed3b56c9df 100644 (file)
@@ -68,6 +68,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -89,6 +90,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index a758a4dca2296f652ec207b644180330bef63f47..42efefa41630bfc8d49c02178efc477272c16f73 100644 (file)
@@ -59,6 +59,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -75,6 +76,8 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index e6e794006cf63c293a0c1a5df91dcc8a56327dea..85ee4ca84589ca7ea88445aaf8c31ddae4487712 100644 (file)
@@ -67,6 +67,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -84,6 +85,8 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index bbdcb895d8e4fb614a27bc9faf46acca5e6a4eb1..547c8682e55c7d08141c0523f1ba0ecf0784393a 100644 (file)
@@ -67,6 +67,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -84,6 +85,8 @@ CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index bb81e56fed81811677901ffdbd4b0ca93ab3de41..421008489bdf2aba131f90360eaf886e62ef1c8c 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -84,6 +85,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index 216ac800742007fc3383d2251b6adbfa448979de..dd1c0760987df923a3e95f6607ee416c43aac181 100644 (file)
@@ -70,6 +70,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -92,6 +93,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index b7a4238e92eac6899b42e2634adcb7354427c1a5..70faef837209ba8054de364a6da54dbd9a690fee 100644 (file)
@@ -71,6 +71,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
+CONFIG_SYS_FSL_DDR_INTLV_256B=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@@ -93,6 +94,8 @@ CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_VITESSE=y
+CONFIG_FSL_MEMAC=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_MDIO_MUX=y
index e55b4a491455cfee25621ea3b0a8f642b73f051b..60a8815194bb874d8778eae060b249efaf4ab2f2 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_PCNET=y
 CONFIG_PCI_GT64120=y
 CONFIG_PCI_MSC01=y
index 6c6492d3febcc9fdf02dee06608c1285b1eb7c3e..b4b0320fc0a0d9585e1ddca656716d7ea56179c5 100644 (file)
@@ -40,6 +40,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_PCNET=y
 CONFIG_PCI_GT64120=y
 CONFIG_PCI_MSC01=y
index 3aff68b0188f5ecfec335575ccd52c73acab05cb..ade98e6236580c876a1867aa7afec12a02a69994 100644 (file)
@@ -37,6 +37,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_PCNET=y
 CONFIG_PCI_GT64120=y
 CONFIG_PCI_MSC01=y
index e268fb63743f36182a1a86ca36d2054595f8d801..ef31afe86aa0842de3bb041fbe124a4b458e7790 100644 (file)
@@ -39,6 +39,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=128
 CONFIG_PCNET=y
 CONFIG_PCI_GT64120=y
 CONFIG_PCI_MSC01=y
index 80b59cbb053b5c7545062e92a6d9ec20b8ce0f09..1fae517ea04e7028c29782ccb3d7b348a9adc472 100644 (file)
@@ -64,6 +64,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
index 6984256a1c2d5c0b35c1fc723fb313170a74b608..111c0f07c7c0e5a847982872dfc7c74341925d5c 100644 (file)
@@ -61,6 +61,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
index ad61859b897eedeaa5d5993cb721bdc44709f379..192bf9873a48b6c4f71d78b133adb800e1375ca5 100644 (file)
@@ -66,9 +66,11 @@ CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=2048
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
index ee83cd40c1ee5b2d07cf4a739cee261aa7782d48..cf251abb9585c3d6e693ceac62208ccb9b940ad0 100644 (file)
@@ -52,9 +52,11 @@ CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_SPANSION=y
index ab5dfad28fccbacbb510acbe34a6c10524109f76..6702df0b22d7066544ea6d6b1aad163476b4fb3a 100644 (file)
@@ -77,6 +77,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
index 8c5bc19f10bfd9635309886fb9e3555303c8146b..b161fe2369ecba87947267f4c2b2986805e6040d 100644 (file)
@@ -78,6 +78,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
index bc58a631bed3007df127edbc9ddef39fc226ffe5..e1cbc0c39c5bfd42f954b436b0164841d1d30797 100644 (file)
@@ -81,8 +81,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 5d70160bd3b95ac2641b083f9febee4b3a1c8a1f..a381c8f41293d40965162d72da96af8cab679b24 100644 (file)
@@ -79,8 +79,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index a604d3248f2cab11b7fa1e959094f4fae7e17f41..39c43ec3987e26a1681a2e7596bec0bd3285466c 100644 (file)
@@ -81,8 +81,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index dfd6d627e1c1b24d6f4bbc284d78030b27d1f6d6..3e057591cacc0a55493c697898498d454c1f86e1 100644 (file)
@@ -79,8 +79,10 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_FSL_IFC=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index 6922380b0093ac1fd9c101a977a2d52e50d285cb..a5256b7a1811e55a8ca3e2cb63e9f2956d98c6c4 100644 (file)
@@ -48,6 +48,7 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_MTD_RAW_NAND=y
 # CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
index 2b4a844d804b5a0ee527aac40d42d992969d9eeb..b7a8124e305565993191ded3f735c9e8486a19b3 100644 (file)
@@ -52,6 +52,7 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_MTD_RAW_NAND=y
 # CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
index f7c93ba2af543dd9be98a0307ba914202e281f06..8d7bc19b7ae28b69e4c083ea28e226068a42cb0f 100644 (file)
@@ -50,6 +50,7 @@ CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_ETH=y
index 50945472315ac659ec631a1186e563ae045c880e..b2bc149e460c1b7e2a45661e270b5ff7317bcd01 100644 (file)
@@ -52,6 +52,7 @@ CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_ETH=y
index 2beda3a2fe0a61a7e90c09a61dc1c3c8490260f9..3af338c90bc329819288f8fc6e35bd8b32ddf416 100644 (file)
@@ -45,6 +45,7 @@ CONFIG_CLK=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_DM_ETH=y
 CONFIG_E1000=y
 CONFIG_EEPRO100=y
index e667d23d7eea61824a207bac5d8e0d135b7197eb..04ad54eb1f1c5f31b09260f5022aa012b81eea10 100644 (file)
@@ -83,7 +83,9 @@ CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_RENESAS_RPC_HF=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
index afccf86461df40974c5e71d0957b30a42d3e0a10..de25e525f9218bda7f52d58d69d0ab4e4d5563d1 100644 (file)
@@ -77,6 +77,7 @@ CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_RENESAS_RPC_HF=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
index d423ad7b82615f484e1a9434bc904baf71a1c70a..9491b78ea36894e87ecd3c2462ce3b8d20a85e22 100644 (file)
@@ -86,7 +86,9 @@ CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_RENESAS_RPC_HF=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
index 341abe4f6dda44d46b9110a63cbc551986d904b1..a7e375978c53bb5807cc9c9b2c41b3cbab96f370 100644 (file)
@@ -85,7 +85,9 @@ CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_RENESAS_RPC_HF=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
index 40a8c028c2dc7256a4fc4a5f31650c4bce083e7d..0f06d4309069c1424de18dd27ff7540007f31bde 100644 (file)
@@ -83,6 +83,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=131
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ATMEL=y
 CONFIG_ATMEL_NAND_HW_PMECC=y
index 772511543dbf0cdf885256ed4d5d3f6bb640e5a4..f29a1b7727d76e9867010bf5a35bf105b45edd93 100644 (file)
@@ -82,6 +82,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=131
 CONFIG_NAND_ATMEL=y
 CONFIG_PMECC_CAP=4
 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
index 4e85807432e5d9a13cf36b7c085df54522ea24f8..cfd6ae1b4c0b700ff2c365b4501f61b65959175b 100644 (file)
@@ -84,6 +84,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=131
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ATMEL=y
 CONFIG_ATMEL_NAND_HW_PMECC=y
index df008b797f869af3aaf2b74c951d965e7317544a..4334182c7f85bd01ba04f5e7baeaad43a4668959 100644 (file)
@@ -53,6 +53,7 @@ CONFIG_LED_GPIO=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
index 60a38abc8e3a670f7318d913180281957e7072ba..251586178ec2adfdc6c124f38014097dc426602f 100644 (file)
@@ -73,6 +73,8 @@ CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_MTD_RAW_NAND=y
 CONFIG_PHY_ATHEROS=y
index 64610658c7bda953cfbbe4b0b584ad1eaeecd29e..aa4e98acc5842f7af0ebc47f9576fc882e4e730c 100644 (file)
@@ -42,6 +42,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_STM32_FLASH=y
+CONFIG_SYS_MAX_FLASH_SECT=8
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
index 753a4b80cbbc12d29656e4b474f2fa24ca07b3cf..feba985168802236888057b6dd87dbd537b4d2f2 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_STM32_FLASH=y
+CONFIG_SYS_MAX_FLASH_SECT=8
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
index fde427ae692f04c02cfc1797cceb7fd267c81138..b347347e253c43e56d27a5e8861bdb53d32462e4 100644 (file)
@@ -32,4 +32,5 @@ CONFIG_ENV_IS_IN_FLASH=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_STM32_FLASH=y
+CONFIG_SYS_MAX_FLASH_SECT=12
 CONFIG_SYS_MAX_FLASH_BANKS=2
index e2c41b0844e8140cb12fdda9c0262d14ec8e6c5f..98c0507b535f7f13f9922162dd4591ef3eca582e 100644 (file)
@@ -31,4 +31,5 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ARM_PL180_MMCI=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_STM32_FLASH=y
+CONFIG_SYS_MAX_FLASH_SECT=12
 CONFIG_SYS_MAX_FLASH_BANKS=2
index c7dbc69fa889479f66207a14875e0481358a2b63..c27f760af4f555713fb63e2c2b24564435f0d5c8 100644 (file)
@@ -33,6 +33,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_STM32_FLASH=y
+CONFIG_SYS_MAX_FLASH_SECT=12
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
index e3f80ab8e2069ea605e936f5c28408e4e787cb6a..61d6daa75762de1f8d7e3143e009d4afdb0d3643 100644 (file)
@@ -42,6 +42,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_STM32_FLASH=y
+CONFIG_SYS_MAX_FLASH_SECT=8
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
index 927d28dd9733b99d5507a17ff0a6293107373626..0368ece6390f8d2f6fdeac03e88ab7ac424fb962 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_STM32_FLASH=y
+CONFIG_SYS_MAX_FLASH_SECT=8
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
index b7e9ee92a7e1ba44643188a1b18f87816c0e7619..c177bd8c733ff6813c34a76e6b861d1629ed5096 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_STM32_FLASH=y
+CONFIG_SYS_MAX_FLASH_SECT=8
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
index bae28b4ec132efb4a234725e31f5065ded96e1dd..7515574dfbc1fcfdcb8f4be3a2b58cf5f2c90962 100644 (file)
@@ -62,6 +62,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_STM32_FLASH=y
+CONFIG_SYS_MAX_FLASH_SECT=8
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_STMICRO=y
index 4bbee30b064220070f4e2993986bf6c159504d8b..dad6c2d9318d1a7af28dc52dcc2753eb0b5829fa 100644 (file)
@@ -71,6 +71,7 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_VITESSE=y
+CONFIG_SYS_MEMAC_LITTLE_ENDIAN=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
index 2cb17f5040bf536f528fc51d9c8518da22a272c4..ab13ac82ee77398034262c6133b655a63c5a707f 100644 (file)
@@ -53,7 +53,9 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_LIBAVB=y
 CONFIG_OF_LIBFDT_OVERLAY=y
index 792bcf1eb5d44f33f687ee94e16068968bf77812..cf3ffc77318257d66354f09bbfdd8fa8a45d7863 100644 (file)
@@ -30,8 +30,10 @@ CONFIG_CMD_UBI=y
 CONFIG_MTD=y
 CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=259
 CONFIG_DM_ETH=y
 CONFIG_PCI=y
 CONFIG_USB=y
index 0ae8ae10a3106eca9fbfe9b467f5851d488e8ca4..39d96fe359909170e8d580b8a3805a99b4d79575 100644 (file)
@@ -27,6 +27,8 @@ CONFIG_CMD_UBI=y
 CONFIG_MTD=y
 CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_VIRTIO_MMIO=y
index f2084890edeca86d948bb952c0199f1370da4ddf..8817c4e46f5973955e62c361c5b62352c4486d28 100644 (file)
@@ -45,8 +45,10 @@ CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=259
 CONFIG_SYS_MAX_FLASH_BANKS=2
 CONFIG_DM_ETH=y
 CONFIG_SMC911X=y
index b3834b4952ff986a6b0896dcf98bc3159f824aae..7beb5915fcecfe58c3deb6d79854aa79a96d5963 100644 (file)
@@ -111,6 +111,7 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_ZYNQ=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
index eab40fc0d133e9b93529041cd1e6886a5f144346..966b0eb6538c3661d44106ce186ee2d98b6e289b 100644 (file)
@@ -39,8 +39,10 @@ CONFIG_DM=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
+CONFIG_SYS_FLASH_EMPTY_INFO=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_SECT=1027
 CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
 CONFIG_ETHOC=y
index ecdbf8182e68c79e4c7d4e223670610499d1d40f..59cd19ef2d40b5afffaa98aef70ac2326310a87d 100644 (file)
@@ -78,5 +78,6 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_ARM_DCC=y
 # CONFIG_GZIP is not set
index 698e288c4487844b361fb72c5c70227fbaafb69c..87a51e5b7db9b50c188774a0b5c3e61d87e1ea54 100644 (file)
@@ -114,8 +114,6 @@ apply to one or more cpu for the ColdFire family:
 
 CONFIG_SYS_MBAR:
   defines the base address of the MCF5272 configuration registers
-CONFIG_SYS_ENET_BD_BASE:
-  defines the base address of the FEC buffer descriptors
 CONFIG_SYS_SCR:
   defines the contents of the System Configuration Register
 CONFIG_SYS_SPR:
index d93ed8d2feb6629e40cec6d2d8b7d4c239897ffd..22400a9b8bab5d9db05a5a99d4b13349dc0b8c5e 100644 (file)
@@ -182,6 +182,13 @@ config SYS_DDR_RAW_TIMING
          timing parameters are extracted from datasheet and hard-coded into
          header files or board specific files.
 
+config SYS_FSL_DDR_INTLV_256B
+       bool "Enforce 256-byte interleave"
+       help
+         DDR controller interleaving on 256-byte. This is a special
+         interleaving mode, handled by Dickens for Freescale layerscape SoCs
+         with ARM core.
+
 endif
 
 menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
index 25a9c8185037d6888ec20a98a34f88cd75188d44..2dae159370644c7b8f04468e0f6e460844029c9e 100644 (file)
@@ -4,7 +4,6 @@
  */
 
 #include <common.h>
-#include <flash.h>
 #include <malloc.h>
 #include <errno.h>
 #include <div64.h>
index 98eccc34556b3ad510b0a15c1c798ea5d73af663..bdfdf262c8a33b097fade98f9801f1cf72834dd2 100644 (file)
@@ -10,7 +10,6 @@
 #include <fastboot-internal.h>
 #include <fb_mmc.h>
 #include <fb_nand.h>
-#include <flash.h>
 #include <part.h>
 #include <stdlib.h>
 
index c62e414306c3cd981f03e94b6380b63fe0d41fdb..033c510bc0961ded09c37fcd93e013566e1d8256 100644 (file)
@@ -10,7 +10,6 @@
 #include <fastboot.h>
 #include <fastboot-internal.h>
 #include <fb_mmc.h>
-#include <flash.h>
 #include <image-sparse.h>
 #include <image.h>
 #include <log.h>
index eb8a36f29222cc2afbcc8c7124ea904f8d8f5dff..6d3a900c772884e00af166ebcfedb8d829772a99 100644 (file)
@@ -7,7 +7,6 @@
 #include <config.h>
 #include <common.h>
 #include <blk.h>
-#include <flash.h>
 
 #include <fastboot.h>
 #include <image-sparse.h>
index 82a8bca27000a0222a64db070701f294386b7747..7e4c3577b366491b4dd95c452cf39c40bbd564d6 100644 (file)
@@ -70,7 +70,7 @@ config GPIO_HOG
 
 config SPL_GPIO_HOG
        bool "Enable GPIO hog support in SPL"
-       depends on SPL_GPIO_SUPPORT
+       depends on SPL_GPIO
        help
          Enable gpio hog support in SPL
          The GPIO chip may contain GPIO hog definitions. GPIO hogging
index e131eccd281f0bc0f0a45ee471eaba9e06e8f005..621d1752176a9175c75a78ddba18680cbc305965 100644 (file)
@@ -18,7 +18,6 @@
 #include <common.h>
 #include <command.h>
 #include <dm.h>
-#include <flash.h>
 #include <i2c.h>
 #include <cros_ec.h>
 #include <fdtdec.h>
index 3d1f6e43fd526a0e56343470f7105fdd433b33d8..fcdb450f77aa9c8ed8031083f1fcd4f18fea13cf 100644 (file)
@@ -106,6 +106,10 @@ config SYS_FLASH_USE_BUFFER_WRITE
        help
          Use buffered writes to flash.
 
+config SYS_FLASH_EMPTY_INFO
+       bool "Enable displaying empty sectors in flash info"
+       depends on FLASH_CFI_DRIVER
+
 config FLASH_CFI_MTD
        bool "Enable CFI MTD driver"
        depends on FLASH_CFI_DRIVER
@@ -128,6 +132,21 @@ config SYS_FLASH_CFI
          Define if the flash driver uses extra elements in the
          common flash structure for storing flash geometry.
 
+config SYS_FLASH_QUIET_TEST
+       bool "Disable printing a warning about not recognizing some flash banks"
+       depends on FLASH_CFI_DRIVER
+       help
+         If this option is enabled, the common CFI flash doesn't print it's
+         warning upon not recognized FLASH banks. This is useful, if some of
+         the configured banks are only optionally available.
+
+config SYS_FLASH_CHECKSUM
+       bool "Compute and print flash CRC if 'flashchecksum' is set in the environment"
+       depends on MTD_NOR_FLASH
+       help
+         If the variable flashchecksum is set in the environment, perform a CRC
+         of the flash and print the value to console.
+
 config ALTERA_QSPI
        bool "Altera Generic Quad SPI Controller"
        depends on DM_MTD
@@ -138,14 +157,6 @@ config ALTERA_QSPI
          NOR flash to parallel flash interface. Please find details on the
          "Embedded Peripherals IP User Guide" of Altera.
 
-config FLASH_PIC32
-       bool "Microchip PIC32 Flash driver"
-       depends on MACH_PIC32 && DM_MTD
-       select USE_SYS_MAX_FLASH_BANKS
-       help
-         This enables access to Microchip PIC32 internal non-CFI flash
-         chips through PIC32 Non-Volatile-Memory Controller.
-
 config RENESAS_RPC_HF
        bool "Renesas RCar Gen3 RPC HyperFlash driver"
        depends on RCAR_GEN3 && DM_MTD
@@ -168,6 +179,11 @@ config STM32_FLASH
         This is the driver of embedded flash for some STMicroelectronics
         STM32 MCU.
 
+config SYS_MAX_FLASH_SECT
+       int "Maximumm number of sectors on a flash chip"
+       depends on MTD_NOR_FLASH || FLASH_CFI_DRIVER
+       default 512
+
 config SAMSUNG_ONENAND
        bool "Samsung OneNAND driver support"
 
index ce0451108eb52562e8c727a62699ef882debd296..3a78590aaaa1d03d66cc598b706e606516a49ef4 100644 (file)
@@ -11,7 +11,6 @@ mtd-$(CONFIG_ALTERA_QSPI) += altera_qspi.o
 mtd-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
 mtd-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
 mtd-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
-mtd-$(CONFIG_FLASH_PIC32) += pic32_flash.o
 mtd-$(CONFIG_STM32_FLASH) += stm32_flash.o
 mtd-$(CONFIG_RENESAS_RPC_HF) += renesas_rpc_hf.o
 mtd-$(CONFIG_HBMC_AM654) += hbmc-am654.o
diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c
deleted file mode 100644 (file)
index ea0dbe9..0000000
+++ /dev/null
@@ -1,448 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015
- * Cristian Birsan <cristian.birsan@microchip.com>
- * Purna Chandra Mandal <purna.mandal@microchip.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <dm.h>
-#include <fdt_support.h>
-#include <flash.h>
-#include <init.h>
-#include <irq_func.h>
-#include <asm/global_data.h>
-#include <linux/bitops.h>
-#include <mach/pic32.h>
-#include <wait_bit.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* NVM Controller registers */
-struct pic32_reg_nvm {
-       struct pic32_reg_atomic ctrl;
-       struct pic32_reg_atomic key;
-       struct pic32_reg_atomic addr;
-       struct pic32_reg_atomic data;
-};
-
-/* NVM operations */
-#define NVMOP_NOP              0
-#define NVMOP_WORD_WRITE       1
-#define NVMOP_PAGE_ERASE       4
-
-/* NVM control bits */
-#define NVM_WR                 BIT(15)
-#define NVM_WREN               BIT(14)
-#define NVM_WRERR              BIT(13)
-#define NVM_LVDERR             BIT(12)
-
-/* NVM programming unlock register */
-#define LOCK_KEY               0x0
-#define UNLOCK_KEY1            0xaa996655
-#define UNLOCK_KEY2            0x556699aa
-
-/*
- * PIC32 flash banks consist of number of pages, each page
- * into number of rows and rows into number of words.
- * Here we will maintain page information instead of sector.
- */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-static struct pic32_reg_nvm *nvm_regs_p;
-
-static inline void flash_initiate_operation(u32 nvmop)
-{
-       /* set operation */
-       writel(nvmop, &nvm_regs_p->ctrl.raw);
-
-       /* enable flash write */
-       writel(NVM_WREN, &nvm_regs_p->ctrl.set);
-
-       /* unlock sequence */
-       writel(LOCK_KEY, &nvm_regs_p->key.raw);
-       writel(UNLOCK_KEY1, &nvm_regs_p->key.raw);
-       writel(UNLOCK_KEY2, &nvm_regs_p->key.raw);
-
-       /* initiate operation */
-       writel(NVM_WR, &nvm_regs_p->ctrl.set);
-}
-
-static int flash_wait_till_busy(const char *func, ulong timeout)
-{
-       int ret = wait_for_bit_le32(&nvm_regs_p->ctrl.raw,
-                                   NVM_WR, false, timeout, false);
-
-       return ret ? ERR_TIMEOUT : ERR_OK;
-}
-
-static inline int flash_complete_operation(void)
-{
-       u32 tmp;
-
-       tmp = readl(&nvm_regs_p->ctrl.raw);
-       if (tmp & NVM_WRERR) {
-               printf("Error in Block Erase - Lock Bit may be set!\n");
-               flash_initiate_operation(NVMOP_NOP);
-               return ERR_PROTECTED;
-       }
-
-       if (tmp & NVM_LVDERR) {
-               printf("Error in Block Erase - low-vol detected!\n");
-               flash_initiate_operation(NVMOP_NOP);
-               return ERR_NOT_ERASED;
-       }
-
-       /* disable flash write or erase operation */
-       writel(NVM_WREN, &nvm_regs_p->ctrl.clr);
-
-       return ERR_OK;
-}
-
-/*
- * Erase flash sectors, returns:
- * ERR_OK - OK
- * ERR_INVAL - invalid sector arguments
- * ERR_TIMEOUT - write timeout
- * ERR_NOT_ERASED - Flash not erased
- * ERR_UNKNOWN_FLASH_VENDOR - incorrect flash
- */
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
-       ulong sect_start, sect_end, flags;
-       int prot, sect;
-       int rc;
-
-       if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MCHP) {
-               printf("Can't erase unknown flash type %08lx - aborted\n",
-                      info->flash_id);
-               return ERR_UNKNOWN_FLASH_VENDOR;
-       }
-
-       if ((s_first < 0) || (s_first > s_last)) {
-               printf("- no sectors to erase\n");
-               return ERR_INVAL;
-       }
-
-       prot = 0;
-       for (sect = s_first; sect <= s_last; ++sect) {
-               if (info->protect[sect])
-                       prot++;
-       }
-
-       if (prot)
-               printf("- Warning: %d protected sectors will not be erased!\n",
-                      prot);
-       else
-               printf("\n");
-
-       /* erase on unprotected sectors */
-       for (sect = s_first; sect <= s_last; sect++) {
-               if (info->protect[sect])
-                       continue;
-
-               /* disable interrupts */
-               flags = disable_interrupts();
-
-               /* write destination page address (physical) */
-               sect_start = CPHYSADDR(info->start[sect]);
-               writel(sect_start, &nvm_regs_p->addr.raw);
-
-               /* page erase */
-               flash_initiate_operation(NVMOP_PAGE_ERASE);
-
-               /* wait */
-               rc = flash_wait_till_busy(__func__,
-                                         CONFIG_SYS_FLASH_ERASE_TOUT);
-
-               /* re-enable interrupts if necessary */
-               if (flags)
-                       enable_interrupts();
-
-               if (rc != ERR_OK)
-                       return rc;
-
-               rc = flash_complete_operation();
-               if (rc != ERR_OK)
-                       return rc;
-
-               /*
-                * flash content is updated but cache might contain stale
-                * data, so invalidate dcache.
-                */
-               sect_end = info->start[sect] + info->size / info->sector_count;
-               invalidate_dcache_range(info->start[sect], sect_end);
-       }
-
-       printf(" done\n");
-       return ERR_OK;
-}
-
-int page_erase(flash_info_t *info, int sect)
-{
-       return 0;
-}
-
-/* Write a word to flash */
-static int write_word(flash_info_t *info, ulong dest, ulong word)
-{
-       ulong flags;
-       int rc;
-
-       /* read flash to check if it is sufficiently erased */
-       if ((readl((void __iomem *)dest) & word) != word) {
-               printf("Error, Flash not erased!\n");
-               return ERR_NOT_ERASED;
-       }
-
-       /* disable interrupts */
-       flags = disable_interrupts();
-
-       /* update destination page address (physical) */
-       writel(CPHYSADDR(dest), &nvm_regs_p->addr.raw);
-       writel(word, &nvm_regs_p->data.raw);
-
-       /* word write */
-       flash_initiate_operation(NVMOP_WORD_WRITE);
-
-       /* wait for operation to complete */
-       rc = flash_wait_till_busy(__func__, CONFIG_SYS_FLASH_WRITE_TOUT);
-
-       /* re-enable interrupts if necessary */
-       if (flags)
-               enable_interrupts();
-
-       if (rc != ERR_OK)
-               return rc;
-
-       return flash_complete_operation();
-}
-
-/*
- * Copy memory to flash, returns:
- * ERR_OK - OK
- * ERR_TIMEOUT - write timeout
- * ERR_NOT_ERASED - Flash not erased
- */
-int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-       ulong dst, tmp_le, len = cnt;
-       int i, l, rc;
-       uchar *cp;
-
-       /* get lower word aligned address */
-       dst = (addr & ~3);
-
-       /* handle unaligned start bytes */
-       l = addr - dst;
-       if (l != 0) {
-               tmp_le = 0;
-               for (i = 0, cp = (uchar *)dst; i < l; ++i, ++cp)
-                       tmp_le |= *cp << (i * 8);
-
-               for (; (i < 4) && (cnt > 0); ++i, ++src, --cnt, ++cp)
-                       tmp_le |= *src << (i * 8);
-
-               for (; (cnt == 0) && (i < 4); ++i, ++cp)
-                       tmp_le |= *cp << (i * 8);
-
-               rc = write_word(info, dst, tmp_le);
-               if (rc)
-                       goto out;
-
-               dst += 4;
-       }
-
-       /* handle word aligned part */
-       while (cnt >= 4) {
-               tmp_le = src[0] | src[1] << 8 | src[2] << 16 | src[3] << 24;
-               rc = write_word(info, dst, tmp_le);
-               if (rc)
-                       goto out;
-               src += 4;
-               dst += 4;
-               cnt -= 4;
-       }
-
-       if (cnt == 0) {
-               rc = ERR_OK;
-               goto out;
-       }
-
-       /* handle unaligned tail bytes */
-       tmp_le = 0;
-       for (i = 0, cp = (uchar *)dst; (i < 4) && (cnt > 0); ++i, ++cp) {
-               tmp_le |= *src++ << (i * 8);
-               --cnt;
-       }
-
-       for (; i < 4; ++i, ++cp)
-               tmp_le |= *cp << (i * 8);
-
-       rc = write_word(info, dst, tmp_le);
-out:
-       /*
-        * flash content updated by nvm controller but CPU cache might
-        * have stale data, so invalidate dcache.
-        */
-       invalidate_dcache_range(addr, addr + len);
-
-       printf(" done\n");
-       return rc;
-}
-
-void flash_print_info(flash_info_t *info)
-{
-       int i;
-
-       if (info->flash_id == FLASH_UNKNOWN) {
-               printf("missing or unknown FLASH type\n");
-               return;
-       }
-
-       switch (info->flash_id & FLASH_VENDMASK) {
-       case FLASH_MAN_MCHP:
-               printf("Microchip Technology ");
-               break;
-       default:
-               printf("Unknown Vendor ");
-               break;
-       }
-
-       switch (info->flash_id & FLASH_TYPEMASK) {
-       case FLASH_MCHP100T:
-               printf("Internal (8 Mbit, 64 x 16k)\n");
-               break;
-       default:
-               printf("Unknown Chip Type\n");
-               break;
-       }
-
-       printf("  Size: %ld MB in %d Sectors\n",
-              info->size >> 20, info->sector_count);
-
-       printf("  Sector Start Addresses:");
-       for (i = 0; i < info->sector_count; ++i) {
-               if ((i % 5) == 0)
-                       printf("\n   ");
-
-               printf(" %08lX%s", info->start[i],
-                      info->protect[i] ? " (RO)" : "     ");
-       }
-       printf("\n");
-}
-
-unsigned long flash_init(void)
-{
-       unsigned long size = 0;
-       struct udevice *dev;
-       int bank;
-
-       /* probe every MTD device */
-       for (uclass_first_device(UCLASS_MTD, &dev); dev;
-            uclass_next_device(&dev)) {
-               /* nop */
-       }
-
-       /* calc total flash size */
-       for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank)
-               size += flash_info[bank].size;
-
-       return size;
-}
-
-static void pic32_flash_bank_init(flash_info_t *info,
-                                 ulong base, ulong size)
-{
-       ulong sect_size;
-       int sect;
-
-       /* device & manufacturer code */
-       info->flash_id = FLASH_MAN_MCHP | FLASH_MCHP100T;
-       info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-       info->size = size;
-
-       /* update sector (i.e page) info */
-       sect_size = info->size / info->sector_count;
-       for (sect = 0; sect < info->sector_count; sect++) {
-               info->start[sect] = base;
-               /* protect each sector by default */
-               info->protect[sect] = 1;
-               base += sect_size;
-       }
-}
-
-static int pic32_flash_probe(struct udevice *dev)
-{
-       void *blob = (void *)gd->fdt_blob;
-       int node = dev_of_offset(dev);
-       const char *list, *end;
-       const fdt32_t *cell;
-       unsigned long addr, size;
-       int parent, addrc, sizec;
-       flash_info_t *info;
-       int len, idx;
-
-       /*
-        * decode regs. there are multiple reg tuples, and they need to
-        * match with reg-names.
-        */
-       parent = fdt_parent_offset(blob, node);
-       fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
-       list = fdt_getprop(blob, node, "reg-names", &len);
-       if (!list)
-               return -ENOENT;
-
-       end = list + len;
-       cell = fdt_getprop(blob, node, "reg", &len);
-       if (!cell)
-               return -ENOENT;
-
-       for (idx = 0, info = &flash_info[0]; list < end;) {
-               addr = fdt_translate_address((void *)blob, node, cell + idx);
-               size = fdt_addr_to_cpu(cell[idx + addrc]);
-               len = strlen(list);
-               if (!strncmp(list, "nvm", len)) {
-                       /* NVM controller */
-                       nvm_regs_p = ioremap(addr, size);
-               } else if (!strncmp(list, "bank", 4)) {
-                       /* Flash bank: use kseg0 cached address */
-                       pic32_flash_bank_init(info, CKSEG0ADDR(addr), size);
-                       info++;
-               }
-               idx += addrc + sizec;
-               list += len + 1;
-       }
-
-       /* disable flash write/erase operations */
-       writel(NVM_WREN, &nvm_regs_p->ctrl.clr);
-
-#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
-       /* monitor protection ON by default */
-       flash_protect(FLAG_PROTECT_SET,
-                     CONFIG_SYS_MONITOR_BASE,
-                     CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
-                     &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-       /* ENV protection ON by default */
-       flash_protect(FLAG_PROTECT_SET,
-                     CONFIG_ENV_ADDR,
-                     CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-                     &flash_info[0]);
-#endif
-       return 0;
-}
-
-static const struct udevice_id pic32_flash_ids[] = {
-       { .compatible = "microchip,pic32mzda-flash" },
-       {}
-};
-
-U_BOOT_DRIVER(pic32_flash) = {
-       .name   = "pic32_flash",
-       .id     = UCLASS_MTD,
-       .of_match = pic32_flash_ids,
-       .probe  = pic32_flash_probe,
-};
index 85867817c7861961e517c67cbaa6fbf892c4828d..e19e34244d1fc23ea55c870b6720921f8c52e6ac 100644 (file)
@@ -10,7 +10,6 @@
 #include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
-#include <flash.h>
 #include <log.h>
 #include <spi.h>
 #include <spi_flash.h>
index 0aed28a52b78acff7ad31f430285759fd0305bb3..071b25ac67f2d4e14f8ea3cf846716cbe926df85 100644 (file)
@@ -4,7 +4,6 @@
  */
 
 #include <common.h>
-#include <flash.h>
 #include <malloc.h>
 #include <linux/errno.h>
 #include <linux/mtd/mtd.h>
index 8a226a7af553c4f63f1a26367cb8ad12dfa702d4..26a356baf8418b7a5e08f9ca49688f89c3d11389 100644 (file)
@@ -10,7 +10,6 @@
  */
 
 #include <common.h>
-#include <flash.h>
 #include <log.h>
 #include <watchdog.h>
 #include <dm.h>
index 5d90a924aab20bfd7c5db95955adf2856ac826c2..93e7dbe97661f139d765f6f612fd70f8a5e8678e 100644 (file)
@@ -357,6 +357,9 @@ config FEC_MXC
 config FMAN_ENET
        bool "Freescale FMan ethernet support"
        depends on ARM || PPC
+       select SYS_FMAN_V3 if ARCH_B4420 || ARCH_B4860 || ARCH_LS1043A || \
+               ARCH_LS1046A || ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || \
+               ARCH_T2080 || ARCH_T4240
        help
          This driver support the Freescale FMan Ethernet controller
 
@@ -370,6 +373,12 @@ config SYS_QE_FMAN_FW_LENGTH
        depends on FMAN_ENET || QE || U_QE
        default 0x10000
 
+config SYS_FMAN_V3
+       bool
+       select FSL_MEMAC
+       help
+         SoC has FMan v3 with mEMAC
+
 config FTMAC100
        bool "Ftmac100 Ethernet Support"
        help
index ae3841217663f20a2141ebf56805b42daaf4f1bd..5a7d3037af405d4960503cec11f04f7dcf358bff 100644 (file)
@@ -11,7 +11,6 @@ obj-y += tgec.o
 obj-y += tgec_phy.o
 
 # Soc have FMAN v3 with mEMAC
-obj-$(CONFIG_SYS_FMAN_V3) += memac_phy.o
 obj-$(CONFIG_SYS_FMAN_V3) += memac.o
 
 # SoC specific SERDES support
index 33a4b6f30db038c71e2db473c475f5445d221dc7..52ce08b3b3841944d809d41f85bc908404f34caf 100644 (file)
@@ -345,6 +345,13 @@ config PHY_NCSI
 
 endif #PHYLIB
 
+config FSL_MEMAC
+       bool "NXP mEMAC PHY support"
+
+config SYS_MEMAC_LITTLE_ENDIAN
+       bool "mEMAC is access in little endian mode"
+       depends on FSL_MEMAC || FSL_LS_MDIO
+
 config PHY_RESET_DELAY
        int "Extra delay after reset before MII register access"
        default 0
index 8fd5a2e205192c35300f3695a6ff0b4acd3c47d0..6e79868d0efc1f18331cbed5df44833df812837f 100644 (file)
@@ -12,6 +12,7 @@ config DM_PWM
 config PWM_ASPEED
        bool "Enable support for the Aspeed PWM"
        depends on DM_PWM
+       select SYSCON
        help
          This PWM is found on Ast2600 SoCs. It supports a programmable period
          and duty cycle. It provides 16 channels which can be independently
index 5e90a6584640cf981e33e097d894d8495337c911..532216fece3a71d554ab5a1df9fa547932c7c119 100644 (file)
@@ -23,7 +23,9 @@
 #include <xen/events.h>
 #include <xen/hvm.h>
 
+#if CONFIG_IS_ENABLED(XEN_SERIAL)
 extern u32 console_evtchn;
+#endif /* CONFIG_IS_ENABLED(XEN_SERIAL) */
 
 #define NR_EVS 1024
 
@@ -51,8 +53,11 @@ void unbind_all_ports(void)
        struct vcpu_info *vcpu_info = &s->vcpu_info[cpu];
 
        for (i = 0; i < NR_EVS; i++) {
+#if CONFIG_IS_ENABLED(XEN_SERIAL)
                if (i == console_evtchn)
                        continue;
+#endif /* CONFIG_IS_ENABLED(XEN_SERIAL) */
+
                if (test_and_clear_bit(i, bound_ports)) {
                        printf("port %d still bound!\n", i);
                        unbind_evtchn(i);
index 9c8abfa016c401ceb37804920f9d7f175aa3ca17..1e75f8c004ee79d0bbac218c0a6284f0a6b89c85 100644 (file)
@@ -13,7 +13,6 @@
 #include <command.h>
 #include <env.h>
 #include <env_internal.h>
-#include <flash.h>
 #include <log.h>
 #include <asm/global_data.h>
 #include <linux/stddef.h>
@@ -26,6 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SPL_BUILD
 # if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_FLASH)
+#  include <flash.h>
 #  define CMD_SAVEENV
 # elif defined(CONFIG_ENV_ADDR_REDUND)
 #  error CONFIG_ENV_ADDR_REDUND must have CONFIG_CMD_SAVEENV & CONFIG_CMD_FLASH
index 4b768542c14c0a7787c1528702a3838bd9bd43ec..a425ecc11c8e6c27606e7f684b6dd641f4abb934 100644 (file)
--- a/env/sf.c
+++ b/env/sf.c
@@ -12,7 +12,6 @@
 #include <dm.h>
 #include <env.h>
 #include <env_internal.h>
-#include <flash.h>
 #include <malloc.h>
 #include <spi.h>
 #include <spi_flash.h>
index 7ef48bbc064c46a87fbb6156843de518e53e61ce..6c017cebc50ff1338c1acb80264618fbd00872a2 100644 (file)
@@ -25,7 +25,6 @@
  */
 
 #include <common.h>
-#include <flash.h>
 #include <malloc.h>
 #include <asm/byteorder.h>
 #include <linux/stat.h>
@@ -43,7 +42,7 @@ struct cramfs_super super;
 /* CPU address space offset calculation macro, struct part_info offset is
  * device address space offset, so we need to shift it by a device start address. */
 #if defined(CONFIG_MTD_NOR_FLASH)
-extern flash_info_t flash_info[];
+#include <flash.h>
 #define PART_OFFSET(x) ((ulong)x->offset + \
                         flash_info[x->dev->id->num].start[0])
 #else
index 1818e8121569f384d97e83e3b959d84ddfa23c97..ef7b302725cad76fde3c81d2967eadfdc32cea78 100644 (file)
 
 #include <common.h>
 #include <config.h>
-#include <flash.h>
 #include <malloc.h>
 #include <div64.h>
 #include <linux/compiler.h>
@@ -381,6 +380,8 @@ static void put_fl_mem_onenand(void *buf)
 
 
 #if defined(CONFIG_CMD_FLASH)
+#include <flash.h>
+
 /*
  * Support for jffs2 on top of NOR-flash
  *
@@ -392,7 +393,6 @@ static inline void *get_fl_mem_nor(u32 off, u32 size, void *ext_buf)
        u32 addr = off;
        struct mtdids *id = current_part->dev->id;
 
-       extern flash_info_t flash_info[];
        flash_info_t *flash = &flash_info[id->num];
 
        addr += flash->start[0];
index 9b4f5fcf1b8e0269f0e2f27d43664da944fa2a11..35560ab68351fb0268822e6e8b338c072140bb3f 100644 (file)
@@ -20,7 +20,6 @@
 /*
  * Flash
  */
-#define CONFIG_SYS_MAX_FLASH_SECT      1024
 
 /*
  * BOOTP options
index 2d52dc6f66080d78bd8ddfdda01b7bfe407564ab..69fa1c1b76818b27e424c3e60d945a9843579854 100644 (file)
@@ -19,7 +19,6 @@
 /*
  * CFI Flash
  */
-#define CONFIG_SYS_MAX_FLASH_SECT      512
 
 /*
  * MEMORY ORGANIZATION
index c773164c869b3ae67a02d296e4e7cbdf9701063d..6c6469b0d4b8633db964ec774cee6e8f6d685317 100644 (file)
@@ -82,7 +82,6 @@
 /* FLASH organization */
 #ifdef CONFIG_SYS_FLASH_CFI
 #      define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
-#      define CONFIG_SYS_MAX_FLASH_SECT        254     /* max number of sectors on one chip */
 #endif
 
 #define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_CS0_BASE
index 79448cf440485ece061b00f21f415ba73cd1df0e..54116413230b2b80f07f4c811ff83437fd212fda 100644 (file)
@@ -90,7 +90,6 @@
  */
 #ifdef CONFIG_SYS_FLASH_CFI
 #      define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
-#      define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 #endif
 
 #define CONFIG_SYS_FLASH_BASE          (CONFIG_SYS_CS0_BASE)
index 1889a235a2a153f0008eab9425d42d32c20df92e..42c62b4d684afec08d0b2ba7ca4345f5f4132a73 100644 (file)
@@ -77,8 +77,6 @@
 #ifdef CONFIG_SYS_FLASH_CFI
 
 #      define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
-#      define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
-#      define CONFIG_SYS_FLASH_CHECKSUM
 #      define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
 #endif
 
index cac9b24ead8e980052680ddf929abfd83961dac9..75278f4dab71143c33519d2d4611d00e648328d2 100644 (file)
@@ -93,8 +93,6 @@
 
 /* FLASH organization */
 #define CONFIG_SYS_FLASH_BASE          (CONFIG_SYS_CS0_BASE)
-#define CONFIG_SYS_MAX_FLASH_SECT      2048    /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    1000
 
 #define FLASH_SST6401B         0x200
 #define SST_ID_xF6401B         0x236D236D
  * 0x30 is block erase in SST
  */
 #      define CONFIG_SYS_FLASH_SIZE            0x800000
-#      define CONFIG_FLASH_CFI_LEGACY
 #else
 #      define CONFIG_SYS_SST_SECT              2048
 #      define CONFIG_SYS_SST_SECTSZ            0x1000
-#      define CONFIG_SYS_FLASH_WRITE_TOUT      500
 #endif
 
 /* Cache Configuration */
 #define CONFIG_SYS_CACHE_ICACR         (CF_CACR_CENB | CF_CACR_CEIB | \
                                         CF_CACR_DBWE)
 
-/* Port configuration */
-#define CONFIG_SYS_FECI2C              0xF0
-
 #define CONFIG_SYS_CS0_BASE            0xFF800000
 #define CONFIG_SYS_CS0_MASK            0x007F0021
 #define CONFIG_SYS_CS0_CTRL            0x00001D80
index 2fa1e4356e3ec76af94eecd4ac0a64a3133b879f..356ad3e9da1e6b064557fb8c6663036b8e3ab55f 100644 (file)
@@ -91,7 +91,6 @@
  */
 #ifdef CONFIG_SYS_FLASH_CFI
 #      define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
-#      define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 #endif
 
 /*-----------------------------------------------------------------------
index 292578fc15b9653a7a2b7dac2dde5ca375cf543b..35ff267371c23afaf0fc8869181cf1e6a7da3bb3 100644 (file)
@@ -91,8 +91,6 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CONFIG_SYS_MAX_FLASH_SECT      11      /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    1000
 
 #define CONFIG_SYS_FLASH_SIZE          0x200000
 
 #define CONFIG_SYS_CS1_CTRL            0x00001900
 #define CONFIG_SYS_CS1_MASK            0x00070001
 
-/*-----------------------------------------------------------------------
- * Port configuration
- */
-#define CONFIG_SYS_FECI2C              0x0FA0
-
 #endif /* _M5275EVB_H */
index 9f06f41ce11b7b9cc64c790252f82e9bdae352d4..900b0b53434b33beea5a7f7d9fbd1778d52f4c9c 100644 (file)
@@ -95,8 +95,6 @@
 #ifdef CONFIG_SYS_FLASH_CFI
 
 #      define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
-#      define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
-#      define CONFIG_SYS_FLASH_CHECKSUM
 #      define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
 #endif
 
index 4d8f752777d08cf1e6e0f35c226be47c41c31edf..4f82389cedfa1b09f01747e046e7ba056ccfec4e 100644 (file)
@@ -99,7 +99,6 @@
 #ifdef CONFIG_SYS_FLASH_CFI
 #      define CONFIG_FLASH_SPANSION_S29WS_N    1
 #      define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
-#      define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 #endif
 
 #define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_CS0_BASE
index 87d3e8fb153b72109d583bdacb3a58d79b913cff..a6c953f1a46cf770f828c94951628ac6b160db47 100644 (file)
@@ -92,7 +92,6 @@
  */
 #ifdef CONFIG_SYS_FLASH_CFI
 #      define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
-#      define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 #endif
 
 #ifdef CONFIG_CMD_NAND
index d920587c37908f3641ed9506787250344894dd25..f519bef24744a337c16d99765ed616423447e95d 100644 (file)
@@ -94,7 +94,6 @@
  */
 #ifdef CONFIG_SYS_FLASH_CFI
 #      define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
-#      define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 #endif
 
 #      define CONFIG_SYS_MAX_NAND_DEVICE       1
index 41ab860850833710142aa3220ce94a8bd8c40858..9d0683829ecb149ccf2cd4589b391c76a152ae4f 100644 (file)
@@ -69,9 +69,6 @@
 
 /* FLASH organization */
 #define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MAX_FLASH_SECT      35
-#define CONFIG_SYS_FLASH_ERASE_TOUT    120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500
 
 /*
  * For booting Linux, the board info and command line data
index d56d60306abf7f9efc84498f603d9bf3d84d30d3..c2f4f2bee2c080a66e7de567f6e5ee7f0927592e 100644 (file)
@@ -69,7 +69,7 @@
 /*
  * Manually set up DDR parameters
  */
-#define CONFIG_SYS_DDR_SIZE            256             /* MB */
+#define CONFIG_SYS_SDRAM_SIZE          0x10000000 /* 256 MiB */
 #define CONFIG_SYS_DDR_CS0_BNDS                0x0000000f
 #define CONFIG_SYS_DDR_CS0_CONFIG      (CSCONFIG_EN \
                                        | CSCONFIG_ODT_WR_ONLY_CURRENT \
 #define CONFIG_SYS_FLASH_BASE          0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE          8 /* max FLASH size is 32M */
 
-#define CONFIG_SYS_FLASH_EMPTY_INFO            /* display empty sectors */
-
-
-#define CONFIG_SYS_MAX_FLASH_SECT      256 /* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
 /*
  * NAND Flash on the Local Bus
  */
index c3c68071f2f2f3197d02c7074ece3ce46b442743..0c710ef8865cec1c321172ef2cb9c2d09157964e 100644 (file)
 
 #define CONFIG_SYS_FLASH_BANKS_LIST \
        {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_MAX_FLASH_SECT      128             /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 #define CONFIG_HWCONFIG                        /* enable hwconfig */
 
index 12a78eac17c90e9596205f7fec105635a957b713..7f5eaf88aa4cbc16e06592b178bb8417030a9879 100644 (file)
@@ -114,43 +114,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-/* DDR3 Controller Settings */
-#define CONFIG_SYS_DDR_CS0_BNDS                0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG      0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2    0x00000000
-#define CONFIG_SYS_DDR_INIT_ADDR       0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR   0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL    0x00000000
-#define CONFIG_SYS_DDR_ZQ_CONTROL      0x89080600
-#define CONFIG_SYS_DDR_SR_CNTR         0x00000000
-#define CONFIG_SYS_DDR_RCW_1           0x00000000
-#define CONFIG_SYS_DDR_RCW_2           0x00000000
-#define CONFIG_SYS_DDR_CONTROL         0xc70c0008      /* Type = DDR3  */
-#define CONFIG_SYS_DDR_CONTROL_2       0x24401000
-#define CONFIG_SYS_DDR_TIMING_4                0x00000001
-#define CONFIG_SYS_DDR_TIMING_5                0x03402400
-
-#define CONFIG_SYS_DDR_TIMING_3_800    0x00030000
-#define CONFIG_SYS_DDR_TIMING_0_800    0x00110104
-#define CONFIG_SYS_DDR_TIMING_1_800    0x6f6b8644
-#define CONFIG_SYS_DDR_TIMING_2_800    0x0FA888CF
-#define CONFIG_SYS_DDR_CLK_CTRL_800    0x03000000
-#define CONFIG_SYS_DDR_MODE_1_800      0x00441420
-#define CONFIG_SYS_DDR_MODE_2_800      0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800    0x0C300100
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
-
-/* settings for DDR3 at 667MT/s */
-#define CONFIG_SYS_DDR_TIMING_3_667            0x00010000
-#define CONFIG_SYS_DDR_TIMING_0_667            0x00110004
-#define CONFIG_SYS_DDR_TIMING_1_667            0x5d59e544
-#define CONFIG_SYS_DDR_TIMING_2_667            0x0FA890CD
-#define CONFIG_SYS_DDR_CLK_CTRL_667            0x03000000
-#define CONFIG_SYS_DDR_MODE_1_667              0x00441210
-#define CONFIG_SYS_DDR_MODE_2_667              0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_667            0x0a280000
-#define CONFIG_SYS_DDR_WRLVL_CONTROL_667       0x8675F608
-
 #define CONFIG_SYS_CCSRBAR                     0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW            CONFIG_SYS_CCSRBAR
 
@@ -174,7 +137,6 @@ extern unsigned long get_sdram_size(void);
 /* NOR Flash on IFC */
 
 #define CONFIG_SYS_FLASH_BASE          0xee000000
-#define CONFIG_SYS_MAX_FLASH_SECT      256     /* 32M */
 
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS     (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
@@ -200,15 +162,9 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_NOR_FTIM3   0x0
 
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45      /* count down from 45/5: 9..1 */
 
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
 /* CFI for NOR Flash */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /* NAND Flash on IFC */
 #define CONFIG_SYS_NAND_BASE           0xff800000
index 2d552835b7766533e48acfcb82868bae414c77e8..de5f42b10117cce0e7852a0614c373772e756bd1 100644 (file)
 #define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_SYS_FLASH_BR_PRELIM \
-               (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
-               BR_PS_16 | BR_V)
-#define CONFIG_SYS_FLASH_OR_PRELIM \
-               ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
-                | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
-
 #define CONFIG_FSL_CPLD
 #define CPLD_BASE              0xffdf0000      /* CPLD registers */
 #ifdef CONFIG_PHYS_64BIT
 #define PIXIS_LBMAP_SHIFT      4
 #define PIXIS_LBMAP_ALTBANK    0x40
 
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024            /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000           /* Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500             /* Write Timeout (ms) */
-
 /* Nand Flash */
 #ifdef CONFIG_NAND_FSL_ELBC
 #define CONFIG_SYS_NAND_BASE           0xffa00000
                               | OR_FCM_EHTR)
 #endif /* CONFIG_NAND_FSL_ELBC */
 
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 
 #define CONFIG_HWCONFIG
index c90ffe048c6f3237c01c7f113488d8e66b86fca5..f5e07a929fc59384d430cfac31d5dc36086885cb 100644 (file)
                                FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3   0x0
 
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
 
 #ifdef CONFIG_TARGET_T1024RDB
index 56486cf5c9345ba8ab911137155fd57aef6ca661..7983a71953d47cffc088fba1c7f8c4e3acf6004a 100644 (file)
                                FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3   0x0
 
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
 
 /* CPLD on IFC */
index 710254a8fb47070face0a682305ad9bf86837ca2..3da9831a028eb17bc4ed9117435ae0e24f144c63 100644 (file)
                                FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3   0x0
 
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS \
                                        + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 
index 8ade2e3c8292755512120e7669a57b9904ed8363..813d8fae9c8cf20655be8e928874c7a0e267f0d0 100644 (file)
                                FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3   0x0
 
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS }
 
 /* CPLD on IFC */
index 653483cc99f0c0cc7bf2de822462959e2198a615..332f34e1ff226fcc52838ee928537aefff18503e 100644 (file)
                                FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3   0x0
 
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS \
                                        + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 
index 4b59759f818eb6e64fbec078693d24c60110cb18..bd7e2f1bf5033cd2b2f9998766455f86f9448cef 100644 (file)
  * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
  */
 #if defined(CONFIG_NOR)
-#define CONFIG_SYS_MAX_FLASH_SECT      128
 #define CONFIG_SYS_FLASH_BASE          (0x08000000)
 #define CONFIG_SYS_FLASH_SIZE          0x01000000
 #endif  /* NOR support */
index 93beed4ad7369d15a5659655e1949e75d2a4a8aa..2dc6bd2f2cdd6ce2bb8cd2809f521eb4747bc26e 100644 (file)
@@ -88,7 +88,6 @@
 /* FLASH and environment organization */
 
 /* **** PISMO SUPPORT *** */
-#define CONFIG_SYS_MAX_FLASH_SECT      520     /* max number of sectors */
                                                /* on one chip */
 #define CONFIG_SYS_MONITOR_LEN         (256 << 10)     /* Reserve 2 sectors */
 
@@ -96,6 +95,4 @@
 #define CONFIG_SYS_FLASH_BASE          NAND_BASE
 #endif
 
-#define CONFIG_SYS_ENV_SECT_SIZE       (128 << 10)     /* 128 KiB */
-
 #endif /* __CONFIG_H */
index 3c9267b14ec98a4aef39dbdd05399c632fe6ea44..3f3b399ed7d9b09086737b1312720ef1b02c28ef 100644 (file)
@@ -36,8 +36,6 @@
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
 #define CONFIG_SYS_SDRAM_SIZE          0x1000000
 #define CONFIG_SYS_FLASH_BASE          0xffc00000
-#define CONFIG_SYS_MAX_FLASH_SECT      1024
-#define CONFIG_SYS_FLASH_ERASE_TOUT    1000
 
 /* amcore design has flash data bytes wired swapped */
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
index 1c7494183a4d5c73ca34ef819065c78a257c73f1..da02a96889bc290ec6960c34c7227031eebb4caf 100644 (file)
 
 /* FLASH */
 #define CONFIG_SYS_FLASH_BASE          0x00000000
-#define CONFIG_SYS_MAX_FLASH_SECT      512
 #define CONFIG_SYS_FLASH_BANKS_LIST    { (CONFIG_SYS_FLASH_BASE) }
 
-#define CONFIG_SYS_FLASH_ERASE_TOUT    3000
-#define CONFIG_SYS_FLASH_WRITE_TOUT    3000
-#define CONFIG_SYS_FLASH_LOCK_TOUT     3000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT   3000
-
 /* ENV setting */
 
 /* SH Ether */
index da4d49741d2cbecb8344814339e608e5105e3bbf..adfadd7c6d7264f7bdcf5c4dbaf81cd01e616677 100644 (file)
@@ -62,9 +62,6 @@
 #define CONFIG_SYS_CPU_CLK             (CONFIG_SYS_CLK * 3)
 #define CONFIG_SYS_SDRAM_SIZE          32              /* SDRAM size in MB */
 
-#define CONFIG_SYS_CORE_SRAM_SIZE      0x8000
-#define CONFIG_SYS_CORE_SRAM           0x80000000
-
 /*
  * Define baudrate for UART1 (console output, tftp, ...)
  * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
                                                (CONFIG_SYS_SDRAM_SIZE << 20))
 
 /* FLASH organization */
-#define CONFIG_SYS_MAX_FLASH_SECT      259
-#define CONFIG_SYS_FLASH_ERASE_TOUT    1000
 
 #define CONFIG_SYS_FLASH_SIZE          0x2000000
-#define CONFIG_SYS_FLASH_CFI_NONBLOCK  1
 
 #define LDS_BOARD_TEXT \
        . = DEFINED(env_offset) ? env_offset : .; \
index 9497f055035dea942c5548b61c4526a53c8b8ad3..8c6d1cd1d9d4f000831c544b6d0dd49c88aea0f9 100644 (file)
@@ -40,7 +40,6 @@
 #ifdef CONFIG_SYS_USE_NORFLASH
 #define PHYS_FLASH_1                           0x10000000
 #define CONFIG_SYS_FLASH_BASE                  PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT              256
 
 #define CONFIG_SYS_MONITOR_SEC 1:0-3
 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
index daa5cdf5b26bbcbd566f96b9d85063a390936790..cf5125fdfa63f57a927fe61ed6f684582f364dda 100644 (file)
@@ -46,9 +46,6 @@
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 #define CONFIG_SYS_FLASH_BANKS_LIST    { PHYS_FLASH_1, }
 
-#define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* TO for Flash Erase (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* TO for Flash Write (ms) */
-
 /* max number of memory banks */
 /*
  * There are 4 banks supported for this Controller,
@@ -58,7 +55,6 @@
 
 /* max number of sectors on one chip */
 #define CONFIG_FLASH_SECTOR_SIZE       (0x10000*2)
-#define CONFIG_SYS_MAX_FLASH_SECT      512
 
 /* environments */
 
index 25b6e7005e7aebe4a68881424477220d597df398..959c521b6c91844ea165617a14b13ebf83ad6cde 100644 (file)
 #define CONFIG_FLASH_SHOW_PROGRESS     45
 #define CONFIG_SYS_FLASH_BASE          0x00000000
 #define CONFIG_SYS_FLASH_SIZE          0x04000000      /* 64 MB */
-#define CONFIG_SYS_MAX_FLASH_SECT      1024
 #define CONFIG_SYS_FLASH_BANKS_LIST    { (CONFIG_SYS_FLASH_BASE) }
 #define CONFIG_SYS_FLASH_BANKS_SIZES   { (CONFIG_SYS_FLASH_SIZE) }
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT    3000
-#define CONFIG_SYS_FLASH_WRITE_TOUT    3000
-#define CONFIG_SYS_FLASH_LOCK_TOUT     3000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT   3000
 #endif
 
 /* Board Clock */
index ddaa54051395fc96465faa8848513d942e8937ed..b8a962dfa2fbdd81bc3851752faf6c82f492c780 100644 (file)
@@ -21,6 +21,5 @@
 #endif
 
 #define CONFIG_SYS_FLASH_BASE                  0xbfc00000
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 #endif /* __CONFIG_BMIPS_BCM6338_H */
index f704fe26ca0dd18bea83f579b7a3fe38509da61e..b23ab6a13cc97de689f68927a2b0fcb746c81416 100644 (file)
@@ -21,6 +21,5 @@
 #endif
 
 #define CONFIG_SYS_FLASH_BASE                  0xbfc00000
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 #endif /* __CONFIG_BMIPS_BCM6348_H */
index 9aaa694cad916401213126932a7f5691ee8721fb..106af2d2772754c08caf4b5683605fc27a967a6b 100644 (file)
@@ -21,6 +21,5 @@
 #endif
 
 #define CONFIG_SYS_FLASH_BASE                  0xbe000000
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 #endif /* __CONFIG_BMIPS_BCM6358_H */
index 0319124a0eddb05f255298df9ca0ec528fcd2654..fb1d760a8f3a146ee5975abc53c7954d4000e990 100644 (file)
@@ -21,6 +21,5 @@
 #endif
 
 #define CONFIG_SYS_FLASH_BASE                  0xb8000000
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 #endif /* __CONFIG_BMIPS_BCM6368_H */
index 8b04492753a870887b84ae3afa1fc988ff6709e2..5d6da772059d0813bbe012e976600ac111eb79c2 100644 (file)
  * Console
  */
 
-/*
- * Flash
- */
-
-#define CONFIG_SYS_MAX_FLASH_SECT              1024
-
 /*
  * Environment
  */
index 789e6a4c9d597b240ddbce1c613191d49272dca2..6cb1a1060022171b9e9bd6f955b94668fe59a899 100644 (file)
@@ -143,8 +143,4 @@ NANDTGTS \
 #define CONFIG_NAND_OMAP_GPMC_WSCFG    1
 #endif /* CONFIG_MTD_RAW_NAND */
 
-#if defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_SYS_ENV_SECT_SIZE       CONFIG_ENV_SIZE
-#endif
-
 #endif /* ! __CONFIG_BRPPT1_H__ */
index 965eba58b311d49b9b477f41fa569cb24dac8d65..fdbcbf5d96e2a50577f6ef3355af0374b11759f6 100644 (file)
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       14
 
-#if defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_SYS_ENV_SECT_SIZE       CONFIG_SYS_NAND_BLOCK_SIZE
-#endif
-
-/* Network. */
-
 #endif /* ! __CONFIG_CHILIBOARD_H */
index 4baf7f7e24aed09884d06645e865d64ac9975f80..84b4271c36fa135cdfe20cde2a76e4f95de28da0 100644 (file)
@@ -79,8 +79,6 @@
 
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 
-#define CONFIG_SYS_ENV_SECT_SIZE       (128 << 10)     /* 128 KiB */
-
 /* GPIO pin + bank to pin ID mapping */
 #define GPIO_PIN(_bank, _pin)          ((_bank << 5) + _pin)
 
index dd7b6c08730cc838254f78f313da45ee15bb3e5c..ba0662f1f40e1abe472faae77c24b45ce1fe8d2d 100644 (file)
@@ -143,13 +143,6 @@ enter a valid image address in flash */
 #define CONFIG_SYS_SCR                 0x0003
 #define CONFIG_SYS_SPR                 0xffff
 
-/* ---
- * Ethernet settings
- * ---
- */
-
-#define CONFIG_SYS_ENET_BD_BASE        0x780000
-
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in internal SRAM)
  */
@@ -186,12 +179,6 @@ enter a valid image address in flash */
  */
 #define CONFIG_SYS_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_SECT      11      /* max number of sectors on one chip    */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    1000    /* flash timeout */
-
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
index 4eeca47c2534faac0971b7c144b865911a930d3d..a4fb2b53dc9fb2382ea22d9bda04d8752de6f49e 100644 (file)
 #define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_SYS_FLASH_BR_PRELIM \
-               (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
-                | BR_PS_16 | BR_V)
-#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
-                                       | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
-
 #define PIXIS_BASE             0xffdf0000      /* PIXIS registers */
 #ifdef CONFIG_PHYS_64BIT
 #define PIXIS_BASE_PHYS                0xfffdf0000ull
 #define PIXIS_LBMAP_SHIFT      4
 #define PIXIS_LBMAP_ALTBANK    0x40
 
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024            /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000           /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500             /* Flash Write Timeout (ms) */
-
 /* Nand Flash */
 #ifdef CONFIG_NAND_FSL_ELBC
 #define CONFIG_SYS_NAND_BASE           0xffa00000
                               | OR_FCM_EHTR)
 #endif /* CONFIG_NAND_FSL_ELBC */
 
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 
 #define CONFIG_HWCONFIG
index 3db97205dab8711ad4f0307139d3e2d708d38eec..58c902431d133d9f5c27cb6b707a816a80590b70 100644 (file)
 #endif
 
 #ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_SECT_SZ       (128 << 10) /* 128KB */
 #define CONFIG_SYS_FLASH_BASE          DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 #define PHYS_FLASH_SIZE                        (8 << 20) /* Flash size 8MB */
-#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
-              + 3)
 #endif
 
 /*
index 328e4958f86a2c991dce570d4c68a8fe3ea49937..7916ca8a6cd4c131cf7550cb50ef962ef482b603 100644 (file)
@@ -29,7 +29,6 @@
 /*
  * NOR Flash
  */
-#define CONFIG_SYS_MAX_FLASH_SECT      71
 #define CONFIG_SYS_FLASH_BASE          EMC_CS0_BASE
 #define CONFIG_SYS_FLASH_SIZE          SZ_4M
 
index 9247720f8b6d8660ed0977f7467ac7edf76641a0..6cf716e293d6c5b6df190e3157db77adfaf083f8 100644 (file)
@@ -89,7 +89,6 @@
 /* Parallel NOR Support */
 #if defined(CONFIG_NOR)
 /* NOR: device related configs */
-#define CONFIG_SYS_MAX_FLASH_SECT      512
 #define CONFIG_SYS_FLASH_SIZE          (64 * 1024 * 1024) /* 64 MB */
 #define CONFIG_SYS_FLASH_BASE          (0x08000000)
 /* Reduce SPL size by removing unlikey targets */
index a38e48634835b8093975f7da427de5ad0dd1f81a..8bfba78dc8e473122e397c5a26816e287d91769d 100644 (file)
@@ -15,7 +15,6 @@
 
 #define CONFIG_FLASH_SHOW_PROGRESS     45
 #define CONFIG_SYS_FLASH_BANKS_LIST    { 0x08000000 }
-#define CONFIG_SYS_MAX_FLASH_SECT      256
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 #endif /* __DRAAK_H */
index 6e444c478922c9261a2adcdc6629da88ded6d3cb..249da66237b5d8d4ea0dd8792b317846857f64a2 100644 (file)
@@ -94,9 +94,6 @@
 #define        CONFIG_SYS_INT_FLASH_BASE       0xF0000000
 #define CONFIG_SYS_INT_FLASH_ENABLE    0x21
 
-#define        CONFIG_SYS_MAX_FLASH_SECT       128
-#define        CONFIG_SYS_FLASH_ERASE_TOUT     10000000
-
 #define CONFIG_SYS_FLASH_SIZE          16*1024*1024
 
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
index 3dc111f5248d419d988e5332c712d5fac55722da..597efd6745cd397b36edc7c4f68660990eb14a4e 100644 (file)
@@ -16,9 +16,7 @@
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
 #define CONFIG_FLASH_SHOW_PROGRESS     45
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_FLASH_BANKS_LIST    { 0x08000000 }
-#define CONFIG_SYS_MAX_FLASH_SECT      256
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 #endif /* __EBISU_H */
index 86257016824fc11f2a56d58e75ae4e0f52eab210..d2f1cd5d5c8cdf468f78945c2e678f5b3d0de4dc 100644 (file)
@@ -79,7 +79,6 @@
  * FLASH configuration
  */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      11 /* max num of sects on one chip */
 #define CONFIG_SYS_FLASH_BASE          0xfff80000
 
 /* auto boot */
index 3acc62d9e178649b4d922afe65c5b2e4d3655e33..7923fbb599d1a0e76c79d7eda6681efac7b60e66 100644 (file)
@@ -15,7 +15,6 @@
 #include "siemens-am33x-common.h"
 /* NAND specific changes for etamin due to different page size */
 #undef CONFIG_SYS_NAND_ECCPOS
-#undef CONFIG_SYS_ENV_SECT_SIZE
 
 #define CONFIG_SYS_ENV_SECT_SIZE       (512 << 10)     /* 512 KiB */
 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
index 88a702f1af27bb99ee64d41bbe5eb79c284bb9a8..7a3c800dca9c1150bc35f666c3f7ca9515b212c2 100644 (file)
@@ -31,7 +31,6 @@
 
 /* 512kB on-chip NOR flash */
 # define CONFIG_SYS_FLASH_BASE         0x00200000 /* AT91SAM9XE_FLASH_BASE */
-# define CONFIG_SYS_MAX_FLASH_SECT     32
 
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
index 25095e192f0bcf66fb73cf04b9f1e0e0f8d058d4..e592dc44e4d78018ffffd8cbd8ad9e93493ad17a 100644 (file)
@@ -40,8 +40,6 @@
 #define CONFIG_SYS_FLASH_BASE          0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE          8 /* FLASH size is up to 8M */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      135
-
 #define CONFIG_SYS_BAUDRATE_TABLE  \
        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 
index a8bb2090ec4a227ce3e1841c5302f92c4345f543..e89b800b7eeb4368125f4a1d97c8259d05879515 100644 (file)
@@ -41,7 +41,7 @@
  * Manually set up DDR parameters,
  * as this board has not the SPD connected to I2C.
  */
-#define CONFIG_SYS_DDR_SIZE            256             /* MB */
+#define CONFIG_SYS_SDRAM_SIZE          0x10000000 /* 256 MiB */
 #define CONFIG_SYS_DDR_CONFIG          (CSCONFIG_EN |\
                                         0x00010000 |\
                                         CSCONFIG_ROW_BIT_13 |\
 #define CONFIG_SYS_FLASH_BASE          0xFF800000
 #define CONFIG_SYS_FLASH_SIZE          8
 
-
-#define CONFIG_SYS_MAX_FLASH_SECT      128
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500
-
 /*
  * NAND FLASH setup
  */
 #define CONFIG_SYS_MRAM_BASE           0xE2000000
 #define CONFIG_SYS_MRAM_SIZE           0x20000 /* 128 Kb */
 
-#define CONFIG_SYS_OR_TIMING_MRAM
-
-
 /*
  * CPLD setup
  */
 #define CONFIG_SYS_CPLD_BASE           0xE3000000
-#define CONFIG_SYS_CPLD_SIZE           0x8000
-
-#define CONFIG_SYS_OR_TIMING_MRAM
-
 
 /*
  * HW-Watchdog
index 17430f15d139292532ddbc2b1e20d9ee0ace38cd..6ebdc3d6f976cf8625c3e79400c357b1e98786c9 100644 (file)
@@ -81,8 +81,6 @@
 #define PHYS_FLASH_1                   0xc0000000
 /* Flash Base for U-Boot */
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT      (PHYS_FLASH_SIZE / \
-               CONFIG_SYS_FLASH_SECT_SZ)
 #define CONFIG_SYS_MONITOR_LEN         0x40000         /* Reserve 256KiB */
 /* Address and size of Redundant Environment Sector    */
 
index 34eec5a33d258ceef6bb8dd97ad3255fc6c64dda..512e0e61aa78b1c27db0968ac767dd49939c01f6 100644 (file)
@@ -44,6 +44,3 @@
 #define CONFIG_SYS_FLASH_BASE          0x24000000
 
 /* Timeout values in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    (2 * CONFIG_SYS_HZ) /* Erase Timeout */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    (2 * CONFIG_SYS_HZ) /* Write Timeout */
-#define CONFIG_SYS_FLASH_EMPTY_INFO    /* flinfo indicates empty blocks */
index 49f07e997d837c546b62154d0311a2432f853c0f..c8457d97161a10a8c1296022750c794354056874 100644 (file)
@@ -21,7 +21,6 @@
 
 /* Flash settings */
 #define CONFIG_SYS_FLASH_SIZE          0x02000000 /* 32 MiB */
-#define CONFIG_SYS_MAX_FLASH_SECT      128
 
 /*-----------------------------------------------------------------------
  * PCI definitions
index 288014c5b82edbde61cf644c736ffd26ba9d55c6..2752152f68ee42448f74d86223724c8ce318f0bd 100644 (file)
@@ -34,7 +34,6 @@
  * Miscellaneous configurable options
  */
 #define PHYS_FLASH_SIZE                        0x01000000      /* 16MB */
-#define CONFIG_SYS_MAX_FLASH_SECT      64
 #define CONFIG_SYS_MONITOR_LEN         0x00100000
 
 #endif /* __CONFIG_H */
index 9f76f48a5c6bc32532713d829c19e941663ad18b..04192d86b7007e3828e8084450ff6dfcdfe6712f 100644 (file)
@@ -18,7 +18,7 @@
 /*
  * Manually set up DDR parameters
  */
-#define CONFIG_SYS_DDR_SIZE            2048 /* MB */
+#define CONFIG_SYS_SDRAM_SIZE          0x80000000 /* 2048 MiB */
 
 /*
  * The reserved memory
@@ -49,7 +49,6 @@
  */
 #define CONFIG_SYS_FLASH_SIZE          256 /* max FLASH size is 256M */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 
 /* I2C */
index 6becd7cd31a85ff25184921d58fc4108b698afa2..20a36fbe115e45e051b7290181cecd56d84736a6 100644 (file)
@@ -9,9 +9,6 @@
 
 /* Do boardspecific init for all boards */
 
-/* EEprom support 24C08, 24C16, 24C64 */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-
 /* Increase max size of compressed kernel */
 
 /******************************************************************************
index eee71db37c2bfaa5947d3af33cf5e410ef2e83e4..a91e5e8f8654cfecfccb6adb045eb9b09dcdccdc 100644 (file)
@@ -97,9 +97,6 @@ extern void __set_direction(unsigned pin, int high);
 #define I2C_DELAY      udelay(1)
 #define I2C_SOFT_DECLARATIONS
 
-/* EEprom support 24C128, 24C256 valid for environment eeprom */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-
 /*
  *  Environment variables configurations
  */
index f83739013507938958819bc59cef60486422a749..43471e08d604f2bb0a31153f74e03e628528bf3c 100644 (file)
                                        FTIM2_NOR_TWP(0xb))
 #define CONFIG_SYS_NOR_FTIM3           0
 
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45      /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      512     /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE_PHYS }
 
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
index b389229b7546064d062ec3d46d4f107a40f24e74..589ba615dd6ddbdd80fa58bc6fa6ac9cd38e34d0 100644 (file)
 #define KM_I2C_DEBLOCK_SDA     21
 
 /* High Level Configuration Options */
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 
 #define CONFIG_RESET_VECTOR_ADDRESS    0xebfffffc
 
 #define CONFIG_SYS_CS0_FTIM3   CONFIG_SYS_NOR_FTIM3
 
 /* More NOR Flash params */
-#define CONFIG_SYS_FLASH_QUIET_TEST
 
-#define CONFIG_SYS_MAX_FLASH_SECT      512     /* sectors per device */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
 
 /* NAND Flash on IFC CS1*/
index e084f87d14dda8c2341cd457516833240027d22d..602c1c5391905c5d5250d0d2b00de2a0aaef7cf1 100644 (file)
@@ -19,7 +19,6 @@
 /* NOR Flash */
 #define KZM_FLASH_BASE (0x00000000)
 #define CONFIG_SYS_FLASH_BASE          (KZM_FLASH_BASE)
-#define CONFIG_SYS_MAX_FLASH_SECT      (512)
 
 /* prompt */
 #define CONFIG_SYS_BAUDRATE_TABLE      { 115200 }
 #define CONFIG_STANDALONE_LOAD_ADDR    0x41000000
 
 /* FLASH */
-#undef  CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define FLASH_SECTOR_SIZE      (256 * 1024)    /* 256 KB sectors */
 
 /* Timeout for Flash erase operations (in ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    (3 * 1000)
 /* Timeout for Flash write operations (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    (3 * 1000)
 /* Timeout for Flash set sector lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT             (3 * 1000)
 /* Timeout for Flash clear lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT   (3 * 1000)
-
-#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
 
 /* GPIO / PFC */
 #define CONFIG_SH_GPIO_PFC
index b124ce52620cae2dcd4522048b043ca9182b4d45..48fe8288aa187df8dbfd0f6383e2996a469c4d03 100644 (file)
 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 
-/* DSPI */
-#define CONFIG_FSL_DSPI1
-
-#define MMAP_DSPI          DSPI1_BASE_ADDR
-
-#define CONFIG_SYS_DSPI_CTAR0   1
-
-#define CONFIG_SYS_DSPI_CTAR1  (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
-                               DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
-                               DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
-                               DSPI_CTAR_DT(0))
-
-#define CONFIG_SYS_DSPI_CTAR2  (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
-                               DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
-                               DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
-                               DSPI_CTAR_DT(0))
-
-#define CONFIG_SYS_DSPI_CTAR3  (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
-                               DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
-                               DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
-                               DSPI_CTAR_DT(0))
-
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS              \
        "verify=no\0"                           \
index 517ade383beea973b12d094dea61c6985f99fc14..d9a973c13fba35a92b8c6ae0ce8444d9132a5743 100644 (file)
                                        FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3           0
 
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS, \
                                        CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 
index 1aa29e541ec5bb73a8db02c97ca805e34a23be11..5f3e8d5b71288e37d5b04daa30c9644b9739bf1c 100644 (file)
                                        FTIM2_NOR_TWPH(0x0e))
 #define CONFIG_SYS_NOR_FTIM3           0
 
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45      /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE_PHYS }
 
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
index 95cbcb036eb83183bf74810573997bcd5168224e..43f30fd70f7183655477f41fc8f4929da4e7d867 100644 (file)
 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY       0x00000000
 
 #ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45      /* count down from 45/5: 9..1 */
 #endif
 #endif
index 15c3ff53fe8e7544681ffc4aa0fe1bb96a0de86b..49f6cd6be11b150ac8ccec1a4707386e7dbf28e5 100644 (file)
                                        FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3           0
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS, \
                                        CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 
index 6c33847b27b6e5bc287c380ab74c7781cca94f11..d36b2c7e557b2825b019276b436a1d37fec96eb4 100644 (file)
 #define CONFIG_SYS_NOR_FTIM3           0
 #define CONFIG_SYS_IFC_CCR             0x01000000
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE_PHYS }
 
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
index 36c64db8f5d17a2e061001a97c411109a7399378..869bbd763461aeae267bf992216e8d7c3b085a90 100644 (file)
@@ -43,7 +43,6 @@
 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY       0x00000000
 
 #ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45      /* count down from 45/5: 9..1 */
 #endif
 #endif
                                        FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3           0
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS, \
                                        CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 
index debb60d25cef92b773823f30d3033e2561470b7b..747ee9d4428a796d4fdfd72a37194420d4937fa5 100644 (file)
 #define CONFIG_SYS_IFC_CCR     0x01000000
 
 #ifndef SYS_NO_FLASH
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE,\
                                         CONFIG_SYS_FLASH_BASE + 0x40000000}
 #endif
 #endif
 #endif
 
-#define CONFIG_FSL_MEMAC
-
 #define COMMON_ENV \
        "kernelheader_addr_r=0x80200000\0"      \
        "fdtheader_addr_r=0x80100000\0"         \
 #endif
 
 #ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_FSL_MEMAC
 #define RGMII_PHY1_ADDR                0x1
 #define RGMII_PHY2_ADDR                0x2
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
index c0567c3fe580a9e8e54970316a046521b638f144..3e829ea8659a147d73301b5ede4e80373abbd995 100644 (file)
 #define CONFIG_SYS_IFC_CCR     0x01000000
 
 #ifndef SYS_NO_FLASH
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
 #endif
 #endif
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM              0
 
-#define CONFIG_FSL_MEMAC
-
 #ifndef SPL_NO_ENV
 /* Initial environment variables */
 #ifdef CONFIG_TFABOOT
index 3e86d1bff215c32dc019a9fedf6f845080fa7049..ba5af6c34d344b0488c8d409353e32f8ac7610c8 100644 (file)
@@ -16,8 +16,6 @@
 
 /* Link Definitions */
 
-#define CONFIG_SYS_FSL_DDR_INTLV_256B  /* force 256 byte interleaving */
-
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0
index 9ba7258572fcdf25cc112ae2ecc45b814aababd7..6487397f65286ecbbed3329294cacfd54f37e9da 100644 (file)
 #define CONFIG_SYS_IFC_CCR     0x01000000
 
 #ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE,\
                                         CONFIG_SYS_FLASH_BASE + 0x40000000}
 #endif
 #define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NAND_FTIM3
 #endif
 
-/* Debug Server firmware */
-#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR        0x580D00000ULL
-
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 /*
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM      0
 
-#define CONFIG_FSL_MEMAC
-
 /* Initial environment variables */
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #ifdef CONFIG_NXP_ESBC
 #endif
 
 #if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_FSL_MEMAC
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
index a504a0ea462a1c34d3bd7cede7285895457b07f4..87d07b765c6c53c978642cdad81aeb17a146670b 100644 (file)
 #define CONFIG_SYS_IFC_CCR     0x01000000
 
 #ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE,\
                                         CONFIG_SYS_FLASH_BASE + 0x40000000}
 #endif
 #define CONFIG_SYS_CS2_FTIM2           CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NAND_FTIM3
 #endif
-
-/* Debug Server firmware */
-#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR        0x580D00000ULL
 #endif
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM      0
 
-#define CONFIG_FSL_MEMAC
-
 #define BOOT_TARGET_DEVICES(func) \
        func(USB, usb, 0) \
        func(MMC, mmc, 0) \
index 81c93375e2efa5b79a2d4ccd99bc6718b55c92c3..e1108619f21b5cd7ca0e38a7f5074f9c5c98b9d0 100644 (file)
@@ -18,9 +18,6 @@
 /*
  *  Environment variables configurations
  */
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_SYS_MAX_FLASH_SECT      8
-#endif
 
 /*
  * Default environment variables
index b7543731691fc41a70eec82d40e1b781eb481973..61870717e8e18dcdce2ec553ca5d4516540c9cda 100644 (file)
 #include <asm/arch/config.h>
 #include <asm/arch/soc.h>
 
-#define CONFIG_FSL_MEMAC
-
 #define CONFIG_SYS_FLASH_BASE          0x20000000
 
 /* DDR */
-#define CONFIG_SYS_FSL_DDR_INTLV_256B  /* force 256 byte interleaving */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE              0x80000000UL
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0
index c8b230ab21e9c22c6ccfd76b2bf787273fe09e90..5a42ceef21218fe1f39ca18a12a3b1a0b7a48563 100644 (file)
@@ -30,7 +30,7 @@
 #else
 # define CONFIG_SYS_SDRAM_BASE         0x80000000
 #endif
-#define CONFIG_SYS_MEM_SIZE            (256 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_SIZE          0x10000000      /* 256 MiB */
 
 #define CONFIG_SYS_INIT_SP_OFFSET      0x400000
 
@@ -47,7 +47,6 @@
 #else
 # define CONFIG_SYS_FLASH_BASE         0xbe000000
 #endif
-#define CONFIG_SYS_MAX_FLASH_SECT      128
 
 /*
  * Environment
index 02a22351874bf88e25799a9b8cfb10cabdb574c5..17986a0e348aa64809b11c6af73f7f2e24ce152c 100644 (file)
@@ -27,7 +27,6 @@
 
 /* NOR 16-bit mode */
 #define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_FLASH_VERIFY
 
 /* NOR Flash MTD */
index 73f84922288091b62852a62bed26e908b11883be..8eaac4f8bc22a148d1b8a9d41aa7ff77536d051e 100644 (file)
 # define CONFIG_SYS_BAUDRATE_TABLE \
        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
-#ifdef CONFIG_CFI_FLASH
-/* ?empty sector */
-# define CONFIG_SYS_FLASH_EMPTY_INFO   1
-/* max number of memory banks */
-/* max number of sectors on one chip */
-# define CONFIG_SYS_MAX_FLASH_SECT     2048
-#endif
-
 #define        CONFIG_HOSTNAME         "microblaze-generic"
 
 /* architecture dependent code */
index bc4aa52f5bf178983378d550cea99aa23ff8fc8c..c76e7ea1605a4d6e855eac838f43fe6582b682dc 100644 (file)
@@ -31,9 +31,6 @@
 
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
-#define CONFIG_SYS_FLASH_SECT_SIZE      (128 * 1024)
-#define CONFIG_SYS_MAX_FLASH_SECT 256   /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #endif
 
 #define CONFIG_SYS_FSL_USDHC_NUM       2
index 7035e6313420690d18a6c557d64cb5b73ca5b096..5479bdedee5d029cf52269416843deba36747cc2 100644 (file)
@@ -9,12 +9,6 @@
 
 #include "octeon_common.h"
 
-/*
- * CFI flash
- */
-#define CONFIG_SYS_MAX_FLASH_SECT      256
-#define CONFIG_SYS_FLASH_EMPTY_INFO    /* flinfo indicates empty blocks */
-
 #define PHY_ANEG_TIMEOUT       8000    /* PHY needs a longer aneg time */
 
 #endif /* __CONFIG_H__ */
index 2cd42e5a1dc49bc231d1707763580c657cb69d77..ad3dbbcac52f918b3c692c4845575b77b70f5336 100644 (file)
@@ -26,7 +26,6 @@
                                          10, 11, 12, 13}
 #define CONFIG_SYS_NAND_ECCSIZE         512
 #define CONFIG_SYS_NAND_ECCBYTES        3
-#define CONFIG_SYS_ENV_SECT_SIZE        SZ_128K
 /* NAND: SPL falcon mode configs */
 #endif /* CONFIG_MTD_RAW_NAND */
 
index 2683d4c7ea45a659e74af9b16bdbd9a626aa07e6..c47d5573c46af58eaba2d4a457879eb98a46e389 100644 (file)
@@ -31,7 +31,6 @@
                                          10, 11, 12, 13}
 #define CONFIG_SYS_NAND_ECCSIZE         512
 #define CONFIG_SYS_NAND_ECCBYTES        3
-#define CONFIG_SYS_ENV_SECT_SIZE        SZ_128K
 #endif /* CONFIG_MTD_RAW_NAND */
 
 #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
index 38dc7ea88f7b545a98e56ff7a027d3a3a9f6c14b..1af87b271c4fa3e551c129877bcaffada566c4c7 100644 (file)
 #define CONFIG_SYS_FLASH_BASE          0x10000000
 #endif
 
-#define CONFIG_SYS_MAX_FLASH_SECT      256
 #define CONFIG_SYS_FLASH_SIZE          0x4000000
 
-#define CONFIG_SYS_ENV_SECT_SIZE       (128 << 10)     /* 128 KiB */
-
 #endif /* __CONFIG_H */
index ba04029df8d89aee11c3e8a28640f3ced4aea931..f7d8723b03d4faedc810c4b1a452b60db6bfe34e 100644 (file)
  * Local Bus Definitions
  */
 #if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_MAX_FLASH_SECT      512     /* 64M */
 #define CONFIG_SYS_FLASH_BASE          0xec000000
 #else
-#define CONFIG_SYS_MAX_FLASH_SECT      128     /* 16M */
 #define CONFIG_SYS_FLASH_BASE          0xef000000
 #endif
 
 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
 
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45      /* count down from 45/5: 9..1 */
 
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
 /* Nand Flash */
 #ifdef CONFIG_NAND_FSL_ELBC
 #define CONFIG_SYS_NAND_BASE           0xff800000
index 7374514698f9ebe1a8c29633a99f34891633608e..797e44f844de01a7a67074f74b87985b1532d454 100644 (file)
 /* NOR flash */
 #define PHYS_FLASH_1                           0x10000000
 #define CONFIG_SYS_FLASH_BASE                  PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT              256
 
 /* USB */
 #define CONFIG_SYS_USB_OHCI_REGS_BASE          0x00500000
index 7a6d817926c7450997ab6eefcf8627a56af7f211..bb5bd8b60646a3d938d2b564000f568ea36e7876 100644 (file)
 /* NOR flash, if populated */
 #define PHYS_FLASH_1                   0x10000000
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT      256
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
index e9f756b13edbb238a2afb08b4e934820212b0205..dd2faebbbb269e0325bc38a6f70a6f7c20e5d86c 100644 (file)
@@ -74,6 +74,4 @@
        "ramdisk_addr_r=0x44000000\0" \
        BOOTENV
 
-#define CONFIG_SYS_MAX_FLASH_SECT      256 /* Sector: 256K, Bank: 64M */
-
 #endif /* __CONFIG_H */
index 31e94df84df7eb88df2e53bb175ad23276fe7cf3..5181792b7b73f20e6948562fa02b24c07ec1d599 100644 (file)
@@ -33,8 +33,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void);
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_SYS_BOOT_BLOCK          0x00000000      /* boot TLB */
-
 #define CONFIG_HWCONFIG
 
 #define CONFIG_SYS_INIT_RAM_ADDR               0x00100000
index 409d5af0241df1c90626175885d49d33f6ca9b98..f0dfba3fd49f6496ea8f63e1b5a7e8c285d00a2c 100644 (file)
@@ -17,7 +17,6 @@
  * NOR Flash ( Spantion S29GL256P )
  */
 #define CONFIG_SYS_FLASH_BASE          (0xA0000000)
-#define CONFIG_SYS_MAX_FLASH_SECT  256
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
 
 /*
index 43593572d963a16ecf20f43f8ec48d5042aabf51..ae94f0ecc56a00c192df981b14fd1cf057946788 100644 (file)
 /*-----------------------------------------------------------------------
  *  System memory Configuration
  */
-#define CONFIG_SYS_MEM_SIZE            0x40000000
 #define CONFIG_SYS_SDRAM_BASE          0x71000000
 
 /*
- * "(CONFIG_SYS_MEM_SIZE - CONFIG_SYS_RESERVE_MEM_SIZE)" has been used in
+ * "(0x40000000 - CONFIG_SYS_RESERVE_MEM_SIZE)" has been used in
  * u-boot nanopi2-v2016.01.
  * This is not working anymore because boot_fdt_add_mem_rsv_regions() in
  * common/image-fdt.c has been extended:
index 4b0f20e89b7cc455c3cb77ea7c7d85f0a510e40a..41e52546ed325502fe242f8171d13838b6967415 100644 (file)
@@ -14,9 +14,7 @@
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
 #define CONFIG_FLASH_SHOW_PROGRESS     45
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_FLASH_BANKS_LIST    { 0x08000000 }
-#define CONFIG_SYS_MAX_FLASH_SECT      256
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 #endif /* __SALVATOR_X_H */
index 7bc3f91e77a80967ebe216cb186b2ac1c4255b9a..b48e40bee440764267e8f45d756c8629a5bda598 100644 (file)
@@ -31,7 +31,6 @@
 /* NOR flash */
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_SYS_FLASH_BASE          0x10000000
-#define CONFIG_SYS_MAX_FLASH_SECT      131
 #endif
 
 /* SDRAM */
index d2d4296eed6232dc32a4f807a3c55d88ecdd8c73..fcb0fd5cec3b2782b7b0f84e93862484532404f4 100644 (file)
                                                        /* CS0 */
 #define CONFIG_SYS_MAX_NAND_DEVICE     1               /* Max number of NAND
                                                           devices */
-#if !defined(CONFIG_SPI_BOOT)
-#define CONFIG_SYS_ENV_SECT_SIZE       (128 << 10)     /* 128 KiB */
-#endif
 #endif
 
 #endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
index 5dc8d8559882f88286b5bf2f3315a7b24a22573c..498deb4e3fc7dde311360e6f4f7dda9aba0e5641 100644 (file)
@@ -80,7 +80,6 @@
  */
 #define CONFIG_SYS_LBC_CACHE_BASE      0xf0000000      /* Localbus cacheable    */
 
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_FLASH0              0xFE000000
 #define CONFIG_SYS_FLASH1              0xFC000000
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 #define CONFIG_SYS_LBC_FLASH_BASE      CONFIG_SYS_FLASH1       /* Localbus flash start */
 #define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH     */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      256             /* sectors per device   */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms)     */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms)     */
-
 #define CONFIG_SYS_LBC_LCRR            0x00030004    /* LB clock ratio reg     */
 #define CONFIG_SYS_LBC_LBCR            0x00000000    /* LB config reg          */
 #define CONFIG_SYS_LBC_LSRT            0x20000000    /* LB sdram refresh timer */
index 18c9e5bfb6eb1743471146e8d541bdc6863a553f..51f69010b17929e58ad9c1664f55ea3bdd5adf0a 100644 (file)
@@ -13,8 +13,6 @@
  * Configuration of the external SDRAM memory
  */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      12
-
 #define CONFIG_SYS_HZ_CLOCK            1000000 /* Timer is clocked at 1MHz */
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
index 6849477beafbf00d5ba786cd6903dacb2d2f09c6..221b7abe1ad7b378efe63bcd9cb32ef375426257 100644 (file)
@@ -18,8 +18,6 @@
  * Configuration of the external SDRAM memory
  */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      12
-
 #define CONFIG_SYS_HZ_CLOCK            1000000 /* Timer is clocked at 1MHz */
 
 #define BOOT_TARGET_DEVICES(func) \
index 2d8b2d27c9254dfde88ff1840e5897dab808d487..55e70ce92508aed608f0f930209f62921beb875e 100644 (file)
@@ -18,8 +18,6 @@
  * Configuration of the external SDRAM memory
  */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      12
-
 #define CONFIG_SYS_HZ_CLOCK            1000000 /* Timer is clocked at 1MHz */
 
 #define BOOT_TARGET_DEVICES(func) \
index df05ee4892a50b34eecfb4b47798a30a29d8137a..64c1bc7d43ff038237b22695a487c9907b8cfd72 100644 (file)
@@ -18,8 +18,6 @@
  * Configuration of the external SDRAM memory
  */
 
-#define CONFIG_SYS_MAX_FLASH_SECT      8
-
 #define CONFIG_SYS_HZ_CLOCK            1000000 /* Timer is clocked at 1MHz */
 
 #define BOOT_TARGET_DEVICES(func) \
index 4fb3d731c67ab53bb8275dc2e18447a6082d8bc8..7c77a8d53690b74ee0b0dace8b65ef1fd61907f9 100644 (file)
  */
 
 #define CONFIG_SYS_FLASH_BASE          0x0C000000
-/* 256 x 256KiB sectors */
-#define CONFIG_SYS_MAX_FLASH_SECT      256
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO    /* flinfo indicates empty blocks */
-#define FLASH_MAX_SECTOR_SIZE          0x00040000
 
 #endif /* __TOTAL_COMPUTE_H */
index 578873295fb9d0db036849139cbbdb5689eb49a5..a977271c1e6e8447dff1d10e8653a5d53d7625ef 100644 (file)
@@ -14,9 +14,7 @@
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 
 #define CONFIG_FLASH_SHOW_PROGRESS     45
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_FLASH_BANKS_LIST    { 0x08000000 }
-#define CONFIG_SYS_MAX_FLASH_SECT      256
 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 #endif /* __ULCB_H */
index 3705313aec064a56619af2d9da412cc96d1ea7d1..077428f500408fdc281ce3ccb0f335de4f856347 100644 (file)
 
 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 #define CONFIG_SYS_FLASH_BASE          0x08000000
-/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
-#define CONFIG_SYS_MAX_FLASH_SECT      259
-/* Store environment at top of flash in the same location as blank.img */
-/* in the Juno firmware. */
 #else
 #define CONFIG_SYS_FLASH_BASE          (V2M_PA_BASE + 0x0C000000)
-/* 256 x 256KiB sectors */
-#define CONFIG_SYS_MAX_FLASH_SECT      256
-/* Store environment at top of flash */
 #endif
 
-#define CONFIG_SYS_FLASH_EMPTY_INFO    /* flinfo indicates empty blocks */
-#define FLASH_MAX_SECTOR_SIZE          0x00040000
-
 #endif /* __VEXPRESS_AEMV8_H */
index ff7307f09044230f25b7b7017a5a3a6b8f9d161f..7c0856ae325a424d16e772e95c7321704edd5153 100644 (file)
                "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
 
 /* FLASH and environment organization */
-#define PHYS_FLASH_SIZE                        0x04000000      /* 64MB */
 #define CONFIG_SYS_FLASH_SIZE          0x04000000
-#define CONFIG_SYS_FLASH_BASE0         V2M_NOR0
-#define CONFIG_SYS_FLASH_BASE1         V2M_NOR1
 
 /* Timeout values in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    (2 * CONFIG_SYS_HZ) /* Erase Timeout */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    (2 * CONFIG_SYS_HZ) /* Write Timeout */
-
-/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
-#define CONFIG_SYS_MAX_FLASH_SECT      259             /* Max sectors */
-#define FLASH_MAX_SECTOR_SIZE          0x00040000      /* 256 KB sectors */
 
 /* Room required on the stack for the environment data */
 
  */
 
 /* Store environment at top of flash */
-#define CONFIG_SYS_FLASH_EMPTY_INFO    /* flinfo indicates empty blocks */
-#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE0, \
-                                         CONFIG_SYS_FLASH_BASE1 }
+#define CONFIG_SYS_FLASH_BANKS_LIST    { V2M_NOR0, V2M_NOR1 }
 
 #endif /* VEXPRESS_COMMON_H */
index f1ea47654671f187e842ae8bc30a170ed4e5eb3b..ad8ea6538c202fd154d728f710296e6e640ec8f5 100644 (file)
 
 #if defined(CONFIG_MAX_MEM_MAPPED) && \
        CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE
-#define CONFIG_SYS_MEMORY_SIZE         CONFIG_MAX_MEM_MAPPED
+#define XTENSA_SYS_TEXT_ADDR           \
+       (MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN)
 #else
-#define CONFIG_SYS_MEMORY_SIZE         CONFIG_SYS_SDRAM_SIZE
-#endif
-
 #define XTENSA_SYS_TEXT_ADDR           \
-       (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN)
+       (MEMADDR(CONFIG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)
+#endif
 
 /*==============================*/
 /* U-Boot general configuration */
  * SHIFT left amount and field WIDTH (bits), and also by a bitMASK.
  */
 
-/* Date of FPGA bitstream build in binary coded decimal (BCD) */
-#define CONFIG_SYS_FPGAREG_DATE                IOADDR(0x0D020000)
-#define FPGAREG_MTH_SHIFT              24              /* BCD month 1..12 */
-#define FPGAREG_MTH_WIDTH              8
-#define FPGAREG_MTH_MASK               0xFF000000
-#define FPGAREG_DAY_SHIFT              16              /* BCD day 1..31 */
-#define FPGAREG_DAY_WIDTH              8
-#define FPGAREG_DAY_MASK               0x00FF0000
-#define FPGAREG_YEAR_SHIFT             0               /* BCD year 2001..9999*/
-#define FPGAREG_YEAR_WIDTH             16
-#define FPGAREG_YEAR_MASK              0x0000FFFF
-
 /* FPGA core clock frequency in Hz (also input to UART) */
 #define CONFIG_SYS_FPGAREG_FREQ        IOADDR(0x0D020004)      /* CPU clock frequency*/
 
 
 #ifdef CONFIG_XTFPGA_LX60
 # define CONFIG_SYS_FLASH_SIZE         0x0040000       /* 4MB */
-# define CONFIG_SYS_FLASH_SECT_SZ      0x10000         /* block size 64KB */
 # define CONFIG_SYS_FLASH_PARMSECT_SZ  0x2000          /* param size  8KB */
 # define CONFIG_SYS_FLASH_BASE         IOADDR(0x08000000)
 #elif defined(CONFIG_XTFPGA_KC705)
 # define CONFIG_SYS_FLASH_SIZE         0x8000000       /* 128MB */
-# define CONFIG_SYS_FLASH_SECT_SZ      0x20000         /* block size 128KB */
 # define CONFIG_SYS_FLASH_PARMSECT_SZ  0x8000          /* param size 32KB */
 # define CONFIG_SYS_FLASH_BASE         IOADDR(0x00000000)
 #else
 # define CONFIG_SYS_FLASH_SIZE         0x1000000       /* 16MB */
-# define CONFIG_SYS_FLASH_SECT_SZ      0x20000         /* block size 128KB */
 # define CONFIG_SYS_FLASH_PARMSECT_SZ  0x8000          /* param size 32KB */
 # define CONFIG_SYS_FLASH_BASE         IOADDR(0x08000000)
 #endif
-#define CONFIG_SYS_MAX_FLASH_SECT      \
-       (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \
-        CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1)
 
 /*
  * Put environment in top block (64kB)
  */
 
 /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 
 #endif /* __CONFIG_H */
index 1fdde90654f259e6e5c5437faa62cd56146b5d6e..75ae68766fa1ba96c931c4012f7f6131b899f978 100644 (file)
 
 /* NOR */
 #ifdef CONFIG_MTD_NOR_FLASH
-# define CONFIG_SYS_MAX_FLASH_SECT     512
-# define CONFIG_SYS_FLASH_ERASE_TOUT   1000
-# define CONFIG_SYS_FLASH_WRITE_TOUT   5000
 # define CONFIG_FLASH_SHOW_PROGRESS    10
-# undef CONFIG_SYS_FLASH_EMPTY_INFO
-# define CONFIG_SYS_FLASH_QUIET_TEST
 #endif
 
 #ifdef CONFIG_NAND_ZYNQ
index f3959f5012021a2033f0696442d9e5eb4089fa86..95992fa689bbc7c8cbb2fbe34e7cbdac958a77f4 100644 (file)
@@ -7,10 +7,6 @@
 #ifndef _FLASH_H_
 #define _FLASH_H_
 
-#ifndef CONFIG_SYS_MAX_FLASH_SECT
-#define CONFIG_SYS_MAX_FLASH_SECT      512
-#endif
-
 /*-----------------------------------------------------------------------
  * FLASH Info: contains chip specific data, per FLASH bank
  */
@@ -91,6 +87,7 @@ int flash_sect_erase(ulong addr_first, ulong addr_last);
 int flash_sect_protect(int flag, ulong addr_first, ulong addr_last);
 int flash_sect_roundb(ulong *addr);
 unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect);
+void flash_cmd_reset(flash_info_t *info);
 void flash_set_verbose(uint v);
 
 /* common/flash.c */
index d4aeea7e464b05a0d8c5fec91e967738fb8eb112..1321da191028f6245d1562595873f241c63aae78 100644 (file)
@@ -176,7 +176,6 @@ extern int cfi_flash_num_flash_banks;
 
 phys_addr_t cfi_flash_bank_addr(int i);
 unsigned long cfi_flash_bank_size(int i);
-void flash_cmd_reset(flash_info_t *info);
 
 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 void flash_write8(u8 value, void *addr);
index 9152ab742ef1a327254547d8ae125588b736b105..9f65cfb20dc9eb0d7447e041cfcb1e9afc0c9e53 100644 (file)
--- a/net/nfs.c
+++ b/net/nfs.c
@@ -28,7 +28,9 @@
 
 #include <common.h>
 #include <command.h>
+#ifdef CONFIG_SYS_DIRECT_FLASH_NFS
 #include <flash.h>
+#endif
 #include <image.h>
 #include <log.h>
 #include <net.h>
index bfc4c9bde9cb965484afe0c8188b2226d4bf1a6c..451d73529f2af9285e3c9ae9f9f26d2ab7dbb90f 100644 (file)
@@ -17,9 +17,6 @@
 #include <asm/global_data.h>
 #include <net/tftp.h>
 #include "bootp.h"
-#ifdef CONFIG_SYS_DIRECT_FLASH_TFTP
-#include <flash.h>
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -158,47 +155,24 @@ static inline int store_block(int block, uchar *src, unsigned int len)
                        tftp_block_size;
        ulong newsize = offset + len;
        ulong store_addr = tftp_load_addr + offset;
-#ifdef CONFIG_SYS_DIRECT_FLASH_TFTP
-       int i, rc = 0;
-
-       for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-               /* start address in flash? */
-               if (flash_info[i].flash_id == FLASH_UNKNOWN)
-                       continue;
-               if (store_addr >= flash_info[i].start[0]) {
-                       rc = 1;
-                       break;
-               }
-       }
-
-       if (rc) { /* Flash is destination for this packet */
-               rc = flash_write((char *)src, store_addr, len);
-               if (rc) {
-                       flash_perror(rc);
-                       return rc;
-               }
-       } else
-#endif /* CONFIG_SYS_DIRECT_FLASH_TFTP */
-       {
-               void *ptr;
+       void *ptr;
 
 #ifdef CONFIG_LMB
-               ulong end_addr = tftp_load_addr + tftp_load_size;
+       ulong end_addr = tftp_load_addr + tftp_load_size;
 
-               if (!end_addr)
-                       end_addr = ULONG_MAX;
+       if (!end_addr)
+               end_addr = ULONG_MAX;
 
-               if (store_addr < tftp_load_addr ||
-                   store_addr + len > end_addr) {
-                       puts("\nTFTP error: ");
-                       puts("trying to overwrite reserved memory...\n");
-                       return -1;
-               }
-#endif
-               ptr = map_sysmem(store_addr, len);
-               memcpy(ptr, src, len);
-               unmap_sysmem(ptr);
+       if (store_addr < tftp_load_addr ||
+           store_addr + len > end_addr) {
+               puts("\nTFTP error: ");
+               puts("trying to overwrite reserved memory...\n");
+               return -1;
        }
+#endif
+       ptr = map_sysmem(store_addr, len);
+       memcpy(ptr, src, len);
+       unmap_sysmem(ptr);
 
        if (net_boot_file_size < newsize)
                net_boot_file_size = newsize;
index 07eab332d21bccc18e9b8752e5718e7968929915..7d65f46d9fea7cbc8fbcd54b14acf5c5435ab809 100644 (file)
@@ -6,12 +6,12 @@
  * Licensed under the GPL-2 or later.
  */
 
+#if CONFIG_POST & CONFIG_SYS_POST_FLASH
 #include <common.h>
 #include <malloc.h>
 #include <post.h>
 #include <flash.h>
 
-#if CONFIG_POST & CONFIG_SYS_POST_FLASH
 
 /*
  * This code will walk over the declared sectors erasing them,
@@ -30,8 +30,6 @@
 # error "invalid flash block start/end"
 #endif
 
-extern flash_info_t flash_info[];
-
 static void *seed_src_data(void *ptr, ulong *old_len, ulong new_len)
 {
        unsigned char *p;
index fc07c5d2579c2ad8abeaa6840f4afceff6594183..4f628e0f1099eb6ec7f19d1d6d6467ec0bd5bda0 100644 (file)
@@ -32,7 +32,6 @@ CONFIG_FEC_ENET_DEV
 CONFIG_FEC_FIXED_SPEED
 CONFIG_FEC_MXC_PHYADDR
 CONFIG_FLASH_BR_PRELIM
-CONFIG_FLASH_CFI_LEGACY
 CONFIG_FLASH_OR_PRELIM
 CONFIG_FLASH_SECTOR_SIZE
 CONFIG_FLASH_SHOW_PROGRESS
@@ -40,16 +39,13 @@ CONFIG_FLASH_SPANSION_S29WS_N
 CONFIG_FLASH_VERIFY
 CONFIG_FM_PLAT_CLK_DIV
 CONFIG_FSL_CADMUS
-CONFIG_FSL_CORENET
 CONFIG_FSL_CPLD
 CONFIG_FSL_DEVICE_DISABLE
-CONFIG_FSL_DSPI1
 CONFIG_FSL_ESDHC_PIN_MUX
 CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
 CONFIG_FSL_IIM
 CONFIG_FSL_ISBC_KEY_EXT
 CONFIG_FSL_LBC
-CONFIG_FSL_MEMAC
 CONFIG_FSL_NGPIXIS
 CONFIG_FSL_PMIC_BITLEN
 CONFIG_FSL_PMIC_BUS
@@ -487,7 +483,6 @@ CONFIG_SYS_BMAN_SP_CENA_SIZE
 CONFIG_SYS_BMAN_SP_CINH_SIZE
 CONFIG_SYS_BMAN_SWP_ISDR_REG
 CONFIG_SYS_BOOTMAPSZ
-CONFIG_SYS_BOOT_BLOCK
 CONFIG_SYS_CACHE_ACR0
 CONFIG_SYS_CACHE_ACR1
 CONFIG_SYS_CACHE_ACR2
@@ -499,8 +494,6 @@ CONFIG_SYS_CCSRBAR_PHYS_HIGH
 CONFIG_SYS_CCSRBAR_PHYS_LOW
 CONFIG_SYS_CLK
 CONFIG_SYS_CLKTL_CBCDR
-CONFIG_SYS_CORE_SRAM
-CONFIG_SYS_CORE_SRAM_SIZE
 CONFIG_SYS_CPLD_AMASK
 CONFIG_SYS_CPLD_BASE
 CONFIG_SYS_CPLD_BASE_PHYS
@@ -511,7 +504,6 @@ CONFIG_SYS_CPLD_FTIM0
 CONFIG_SYS_CPLD_FTIM1
 CONFIG_SYS_CPLD_FTIM2
 CONFIG_SYS_CPLD_FTIM3
-CONFIG_SYS_CPLD_SIZE
 CONFIG_SYS_CPU_CLK
 CONFIG_SYS_CS0_BASE
 CONFIG_SYS_CS0_CTRL
@@ -602,7 +594,6 @@ CONFIG_SYS_DDR_CLKSEL
 CONFIG_SYS_DDR_CLK_CNTL
 CONFIG_SYS_DDR_CLK_CONTROL
 CONFIG_SYS_DDR_CLK_CTRL
-CONFIG_SYS_DDR_CLK_CTRL_667
 CONFIG_SYS_DDR_CLK_CTRL_800
 CONFIG_SYS_DDR_CONFIG
 CONFIG_SYS_DDR_CONFIG_2
@@ -618,15 +609,12 @@ CONFIG_SYS_DDR_CS1_CONFIG_2
 CONFIG_SYS_DDR_INIT_ADDR
 CONFIG_SYS_DDR_INIT_EXT_ADDR
 CONFIG_SYS_DDR_INTERVAL
-CONFIG_SYS_DDR_INTERVAL_667
 CONFIG_SYS_DDR_INTERVAL_800
 CONFIG_SYS_DDR_MODE
 CONFIG_SYS_DDR_MODE2
 CONFIG_SYS_DDR_MODE_1
-CONFIG_SYS_DDR_MODE_1_667
 CONFIG_SYS_DDR_MODE_1_800
 CONFIG_SYS_DDR_MODE_2
-CONFIG_SYS_DDR_MODE_2_667
 CONFIG_SYS_DDR_MODE_2_800
 CONFIG_SYS_DDR_MODE_CONTROL
 CONFIG_SYS_DDR_RCW_1
@@ -635,53 +623,34 @@ CONFIG_SYS_DDR_SDRAM_BASE
 CONFIG_SYS_DDR_SDRAM_CFG
 CONFIG_SYS_DDR_SDRAM_CFG2
 CONFIG_SYS_DDR_SDRAM_CLK_CNTL
-CONFIG_SYS_DDR_SIZE
 CONFIG_SYS_DDR_SR_CNTR
 CONFIG_SYS_DDR_TIMING_0
-CONFIG_SYS_DDR_TIMING_0_667
 CONFIG_SYS_DDR_TIMING_0_800
 CONFIG_SYS_DDR_TIMING_1
-CONFIG_SYS_DDR_TIMING_1_667
 CONFIG_SYS_DDR_TIMING_1_800
 CONFIG_SYS_DDR_TIMING_2
-CONFIG_SYS_DDR_TIMING_2_667
 CONFIG_SYS_DDR_TIMING_2_800
 CONFIG_SYS_DDR_TIMING_3
-CONFIG_SYS_DDR_TIMING_3_667
 CONFIG_SYS_DDR_TIMING_3_800
 CONFIG_SYS_DDR_TIMING_4
 CONFIG_SYS_DDR_TIMING_5
 CONFIG_SYS_DDR_WRLVL_CONTROL
-CONFIG_SYS_DDR_WRLVL_CONTROL_667
-CONFIG_SYS_DDR_WRLVL_CONTROL_800
 CONFIG_SYS_DDR_ZQ_CONTROL
-CONFIG_SYS_DEBUG
-CONFIG_SYS_DEBUG_SERVER_FW_ADDR
-CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
-CONFIG_SYS_DIRECT_FLASH_TFTP
 CONFIG_SYS_DPAA_DCE
 CONFIG_SYS_DPAA_FMAN
 CONFIG_SYS_DPAA_PME
 CONFIG_SYS_DPAA_RMAN
-CONFIG_SYS_DRAM_SIZE
 CONFIG_SYS_DRAM_TEST
-CONFIG_SYS_DSPI_CTAR0
-CONFIG_SYS_DSPI_CTAR1
-CONFIG_SYS_DSPI_CTAR2
-CONFIG_SYS_DSPI_CTAR3
 CONFIG_SYS_DV_NOR_BOOT_CFG
 CONFIG_SYS_EEPROM_BUS_NUM
-CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
 CONFIG_SYS_EEPROM_WREN
-CONFIG_SYS_ENET_BD_BASE
 CONFIG_SYS_ENV_SECT_SIZE
 CONFIG_SYS_ETHOC_BASE
 CONFIG_SYS_ETHOC_BUFFER_ADDR
 CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 CONFIG_SYS_FAST_CLK
 CONFIG_SYS_FDT_PAD
-CONFIG_SYS_FECI2C
 CONFIG_SYS_FEC_BUF_USE_SRAM
 CONFIG_SYS_FLASH0
 CONFIG_SYS_FLASH1
@@ -690,24 +659,10 @@ CONFIG_SYS_FLASH1_BASE_PHYS_EARLY
 CONFIG_SYS_FLASH_BANKS_LIST
 CONFIG_SYS_FLASH_BANKS_SIZES
 CONFIG_SYS_FLASH_BASE
-CONFIG_SYS_FLASH_BASE0
-CONFIG_SYS_FLASH_BASE1
 CONFIG_SYS_FLASH_BASE_PHYS
 CONFIG_SYS_FLASH_BASE_PHYS_EARLY
-CONFIG_SYS_FLASH_BR_PRELIM
-CONFIG_SYS_FLASH_CFI_NONBLOCK
-CONFIG_SYS_FLASH_CHECKSUM
-CONFIG_SYS_FLASH_EMPTY_INFO
-CONFIG_SYS_FLASH_ERASE_TOUT
-CONFIG_SYS_FLASH_LOCK_TOUT
-CONFIG_SYS_FLASH_OR_PRELIM
 CONFIG_SYS_FLASH_PARMSECT_SZ
-CONFIG_SYS_FLASH_QUIET_TEST
-CONFIG_SYS_FLASH_SECT_SIZE
-CONFIG_SYS_FLASH_SECT_SZ
 CONFIG_SYS_FLASH_SIZE
-CONFIG_SYS_FLASH_UNLOCK_TOUT
-CONFIG_SYS_FLASH_WRITE_TOUT
 CONFIG_SYS_FM1_10GEC1_PHY_ADDR
 CONFIG_SYS_FM1_CLK
 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
@@ -727,9 +682,7 @@ CONFIG_SYS_FM2_DTSEC1_PHY_ADDR
 CONFIG_SYS_FM2_DTSEC2_PHY_ADDR
 CONFIG_SYS_FM2_DTSEC3_PHY_ADDR
 CONFIG_SYS_FM2_DTSEC4_PHY_ADDR
-CONFIG_SYS_FMAN_V3
 CONFIG_SYS_FM_MURAM_SIZE
-CONFIG_SYS_FPGAREG_DATE
 CONFIG_SYS_FPGAREG_DIPSW
 CONFIG_SYS_FPGAREG_FREQ
 CONFIG_SYS_FPGAREG_RESET
@@ -747,10 +700,6 @@ CONFIG_SYS_FPGA_SIZE
 CONFIG_SYS_FPGA_WAIT
 CONFIG_SYS_FSL_BMAN_ADDR
 CONFIG_SYS_FSL_BMAN_OFFSET
-CONFIG_SYS_FSL_CCSR_GUR_BE
-CONFIG_SYS_FSL_CCSR_GUR_LE
-CONFIG_SYS_FSL_CCSR_SCFG_BE
-CONFIG_SYS_FSL_CCSR_SCFG_LE
 CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR
 CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR
 CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR
@@ -781,7 +730,6 @@ CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET
 CONFIG_SYS_FSL_CORENET_SERDES_ADDR
 CONFIG_SYS_FSL_CORENET_SERDES_OFFSET
 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
-CONFIG_SYS_FSL_CORES_PER_CLUSTER
 CONFIG_SYS_FSL_CPC_ADDR
 CONFIG_SYS_FSL_CPC_OFFSET
 CONFIG_SYS_FSL_CSU_ADDR
@@ -791,7 +739,6 @@ CONFIG_SYS_FSL_DCSR_DDR_ADDR
 CONFIG_SYS_FSL_DDR2_ADDR
 CONFIG_SYS_FSL_DDR3_ADDR
 CONFIG_SYS_FSL_DDR_ADDR
-CONFIG_SYS_FSL_DDR_INTLV_256B
 CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
 CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
 CONFIG_SYS_FSL_DSPI_BE
@@ -803,10 +750,8 @@ CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
 CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
 CONFIG_SYS_FSL_ERRATUM_A008751
 CONFIG_SYS_FSL_ESDHC_ADDR
-CONFIG_SYS_FSL_ESDHC_BE
 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
-CONFIG_SYS_FSL_ESDHC_LE
 CONFIG_SYS_FSL_ESDHC_NUM
 CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
 CONFIG_SYS_FSL_FM
@@ -833,8 +778,6 @@ CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET
 CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET
 CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET
 CONFIG_SYS_FSL_GUTS_ADDR
-CONFIG_SYS_FSL_IFC_BE
-CONFIG_SYS_FSL_IFC_LE
 CONFIG_SYS_FSL_ISBC_VER
 CONFIG_SYS_FSL_JR0_ADDR
 CONFIG_SYS_FSL_JR0_OFFSET
@@ -848,8 +791,6 @@ CONFIG_SYS_FSL_OCRAM_SIZE
 CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 CONFIG_SYS_FSL_PAMU_OFFSET
 CONFIG_SYS_FSL_PCIE_COMPAT
-CONFIG_SYS_FSL_PEX_LUT_BE
-CONFIG_SYS_FSL_PEX_LUT_LE
 CONFIG_SYS_FSL_PMIC_I2C_ADDR
 CONFIG_SYS_FSL_PMU_ADDR
 CONFIG_SYS_FSL_PMU_CLTBENR
@@ -1003,7 +944,6 @@ CONFIG_SYS_MAMR
 CONFIG_SYS_MASTER_CLOCK
 CONFIG_SYS_MATRIX_EBI0CSA_VAL
 CONFIG_SYS_MATRIX_EBICSA_VAL
-CONFIG_SYS_MAX_FLASH_SECT
 CONFIG_SYS_MAX_I2C_BUS
 CONFIG_SYS_MAX_NAND_CHIPS
 CONFIG_SYS_MAX_NAND_DEVICE
@@ -1015,11 +955,8 @@ CONFIG_SYS_MCKR1_VAL
 CONFIG_SYS_MCKR2_VAL
 CONFIG_SYS_MCKR_CSS
 CONFIG_SYS_MDIO1_OFFSET
-CONFIG_SYS_MEMAC_LITTLE_ENDIAN
 CONFIG_SYS_MEMORY_BASE
-CONFIG_SYS_MEMORY_SIZE
 CONFIG_SYS_MEM_RESERVE_SECURE
-CONFIG_SYS_MEM_SIZE
 CONFIG_SYS_MFD
 CONFIG_SYS_MHZ
 CONFIG_SYS_MIPS_TIMER_FREQ
@@ -1183,7 +1120,6 @@ CONFIG_SYS_OBIR
 CONFIG_SYS_OMAP_ABE_SYSCK
 CONFIG_SYS_ONENAND_BASE
 CONFIG_SYS_ONENAND_BLOCK_SIZE
-CONFIG_SYS_OR_TIMING_MRAM
 CONFIG_SYS_OSCIN_FREQ
 CONFIG_SYS_OSPR_OFFSET
 CONFIG_SYS_PACNT
index 9f2339666a7c9af92242866ca8e9e008ee495770..005e7362a31ab54a998ea91909a4bdaf6dbbdcb1 100644 (file)
@@ -198,7 +198,9 @@ hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl
 HOSTCFLAGS_mkexynosspl.o := -pedantic
 
 HOSTCFLAGS_kwboot.o += -pthread
-HOSTLDLIBS_kwboot += -pthread -ltinfo
+HOSTLDLIBS_kwboot += -pthread
+HOSTLDLIBS_kwboot += \
+       $(shell pkg-config --libs tinfo 2> /dev/null || echo "-ltinfo")
 
 ifdtool-objs := $(LIBFDT_OBJS) ifdtool.o
 hostprogs-$(CONFIG_X86) += ifdtool
@@ -242,7 +244,10 @@ hostprogs-$(CONFIG_MIPS) += mips-relocs
 hostprogs-$(CONFIG_ASN1_COMPILER)      += asn1_compiler
 HOSTCFLAGS_asn1_compiler.o = -idirafter $(srctree)/include
 
-HOSTLDLIBS_mkeficapsule += -lgnutls -luuid
+HOSTCFLAGS_mkeficapsule.o += \
+       $(shell pkg-config --cflags gnutls uuid 2> /dev/null || echo "")
+HOSTLDLIBS_mkeficapsule += \
+       $(shell pkg-config --libs gnutls uuid 2> /dev/null || echo "-lgnutls -luuid")
 hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule
 
 # We build some files with extra pedantic flags to try to minimize things
index bab5d17b7de19e877074ed828e626b2a08468858..56200bd9276d7117c6b7a904a61856b92669fa2f 100644 (file)
 #define pr_warn(fmt, args...)  fprintf(stderr, pr_fmt(fmt), "warning", ##args)
 #define pr_info(fmt, args...)  fprintf(stderr, pr_fmt(fmt), "info", ##args)
 
+#if defined(LIBRESSL_VERSION_NUMBER)
+#define RSA_get0_n(key) (key)->n
+#define RSA_get0_e(key) (key)->e
+#define RSA_get0_d(key) (key)->d
+#endif
+
 struct __packed toc0_key_item {
        __le32  vendor_id;
        __le32  key0_n_len;