3.4-stable patches

added patches:
	ssb-implement-spurious-tone-avoidance.patch

diff --git a/queue-3.4/series b/queue-3.4/series
index fe2b70fd10c37bfef1ae70ff7d1fb6489a264556..7162450e0634d01ca330942f9af0b7092bec78ef 100644 (file)
--- a/queue-3.4/series
+++ b/queue-3.4/series
@@ -13,3 +13,4 @@ arm-7696-1-fix-kexec-by-setting-outer_cache.inv_all-for-feroceon.patch
 arm-7698-1-perf-fix-group-validation-when-using-enable_on_exec.patch
 ath9k_htc-accept-1.x-firmware-newer-than-1.3.patch
 ath9k_hw-change-ar9580-initvals-to-fix-a-stability-issue.patch
+ssb-implement-spurious-tone-avoidance.patch

diff --git a/queue-3.4/ssb-implement-spurious-tone-avoidance.patch b/queue-3.4/ssb-implement-spurious-tone-avoidance.patch
new file mode 100644 (file)
index 0000000..2e6cc70
--- /dev/null
+++ b/queue-3.4/ssb-implement-spurious-tone-avoidance.patch
@@ -0,0 +1,90 @@
+From 46fc4c909339f5a84d1679045297d9d2fb596987 Mon Sep 17 00:00:00 2001
+From: Rafał Miłecki <zajec5@gmail.com>
+Date: Tue, 2 Apr 2013 15:57:26 +0200
+Subject: ssb: implement spurious tone avoidance
+
+From: Rafał Miłecki <zajec5@gmail.com>
+
+commit 46fc4c909339f5a84d1679045297d9d2fb596987 upstream.
+
+And make use of it in b43. This fixes a regression introduced with
+49d55cef5b1925a5c1efb6aaddaa40fc7c693335
+b43: N-PHY: implement spurious tone avoidance
+This commit made BCM4322 use only MCS 0 on channel 13, which of course
+resulted in performance drop (down to 0.7Mb/s).
+
+Reported-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Signed-off-by: John W. Linville <linville@tuxdriver.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/net/wireless/b43/phy_n.c          |    3 ++-
+ drivers/ssb/driver_chipcommon_pmu.c       |   29 +++++++++++++++++++++++++++++
+ include/linux/ssb/ssb_driver_chipcommon.h |    2 ++
+ 3 files changed, 33 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/wireless/b43/phy_n.c
++++ b/drivers/net/wireless/b43/phy_n.c
+@@ -4582,7 +4582,8 @@ static void b43_nphy_pmu_spur_avoid(stru
+ #endif
+ #ifdef CONFIG_B43_SSB
+       case B43_BUS_SSB:
+-              /* FIXME */
++              ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
++                                          avoid);
+               break;
+ #endif
+       }
+--- a/drivers/ssb/driver_chipcommon_pmu.c
++++ b/drivers/ssb/driver_chipcommon_pmu.c
+@@ -645,3 +645,32 @@ u32 ssb_pmu_get_controlclock(struct ssb_
+               return 0;
+       }
+ }
++
++void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
++{
++      u32 pmu_ctl = 0;
++
++      switch (cc->dev->bus->chip_id) {
++      case 0x4322:
++              ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
++              ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
++              ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
++              if (spuravoid == 1)
++                      ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
++              else
++                      ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
++              pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
++              break;
++      case 43222:
++              /* TODO: BCM43222 requires updating PLLs too */
++              return;
++      default:
++              ssb_printk(KERN_ERR PFX
++                         "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
++                         cc->dev->bus->chip_id);
++              return;
++      }
++
++      chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
++}
++EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
+--- a/include/linux/ssb/ssb_driver_chipcommon.h
++++ b/include/linux/ssb/ssb_driver_chipcommon.h
+@@ -219,6 +219,7 @@
+ #define SSB_CHIPCO_PMU_CTL                    0x0600 /* PMU control */
+ #define  SSB_CHIPCO_PMU_CTL_ILP_DIV           0xFFFF0000 /* ILP div mask */
+ #define  SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT     16
++#define  SSB_CHIPCO_PMU_CTL_PLL_UPD           0x00000400
+ #define  SSB_CHIPCO_PMU_CTL_NOILPONW          0x00000200 /* No ILP on wait */
+ #define  SSB_CHIPCO_PMU_CTL_HTREQEN           0x00000100 /* HT req enable */
+ #define  SSB_CHIPCO_PMU_CTL_ALPREQEN          0x00000080 /* ALP req enable */
+@@ -661,5 +662,6 @@ enum ssb_pmu_ldo_volt_id {
+ void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
+                            enum ssb_pmu_ldo_volt_id id, u32 voltage);
+ void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
++void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
+ 
+ #endif /* LINUX_SSB_CHIPCO_H_ */