clk: imx: composite-7ulp: Check the PCC present bit

When some module is disabled by fuse, its PCC PR bit is default 0 and
PCC is not operational. Any write to this PCC will cause SError.

Fixes: b40ba8065347 ("clk: imx: Update the compsite driver to support imx8ulp")
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240607133347.3291040-4-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c
index e208ddc511339ea398d15bcf7055e1daf8ed4502..db7f40b07d1abf3321eac0951fceb8ed0f09a497 100644 (file)
--- a/drivers/clk/imx/clk-composite-7ulp.c
+++ b/drivers/clk/imx/clk-composite-7ulp.c
@@ -14,6 +14,7 @@
 #include "../clk-fractional-divider.h"
 #include "clk.h"
 
+#define PCG_PR_MASK            BIT(31)
 #define PCG_PCS_SHIFT  24
 #define PCG_PCS_MASK   0x7
 #define PCG_CGC_SHIFT  30
@@ -78,6 +79,12 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name,
        struct clk_hw *hw;
        u32 val;
 
+       val = readl(reg);
+       if (!(val & PCG_PR_MASK)) {
+               pr_info("PCC PR is 0 for clk:%s, bypass\n", name);
+               return 0;
+       }
+
        if (mux_present) {
                mux = kzalloc(sizeof(*mux), GFP_KERNEL);
                if (!mux)